2010 Asia Pacific Conference on Circuits and Systems (APCCAS2010)6 - 9 December 2010, Kuala Lumpur, Malaysia

Space Vector PWM for PMSM Simulation usingMatlab Simulink

Anas Mohd Nazlee∗, Nor Hisham Hamid†, Fawnizu Azmadi Hussin‡ and Noohul Basheer Zain Ali§

Electrical and Electronics Engineering DepartmentUniversiti Teknologi PETRONAS

Tronoh, Perak Darul RidzuanMalaysia

∗anas_g01319@utp.edu.my†hishmid@petronas.com.my‡fawnizu@petronas.com.my

§noohulbasheer_zainali@petronas.com.my

Abstract—Space Vector PWM (SVPWM) model is often builtbased on high-level functions and verified based on the outputof the inverter or the model of the electrical motor with bestpossible accuracy. However, SVPWM implementation on digitalhardware such as Field Programmable Gate Array (FPGA)and Application-specific Integrated Circuit (ASIC) is constrainedby the limited resources and computation accuracy in thesedigital hardware compared to the mathematical model. The paperproposed a method that utilizes Matlab Simulink and Fixed-PointToolbox to construct hardware-amenable SVPWM model. Usingthe proposed model, it is possible to estimate the digital hardwareresources used and analyze the accuracy of the system beforethe actual designing process takes place. The model has beensimulated and verified with signal switching patterns and outputsignals from the model of the electrical motor. Based on functionalcomparisons, it was found that the outputs of the SVPWM modelare almost identical to the digital hardware implementation.

Index Terms—Digital control, simulation model, field pro-grammable gate arrays (FPGA), space vector pulse-width mod-ulation (SVPWM)

I. I NTRODUCTION

Space Vector Pulse Width Modulation (SVPWM) is a formof Pulse Width Modulation (PWM) proposed in mid-1980swhich was claimed to be more efficient compared to naturaland regular sampled PWM [1]. SVPWM has been the subjectresearch interest in further the efficiency, hence, many workshave been done especially in improving the algorithm andhardware implementation.

For hardware implementation to have a better efficiency, thecomputation accuracy for the hardware has to be within theacceptable range to produce the needed output. The resourcesin hardware is normally limited such as in Field ProgrammableGate Array (FPGA) and Application-specific Integrated Circuit(ASIC), thus the usage of resources for the implementationmust be optimum. The hardware must be part of a completesystem that utilizes the efficiency of the hardware. SVPWMis normally implemented as part of Field-Oriented Control(FOC) to efficiently control the PMSM based on the referencespeed. Before the SVPWM is implemented in hardware,simulation is done to understand the behavioral model.

This paper presents high-level behavioral SVPWM modelthat able to predict the usage of resources for hardware im-plementation. In most cases [2]–[5], conventional model doesnot reflect the true hardware requirement for implementation.The proposed high-level behavioral model was developed togive early estimation of the resources used and provide earlyanalysis of the accuracy needed based on the number ofbits specified to be used. The information from the modelcould be used in drafting microarchitecture specification sincethe model is built as the most accurate hardware amenablemathematical functions.

II. REALIZATION OF SVPWM

The concept of SVPWM for implementation is explained inthis section. The mathematical equations model the behaviorof SVPWM, thus it is important to realize the role of eachequation.

A. SVPWM Control

The basic principle of SVPWM is based on the eight switchcombinations for three-phase inverter. The switch combina-tions can be represented as binary codes that correspondsto the top switch transistors (S1, S3 and S5) of the inverteras shown in Fig. 1. The combinations are used to representvoltage vectors that are~V0(000), ~V1(100), ~V2(110), ~V3(010),~V4(011), ~V5(001), ~V6(101) and ~V7(111), where 1 indicate theupper switch (e.g. S1) is ’open’ while at the same time thelower switch (e.g. S2) is ’close’.

Six of the voltage vectors (~V1 − ~V6) are working states thatform stationary vectors in theαβ frame and divide the plane

Fig. 1. Switches configuration of three-phase inverter

2010 Asia Pacific Conference on Circuits and Systems (APCCAS2010)6 - 9 December 2010, Kuala Lumpur, Malaysia

Fig. 2. Voltage vectors and sectors inαβ frame

into six sectors with each having an angle of 60 degree, whiletwo of the voltage vectors (~V0 and ~V7) are zero states andconsidered as null vectors situated at the origin of the plane.Based on the stationary vectors and null vectors, a referencevector ( ~Vref ) is formed as shown in Fig. 2 using geometrysummation and can be expressed mathematically as

~Vref =T~Vk

TS

~Vk +T~Vk+1

TS

~Vk+1 (1)

where in (1),T~Vk

is the time for which the vector~Vk is selected(referred as ’dwelling time’),k + 1 is referred as the nextvoltage vector andTS is the switching period. The switchesof the inverter are then controlled according to the voltagevector at the given time with respect to the switching period.

B. Balanced Three-phase to Stationary Reference Frame

In SVPWM, αβ frame is used instead of the three-phaseaxisa− b− c as shown in Fig. 2. The transformation involvedis known as the Clarke Transformation. For balanced three-phase system, the sum of the three currents (ia, ib and ic)adds up to zero since the loads do not have a neutral returnpath thus it is possible to project a reference frame rather thanusing thea − b − c axes as reference. In the case of theαβframe is stationary, the projection of the phasea axis forms thereferenceα axis and the second axis (β) is defined as beingorthogonal to theα axis. The transformation is represented as

[

Vα

Vβ

]

=2

3·[

1 − 1

2− 1

2

0√3

2−

√3

2

]

·

va

vb

vc

(2)

The value ofVα andVβ becomes the input for the SVPWMin dwelling time calculation. The voltage inputs (Vα andVβ)are normally required to compute the scalar value of referencevoltage,|~Vref | using the formula

|~Vref | =2

3·Mi ·

√

V 2α + V 2

β (3)

As the maximum value for|~Vref | is 2

3VDC and Mi is the

modulation index to avoid overmodulation.

C. SVPWM Dwelling Time Calculation

As explained in II-A, ~Vref is derived based on the stationaryvoltage vectors that are adjacent (~Vk and ~Vk+1) to the ~Vref .The dwelling time for the voltage vectors are computed basedon the ~Vref angle (θ) with respect to theα axis and the sectorin which ~Vref resides at the given time. The angle,θ is definedin trigonometric function as

θ = tan−1(Vβ

Vα

) (4)

The angle value is used to determine the sector (k) in which~Vref is located at the given time. The values|~Vref |, θ andk

are then used to calculate the dwelling time for the voltagevectors in each sector. The dwelling time can be evaluatedusing the equations:

T~Vk

= C ·(

sink

3π · cos θ − cos

k

3π · sin θ

)

(5)

T~Vk+1= C·

(

− cos θ · sin k − 1

3π + sin θ · cos k − 1

3π

)

(6)

T~V0,~V7= TS − T~Vk

− T~Vk+1(7)

C =

√3 · |~Vref | · TS

VDC

(8)

The dwelling times calculated based on (5), (6) and (7) areapplied to the switches to produce SVPWM switching patternsbased on the sector [1] as shown in Table I. The switchingtime is arranged according to the first half of the switchingperiod (TS/2) with the other half as the reflection formingsymmetrical pattern.

III. PROPOSED HIGH-LEVEL BEHAVIORAL SVPWMMODEL

In order to construct a simulation model for hardwareimplementation, the proposed model has to be functional andsuited as a hardware reference model. The components have tobe compatible as to describe the digital hardware itself such asinputs, outputs, global clock pulses, storages, arithmetic logicoperations, datapath, and control unit.

A conventional model is built based on [6] as a referenceplatform. The conventional model is constructed in modularform for it to be replaced module-by-module with the proposedmodel and for debugging purposes. The proposed model ofSVPWM shown as in Fig. 3 consists of a few modules:

• Coefficientmodule is used to computeC as in (8).• Triangle Wave Generatormodule is used to generate

symmetrical triangle signal as reference based on globalclock and counters.

• Trigonometric Functionmodule is a trigonometric mod-ule based on either Look-Up Table (LUT) method orCoordinate Rotation Digital Computer (CORDIC) algo-rithm.

• Dwelling Time Calculationmodule is a computationmodule for (5), (6) and (7).

2010 Asia Pacific Conference on Circuits and Systems (APCCAS2010)6 - 9 December 2010, Kuala Lumpur, Malaysia

TABLE ISWITCHING TIME CALCULATION FOR EACH SECTOR [1]

Sector,n Upper Switches (S1,S3,S5) Lower Switches (S2,S4,S6)

S1 =T~V1+ T~V2

+ T~V7/2 S2 =T~V0

/2

1 S3 =T~V2+ T~V7

/2 S4 =T~V0/2 + T~V1

S5 =T~V7/2 S6 =T~V0

/2 + T~V1+ T~V2

S1 =T~V2+ T~V7

/2 S2 =T~V0/2 + T~V3

2 S3 =T~V3+ T~V2

+ T~V7/2 S4 =T~V0

/2

S5 =T~V7/2 S6 =T~V0

/2 + T~V3+ T~V2

S1 =T~V7/2 S2 =T~V0

/2 + T~V3+ T~V4

3 S3 =T~V3+ T~V4

+ T~V7/2 S4 =T~V0

/2

S5 =T~V4+ T~V7

/2 S6 =T~V0/2 + T~V3

S1 =T~V7/2 S2 =T~V0

/2 + T~V5+ T~V4

4 S3 =T~V4+ T~V7

/2 S4 =T~V0/2 + T~V5

S5 =T~V5+ T~V4

+ T~V7/2 S6 =T~V0

/2

S1 =T~V6+ T~V7

/2 S2 =T~V0/2 + T~V5

5 S3 =T~V7/2 S4 =T~V0

/2 + T~V5+ T~V6

S5 =T~V5+ T~V6

+ T~V7/2 S6 =T~V0

/2

S1 =T~V1+ T~V6

+ T~V7/2 S2 =T~V0

/2

6 S3 =T~V7/2 S4 =T~V0

/2 + T~V1+ T~V6

S5 =T~V6+ T~V7

/2 S6 =T~V1+ T~V0

/2

• Switching Timemodule implemented equation as in TableI with triangle wave signal as reference.

The proposed model make use of Matlab Fixed-Point Tool-box to format the output of computation as fixed-point with thespecified number of bits. In the case of SVPWM, the numberof bits determines the accuracy of dwelling time calculation.The proposed model is constructed as such for the developer

Fig. 4. Simulation model of Coefficient block

to estimate the accuracy needed for the design. An exampleof one of the modules is illustrated in Fig. 4.

All the blocks in Fig. 4 have output attribute based on theFixed-Point Toolbox. The numbers of bits that are specifiedin the fixed-point format are word length and fraction length.The computation is then constrained to the specified fixed-point format. The module is built with discrete mathematicaloperators to estimate the resources used at the given time.After all of the modules are configured with the same outputattribute, the functionality of the model is then tested withspecific configuration to the system.

The functionality of the proposed model is validated inField-Oriented Control (FOC) system. The input of the FOCsystem is the speed reference for the motor in rotation perminute (rpm) and the PMSM model used is based on MatlabSimulink preset. The FOC model and SVPWM model areconfigured according to the variables:

• Speed reference,ωref = 3000 rpm• PMSM preset model = 01: 0.8 Nm 300 Vdc 3000 rpm• Load torque,Tm = 0 Nm• Global clock frequency,FCLK = 50 MHz• Switching frequency,FS = 10 KHz• Modulation index,Mi = 0.6• Voltage supply,VDC = 300 V• Fraction length = 16 bits

The results of the simulation are observed and recorded usingthe component Scope in Matlab Simulink. The detail of theresults are presented and discussed further in the Section IV.

Fig. 3. Simulation model of SVPWM

2010 Asia Pacific Conference on Circuits and Systems (APCCAS2010)6 - 9 December 2010, Kuala Lumpur, Malaysia

Fig. 5. (a)SVPWM signal switching pattern (b)PMSM model output

IV. RESULTS AND DISCUSSIONS

The proposed model is verified based on the output ofthe SVPWM signal switching pattern, stator currents, rotationspeed and electromechanical torque as shown in Fig. 5. InFig. III, the Scope output has displayed from the top trianglereference signal, signals to the upper switches (S1, S3 and S5)and at the bottom is the sector in which~Vref located. Whilein Fig. III, the Scope output has displayed from the top statorcurrents, rotation speed and at the bottom is electromechanicaltorque.

As explained earlier in Section II-A, the voltage vectorscorrespond to a switch combination and the value 1 indicatesthe switch is open or in other word turned off. The switchesin ’Universal Bridge’ component in Simulink are turned offby sending a low signal or logical 0. As shown in Fig. III,the switches timing is dependent on the triangle wave signal.Whenever the value of the triangle wave counter more thanthe value of calculated switch time, the signal for the switch ischanged from high to low. The signal generated is accordingto the respective sector.

The stator currents in Fig. III shows a coarse sinusoidalwaveform as a result from a system with no filter to counteractthe PWM switching feedback. It is also affected by the limitedaccuracy of the fixed-point format in the SVPWM computa-tion. This is proven as the digital design model computed thevalue3.4641e − 004 for the dwelling time as3.3570e − 004because of the limited fraction length in the fixed-point format.Regardless, the system was able to produce a good responsewith the ability to reach the reference speed in less than 0.005second. The electromechanical torque remained at zero asthere is no load torque provided on the motor.

Based on the proposed model, the conventional algorithmused the majority resources in multipliers and dividers forthe computation to maximize the adaptivity. Some of theprocesses could be done in parallel, such as computing thecoefficient and running trigonometric function at the sametime. In the initial attempt in constructing the model,TriangleWave Generatormodule was built using up-down counter toproduce the triangle signal. As a result, the simulation tooka long time to finish. It is then replaced with up-down rampsignal to provide much faster time in simulation.

V. CONCLUSION AND FUTURE WORK

To maximize the usage of Matlab in modeling and simu-lation, a high-level behavioral model is proposed to benefitdigital design simulation when implementing a theory. Theproposed model has been successfully constructed and veri-fied according to the signal pattern and the motor response.Even though the proposed model is a bit more tedious tobe built compared to the conventional model, the proposedmodel provided more information and analysis for hardwareimplementation compared to the conventional model basedon [6]. The simulation results provided early estimation andexpectation of the design, thus some of the issues in hardwareimplementation might be solved earlier in the design phase.

The research would proceed with in-depth analysis of theproposed model such as varying the fraction length to study theeffect on the proposed model, comparing the Total HarmonicDistortion with the conventional model and the output withthe hardware implementation.

ACKNOWLEDGMENT

This research project is funded by Malaysia Ministry of Sci-ence, Technology and Innovation through TechnoFund grantTF1008C130.

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