Solar Probe Plus FIELDS

Quarterly ManagementDCB_RFS-ADC

July 18, 2013

FPGA Daughter Board Development

• FPGA ETU Daughter board schematics and layout completed– This board houses the Actel/Microsemi reprogrammable FPGA (ProASIC3000)– Fabrication and population scheduled to accommodate integration with DCB-RFS_ADC ETU1– HDLP Connectors delivery expected in September, 2013

Daughter board de-insertion hardwareETU FPGA Daughter board layout

3

DCB/RFS_ADC ETU1 Development

• DCB_RFS-ADC Schematics Completed– Schematic Review held in June, 2013– BOM released and parts have been ordered

• DCB_RFS-ADC PCB Layout CompletedBoards can be driven by the RFS Frontend ETU1 boards (will be eventually integrated during the ETU2 stage)

FPGA Daughter Bd CPU Memory: SRAM, EEPROM & PROM

FLASH

RFS Memory (SRAM)

RFS ADCs and Data Buffers

Instrument & LNPS I/Fs

S/C I/F

We are checking the layout & expect to have boards in August, 2013.

DCB/RFS_ADC ETU1 BOM

• Most parts are “flight-like” or high-fidelity commercial equivalents on order• Linear Power supply (non-flight) replaces LNPS for ETU1

• Digital I/F to LNPS is included• Instrument I/Fs (to DFB, AEB and MAG-O) are included

• HDLP Connectors (mother to daughter board) may be the gating item • But FPGA Development/Simulation is ongoing during this “waiting period”

• Design & fabrication of an SRAM adapter (for use of commercial parts) is underway

Item Qty Part / Value Function Part No. Footprint Reference Designators58 2 Mini-Circuits TT1-6-KK81+ transformer/balun XFMR_TT1-6-KK81 T100, T10159 2 HXSR01632 SRAM 512Kby32 HXSR01632D_H HXSR01632 U101, U10060 1 79LV0408 EEPROM 512Kby8 79LV0408RT4FX20 79LV0408 U10261 1 UT28F256LVQLE PROM 32Kby8 UT28F256LVQLE CFP28 U10362 8 UT54ACS164245SEI buffer/driver UT54ACS164245SEI CFP48 U104, U105, U106, U107, U117, U119, U121, U12363 1 LM317 linear regulator TO-220-UP U10864 2 TPS72625 linear regulator SOT23-5 U109, U11265 1 LM2940T-5.0 linear regulator TO-220-UP U11066 1 LMS1587CS-3.3 linear regulator TO263-TS3B U11167 1 TPS72615 linear regulator SOT23-5 U11368 1 TPS72618 linear regulator SOT23-5 U11469 1 54AC14 inverter/schmitt trigger UT54ACS14E CFP14WB U11570 4 3DFN64G08VS8305MS FLASH Memory 3DFN64G08VS8305MS SOP50 U116, U118, U120, U12271 2 UT54LVDS032LV/E LVDS Driver UT54LVDS032LV-UC(A G or X) CFP16-04 U124, U12572 2 UT54LVDS031LV LVDS Receiver UT54LVDS031LV-UC(A G or X) CFP16-04 U126, U12773 2 RHF1201 A/D Converter 5962F0521701VXC SO-48 U128, U13274 2 SNJ54LVTH162374WD buffer/driver/latch SNJ54LVTH162374WD CFP48 U129, U13375 1 SN54LVC00A Fast NAND SN54LVC00A DIP14 U13076 1 UT54ALVC2525 Clock Driver/Buffer UT54ALVC2525-UC(A G or X) CFP14-04 U13177 1 ADC128S102 ADC/MUX 5962R0722701VZA CFP16-04 U13478 1 AD584 Voltage Ref AD584TH/883B AD584-TO-99 U13579 1 RH1078 OpAmp RH1078M RH1078M U13680 1 OSCILLATOR - 38.4 MHz Oscillator still need to identify flight part ECS-P73 Y100

DCB/RFS_ADC Revised Power Estimate

DCB and RFS have been combined into one board and one FPGARevised Power Estimates include scenarios for DCB (1.6W Avg) only and DCB with RFS subsystem (2.6W Avg). We expect to be able to operate without the ADC External Reference, but have included this as an option on ETU1

Part Type Part Num Qty Volt STDBY Curr/PerActCurr/PerWC Curr/PerTotal Curr WC Curr Normal PwrAvg Pwr WC Pwr PowerOSC 38.4MHz 1 3.3 0.0075 0.0075 0.015 0.008 0.015 0.02475 0.0495

SRAM-DCB HXSR01632 1 3.3 0.005 0.002 0.003 0.002 0.003 0.0066 0.0099 full IC WCSRAM-DCB HXSR01632 1 1.8 0.002 0.01 0.035 0.010 0.035 0.018 0.063 0.0246 0.0729SRAM-RFS HXSR01632 1 3.3 0.005 0.002 0.01 0.002 0.010 0.0066 0.033SRAM-RFS HXSR01632 1 1.8 0.002 0.02 0.15 0.020 0.150 0.036 0.27 0.0426 0.303

FPGA RT54SX4000SL (DC) 1 3.3 0.055 0.07 0.07 0.070 0.070 0.231 0.231 0.231 0.231 FPGA 3.31 1.5 0.175 0.175 0.425 0.175 0.425 0.2625 0.6375 0.2625 0.6375 FPGA 1.5

Linear Reg (1.8V to 1.5V) 1 1.8 0.0525 0.1275

0.4935 0.8685 TOTAL FPGAROM UT28F256LVQLE 1 3.3 0.001 0.02 0.04 0.020 0.040 4MHz operation 0.0033 0.066 0.132

MAG BUFFER UT54ACS164245SEI 1 3.3 0.004 0.015 0.025 0.015 0.025 MAG Signal Accrued F (MHz) 5 0.0495 0.0825DFB & TDS BUFFER UT54ACS164245SEI 1 3.3 0.004 0.12 0.2 0.120 0.200 DFB & TDS Acrrued F (MHz) 40 0.396 0.66AEB BUF1 UT54ACS164245SEI 1 3.3 0.004 0.003 0.005 0.003 0.005 AEB Synch + Misc Sigs 1 0.0099 0.0165AEB/LNPS BUF UT54ACS164245SEI 1 3.3 0.004 0.003 0.005 0.003 0.005 LNPS Synch + Misc Sigs 1 0.0099 0.0165FLASH BUFFERS UT54ACS164245SEI 2 3.3 0.004 0.024 0.04 0.048 0.080 LNPS Synch + Misc Sigs 8 0.1584 0.264

LVDS Drivers UT54LVDS031LV 2 3.3 0.003 0.012 0.018 0.024 0.036 0.0792 0.1188LVDS Receivers UT54LVDS032LV 2 3.3 0.004 0.012 0.015 0.024 0.030 0.0792 0.099

Buff/ST 54AC14DMQB 1 3.3 0.001 0.005 0.001 0.005 0.0033 0.0165

FLASH 4 3.3 0.03 0.045 0.030 0.045 0.099 0.1485Switches transistor pair 4 3.3 0 0.005 0.005 0.005 0.005 0.004 0.008

EEPROM 1 3.3 0.004 0.010 0.040 0.010 0.040 0.033 0.132

HSKPADC 1 4 0.000001 0.0015 0.0015 0.002 0.002 0.006 0.006

Linear Reg (4.0V to 2.5V)ADC Component 1 4 0.12 0.171

RFS ADC Buffers SNJ54LVTH162374WD 2 3.3 0.001 0.005 0.020 0.010 0.040 0.033 0.132

RFS Clock Drivers UT54ALVC2525 1 3.3 0.025 0.030 0.035 0.030 0.035 0.099 0.1155

RFS Nand/Buffer SN54LVC00A 1 3.3 0.001 0.015 0.030 0.015 0.030 0.0495 0.099

RFS ADCs RHF12012 2.5 0.010 0.040 0.057 0.080 0.114 0.2 0.2852 2.5 0.003 0.003 0.003 0.006 0.006 0.015 0.0152 3.3 0.008 0.010 0.015 0.020 0.030 0.066 0.099

VREF CircuitREFERENCE IC AD584 1 5 0.00075 0.001 0.001 0.001 0.001 0.005 0.005opAmp LTC2054HV 1 5 < 1mA < 1mA < 1mARef Drive VREF - via transistor 1 2.5 0.065 0.065 0.065 0.065 0.065 0.1625 0.1625

INCM - via transistor 1 2.5 0.025 0.025 0.025 0.025 0.025 0.0625 0.0625Linear Reg (4.0V to 2.5V)VREF Component 1 4 0.135 0.135

TOTAL FOR DCB/RFS 2.57885 4.4032

TOTAL FOR DCB ONLY 1.63135 3.1217

TOTAL FOR RFS ONLY 0.8275 1.1105

0.4625 0.7455TOTAL FOR RFS w/o external REFERENCE DRIVER:

DCB/RFS_ADC FPGA

DCB related subsystems are well-known (Coldfire Processor has been used for the MAVEN DCB). The DCB portion of FPGA utilization is estimated at approximately 30%.RFS utilization estimated at approximately 40% of the FPGA gates. FPGA SRAM is allocated for filter coefficients and high-speed temporary storage.

RFS SRAM5 1 2 K x 3 2

A d d r[ 2 0 : 2 ]D a t a [ 3 1 : 0 ]

C S / B E _ R A M [ 3 : 0 ]

A D C

A M U X

T / H

Ho u s ekeep in g

H A D C C n t l

A H K [ 7 : 0 ]

H A D C D a t O u t

EEPROM5 1 2 K x 8D a t a [ 7 : 0 ]

A d d r[ 1 6 : 0 ]C S _ N V R A M [ 3 : 0 ]

S/C_TLM_B

RFS Su bsystem

CPU SRAM5 1 2 K x 3 2

A d d r[ 2 0 : 2 ]D a t a [ 3 1 : 0 ]

C S / B E _ R A M [ 3 : 0 ]

to EEPROMs

LV D S

fromInstruments

DCB/RFS FPGA

P o w er-O nR eset 3 8 .4 M H z

C o l d fi reP ro cesso r

T i mek eep i n g

S /C I / F

O S C

M emo ryC o n t /A rb

D M A C n tl

F L A S H C n tl

DFB, TDS,MAG (2) DFB, TDS,

MAG (2)

I n s t ru men t C n tl

R F S E n g i n e

FPGA/ Processor C ore H W R e s e t

M D A T[ 3 1 : 0 ]

S C Tlm _ AS C C m d _ A

M B U S C N TL

M A D R [ 2 0 :0 ]F L A S H C n t l

H A D C C n t l

C D I TL M [ 3 : 0 ]

L N P S C N TL [ 7 : 0 ]

C D I C M D [ 3 : 0 ]C D I C L K [ 3 : 0 ]

S C C m d _ B S C Tlm _ B

A E B C D [ 9 :0 ]

H A D C D a t I n

R D A T[ 3 1 : 0 ]R B U S C N TL

R F E C N TLR A D C D A T[ 1 1 : 0 ]R F E S Y N CR F E S TA T

R A D R [ 2 0 :0 ]

Analog HSKPfrom LNPS,AEB andDCB/RFS

LV D S

S/C_CMD_B

BOOT ROM 3 2 K x 8A d d r[ 1 4 : 0 ]

D a t a [ 7 : 0 ]

C S _ R O M

S/C_TLM_A

to InstrumentElectronics

to AEB

LV D S

FLASH

I n c lu d e s f o u r F L A S H P o we r S w it c h e s

3 2 G B y t e sI O [ 7 : 0 ]C n t l/ D e c o d e

LV D S

to LNPS

S/C_CMD_A