SOI EDA/IP OverviewJon Cheek

Executive Director

SOI Industry Consortium

SOI EDA/IP Overview

Apr/9, 2019 Silicon Valley Symposium 2

Substrates

Supply Chain & Eco-system

Technology

Foundry

EDA & IP

✓

✓

✓

© 2018 Cadence Design Systems, Inc. All rights reserved.3

Design Capabilities 22FDX 28FDS

Logic Simulation (Incisive®)

Dig

ital Im

ple

menta

tion a

nd S

ignoff

(RT

L to G

DS

)

Synthesis (Genus™)

Power Analysis (Joules™)

Test (Modus)

Place and Route (Innovus™)

Timing Analysis (Tempus™)

Extraction (Quantus™)

EM/IR Analysis (Voltus™)

Physical Verification (PVS)

Litho Physical Analysis (DFM/LPA)

Litho Electrical Analysis (DFM/LEA)

Chemical Mechanical Polishing (DFM/CMP)

Custo

m a

nd A

nalo

g

Desig

n

Schematic Editing (Virtuoso® VSE)

Analog Design Environment (Virtuoso ADE)

Layout System (Virtuoso VLS)

Circuit Simulation (Spectre® APS/XLS)

Electrically Aware Design (EAD)

EM/IR Analysis (Voltus-Fi)

Cadence EDA Enablement and Proof-Points for 22FDX and 28FDS

Certified

Enabled

Recent CES demos on 22FDX: Vision Processing;

Artificial Intelligence: Image Classification – Pedestrian

and Gender Detection

• NXP-Cadence-Samsung Foundry

28 FDS

• i.MX product line multiple tapeouts

• Cadence EDA Digital and Custom

tools, DIP and Tensilica HiFi 4 DSP

Silvaco Modeling

Apr/9, 2019 Silicon Valley Symposium 4

Apr/9, 2019 Silicon Valley Symposium 5

Apr/9, 2019 Silicon Valley Symposium 6

Apr/9, 2019 Silicon Valley Symposium 7

Apr/9, 2019 Silicon Valley Symposium 8

Apr/9, 2019 Silicon Valley Symposium 9

Apr/9, 2019 Silicon Valley Symposium 10

SOI Industry Consortium

Apr/9, 2019 Silicon Valley Symposium 11