Soft Switch Phase Shift

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Soft-Switched, Phase-Shifted Topology Cuts MOSFET Switching Stresses in FBCs

Power Electronics

Dr. Krishna Shenai and Malay Trivedi, The University of Illinois at Chicago

Tue, 2001-05-01 12:00

Circuit topology reduces switching power loss.

The full bridge converter (FBC) topology is widely used in medium-voltage, high frequency 1kW to 10kW

dc-dc power supplies. A typical example is a 350V/5V power supply used in computers and

telecommunication equipment. We use power metal oxide semiconductor field effect transistors

(MOSFETs) rated at 400V to 600V/10A to 50A in the full bridge at the input of the converter. Operation

of MOSFETs in a hard-switched FBC results in excessive device switching power loss especially at high

switching frequencies. Circuit and package parasitic inductances generally cause overvoltage stress. In

addition, the MOSFET body diode may undergo stressful reverse recovery under certain switching

conditions. The soft-switched phase-shifted FBC (PS-FBC) significantly reduces dynamic switching

stresses and offers high power conversion efficiency, constant operating frequency, and good EMI

characteristics. An advantage of PS-FBC is the reduction of switching power loss with a similar circuit

topology as the hard-switched FBC but with a distinct control strategy. The PS-FBC is popular for

switchmode power supplies in this power range.

You can see the schematic circuit diagram of the PS-FBC in Fig. 1. The switches M1 and M2 form the

lagging leg and M3 and M4 form the leading leg of the bridge. Experimentally demonstrated, this is a

well-established design procedure for this topology [1] .

You can see the current and voltage waveforms of the switches over one complete cycle in Fig. 2.

Resonance between the output capacitance of the FET and circuit parasitics during the switching

transients enables zero voltage switching (ZVS). The leakage inductance (Llk ) of the transformer controls

the switching of M3 and M4 , while the output filter inductor current reflected to the primary determines

that of M1 and M2 . Hence, the waveforms of M3 and M4 are distinct from those of M1 and M2 . M3 and

M4 don't conduct simultaneously, and their waveforms are similar over opposite halves of the switching

cycle. The same is true for M1 and M2 .

During ZVS, the inductors must completely charge/discharge the voltage-dependent output capacitors of

both switches in a leg (leading or lagging) as well as the transformer winding capacitance, CTR .

Accordingly, the minimum energy in Llk and primary current (I2 ) required for soft switching in the

leading leg are [1] :

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Where:

Coe3 (Coe4 )=Effective output capacitance of M3 (M4 )=4 / 3 Coss

Where:

Coss =Output capacitance when VDS =VIN

If Llk has less energy than Emin , the output capacitors are only partially charged/discharged. Turning the

MOSFET on in this condition causes a Cdv/dt shoot-through current spike through the leg. This current

surge in low-load conditions could lead to switch failure [2] . At energies higher than Emin , Llk facilitates

loss-less energy transfer between the output capacitors of M3 and M4 . The energy stored in the output

capacitor of each switch during turn-off recirculates into the circuit during turn-on.

The output filter inductor has much higher energy than Emin . It charges and discharges the output

capacitances of switches M1 and M2 approximately linearly. Thus, the ZVS operation of the leading leg is

lost earlier than that of the lagging leg. Hence, developers must design the switching transitions of M3

and M4 carefully for a wide ZVS range.

The energy in Llk increases rapidly at loads higher than the minimum load for ZVS. The voltage

transition of M3 and M4 takes place with a nearly constant dv/dt since the current that charges or

discharges the output capacitance increases at higher load levels. Assuming that the I2 splits equally

between M3 and M4 , the corresponding dv/dt is given by:

The gate drives of power MOSFETs typically have a finite gate resistance (RG ) that controls the transfer

of gate charge to and from the input capacitance. Generally, the turn-off current through the power

MOSFET has three components, as depicted in Fig. 3, on page 44. A dv/dt at the drain induces a current

ICo (=Coe dv/dt) through the output capacitor and a current ICf (=Cfe dv/dt) through the feedback

capacitor and the gate. Here, Cfe is the effective value of the voltage-dependent feedback capacitor (CGD ).

A remaining current (I2 -ICo -ICf ) flows through the FET channel. The gate current (ICf ) also flows

through the gate resistor (RG ) of the FET. At high load currents, the voltage drop across RG places an

upper limit on the dv/dt value. Thus,

Where:

VGn =Negative applied gate voltage

VGS,on =Gate-source voltage (VGS ) required to support the current IM through the channel in saturation.

Current flow through the FET channel and gate resistance of M3 and M4 represents a real loss during

switch turn-off. Turn-off energy increases with load current. Note, Coe primarily determines the dv/dt at

low-medium loads.

Gate voltage is at its low level (VGn ) during the turn-on transient. The energy in Coe (and to a lesser

extent Cfe ) recirculates into the circuit when the drain voltage falls. Since the channel doesn't support

external current, Coe almost entirely provides the turn-on energy of the switch with a value of 1/2Coe



Vin2 . Thus, the switch experiences ZVS turn-on if the energy in Llk is higher than Emin . The mismatch

between the turn-on and turn-off energies of the MOSFET results in switching loss at higher load

current.

The body diode of the MOSFET conducts the inductor current at the end of the turn-on transient. The

MOSFET is turned on after a dead time equal to one-fourth of the resonant period of Llk with the switch

output capacitance [1] . Once the switch turns on, the FET channel conducts reverse current in parallel

with the body diode, as depicted in Fig. 4, page 47. The diode on-state conduction is modeled as VD =VF

+ID RD , where VF is the turn-on voltage and RD is the diode series resistance. With an FET on-resistance

of RM , you can express the current through the diode as:

You express the voltage drop experienced during reverse conduction as VON =ID RD +(I2 -ID )RM . Most of

the reverse current flows through the FET channel during low load, the body diode primarily supports

the reverse current during high load. After the zero crossing of switch current, all current flows through

the FET channel and the voltage drop is simply given as I2 RM . Since the FET channel current also flows

through this low-resistance drift region, the value of RM is lower than the value obtained from the output

characteristics at the same current level. Excess charge in the body diode decays by recombination

during forward conduction phase. Considerable charge also sweeps out during the turn-off transient,

adding to turn-off power loss. Charge removal can lead to switch failure under high load conditions [3] .

Fig. 5 shows the influence of RG and I2 on the conduction and overall switching energy losses per cycle of

the switches M3 and M4 in a PS-FBC. The converter operates at 75 kHz with Llk =120J and VIN =300V.

The switches have ratings at 500V/20A. With measurements less than 2 J for the turn-on energy of the

switches, the turn-off process determines the overall switching energy loss and it's much higher than

the energy stored in the output capacitor alone. For a given FET, the choice of RG also affects the turn-off

loss. The switching loss is comparable to the conduction loss at the chosen switching frequency.

It's necessary to optimize power MOSFET technology to suit specific switching and reliability

considerations in the application [4-6] . Last year, the Power Electronics Reliability Group (PERG), was

founded for the development and commercialization of high-performance power supply technologies in

the emerging Internet age [7] .

References

1. J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C. Lee, and B. H. Cho, Design considerations for high-

voltage high-power full-bridge zero-voltage-switched PWM converter, in Proc. IEEE APEC, 1990,

pp. 275-284.

2. N. Keskar, M. Trivedi, and K. Shenai, Device Reliability and Robust Power Converter

Development, Microelectronics Reliability, Vol. 39, No. 6-7, pp. 1121-1130, June 1999.

3. H. Aigner, K. Dierberger, and D. Grafham, Improving the full-bridge phase-shift ZVT converter

for failure-free operation under extreme conditions in welding and similar applications, in Proc.

IEEE IAS Ann. Mtg., 1998.

4. K. Shenai, Made-to-Order Power, IEEE Spectrum, Vol. 37, No. 7, pp. 50-55, 2000.



5. K. Shenai, P. J. Singh, S. Rao, D. Sorenson, K. Chu, and G. Galyon, On the Reliability of DC-DC

Power Converters, Proc. IEEE IECEC, 2000, pp. 1480-1490.

6. K. Shenai, Power Semiconductor Manufacturers Need to Update MOSFET SOA, PCIM

Magazine, Dec. 2000.

7. URL: www.eecs.uic.edu/~shenai/perg.html.

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