SoC TAM Design to Minimize Test Application Time

Advisor Dr. Vishwani D. Agrawal

Committee Members Dr. Victor P. Nelson, Dr. Adit D. Singh

Apr 9, 2015

Master’s Project Defense Huiting Zhang

Outline

Background

IEEE 1500 Overview

Hardware Constraint of SoC testing

MILP Formulation (session-less and session-based)

Benchmark Introduction

Results

Limitation, future work, and conclusion

References

2Apr 9, 2015

Background

3

Whst is System On Chip

-More of a System not a Chip

-Large and Complex

~5-10 Million Gates

~1-64 MB memory

-Many complex subsystems

• Processor

• Graphics/communications/

• Memory

• Interface logic

• Analog

Apr 9, 2015

Background

4

.

-Reduced Space, higher device integration

-High performance

-Low power

-Hard to Design

-Lack of flexibility

-component testing needs access mechanism.

-lower yields

Apr 9, 2015

SoC Advantages:

SoC Disadvantages:

5

Testing of SoCSource – to apply test stimuliSink – to capture test resultsTAM – test access mechanism to transport test & its resultsWrapper – Interface between TAM and the embedded core

IEEE 1500 Overview

Apr 9, 2015

TAM Architecture

In this figure, Total TAM width of 7 is partitioned among three test buses.

TAM are modeled as TAM buses in this work.

The number of TAM correspond to the number of scan chains of each core, double

the TAM wires reduce the test time of the core to half.

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6

Rectangle Bin Packing Problem

Apr 9, 2015

Hardware Constraint of SoC Testing

Hardware compatibility between cores of each SoC is given by

benchmark[10], eg. {1,2,4} means module1, module2 and module 4 are

compatible.

Cores on different Voltage Island are

independent with each others, which

Means they could operate at different

Voltages at the same time.

Cores that share the same voltage

island need to operate in the same

voltage and frequency pair if they

are to be scheduled concurrently.

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Session-based and Sessionless

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How does the effect of these two differs in the benchmark?

10

MILP (Sessionless Test Scheduling)

Each pin choice corresponds to different TAM pins numbers

Apr 9, 2015

:

:

: 0

1, / ,

, , .

0, .

( )

( )

: , , 1

( ) ( )

( )

( )

( )pin C

t T tfinish F t

t T F t S t L t

t T S t

if test t are executed with nth v f pairs

Assign t n pin and assigned with TAM pin choice

Otherwise

t T Assign t n pin

: , ,( )* , ,( )

n N

n N pin C

t T L t Assign t n pin Lt n pin

This is the objective function of MILP

11

1, 1 2 1, 2

0,

1, 2 : 1, 2 2, 1 1

( )

1, 2 : 1 2 1 1, 2

1, 2 : 2 1 1, 2

1,

( ) ( )

( ) ( ) ( ( ))*

( ) (

1, 2

) ( )*

) (

l

l

If the test t finishes before t beginst t

Otherwise

t t T t t t t

t t T F t S t t t

t t T S t F t t t

If theComp t t

1 2

0,

( ) (1, 2 : 1, 2 2 ) (, 1 )1, 2

test t incompatible with t

compatible

t t T t t t t Comp t t

MILP (Sessionless Test Scheduling)

λL is the TAT of the longest possible test schedule

Apr 9, 2015

12

t1

t2

When two tests overlaps

1, 1 21, 2

0,

1, 2 : Overlap 1

Overlap( )

( ) (, 2 1 1, 2 2, 1) ( )

If the test t overlaps with tt t

Otherwise

t t T t t t t t t

MILP (Sessionless Test Scheduling)

Apr 9, 2015

13

1, 1 2 1, 2

0,

1, 2 :

( )

( ) ( ) ( ( ))*

( ) (

1 2 1 1, 2

1, 2 : 1 2 1, 2

: ,

(

)

) 1

) *

(

l

l

If test t starts earlier or when t startst t

Otherwise

t t T S t S t t t

t t T S t S t t t

t T t t

MILP (Sessionless Test Scheduling)

Apr 9, 2015

t1

t2

Eg. P(t2,t1)+ P(t2,t3)+ p(t2)<=Pboundt3

Constant power model is used for simplicity, peak power is used to

guarantee the accuracy, but somewhat make this design pessimistic

14

λp is the TAT of the longest possible test schedule

MILP (Sessionless Test Scheduling)

Apr 9, 2015

2

1 : ( 1) 1, 2

1, 2 : 1, 2 1, 2

1, 2 : 1, 2 2, 1

1, 2 : 1, 2 2, , 2,

1 1,

( )

( ) ( )*

( ) ( )*

( ) Assign( )*

( ( ))* (2 (1

t T

P

P

n N pin C

p

t T Pow t Pow t t Pbound

t t T Pow t t Overlap t t

t t T Pow t t t t

t t T Pow t t t n pin Pt n

Overlap t t t

)2 *, 1 ) pt

MILP (Sessionless Test Scheduling)

Apr 9, 2015 14

2

( )

( ) ( )*

( ) ( )*

( ) Assign( )*

( ( ))*

1 : ( 1) 1, 2

1, 2 : 1, 2 1, 2

1, 2 : 1, 2 2, 1

1, 2 : 1, 2 2, , 2,

1 1, 2 1 2( ,(

t T

Pin

Pin

n N pin C

pin

t T W t W t t Wbound

t t T W t t Overlap t t

t t T W t t t t

t t T W t t t n pin Wt pin

Overlap t t t

))* 1 pint

t1

t2

Eg. W(t2,t1)+ W(t2,t3)+ W(t2)<=Wboundt3

MILP (Sessionless Test Scheduling)

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1, 2 , : 1, , 2, , pin 1 1, 2

1, 2 , : 2, , 1, , pi

Assign( ) Assign( ) ( ( ))

Assign( ) Assign( ) ( ( ))n 1 1, 2

pin C pin C

pin C pin C

t t T n N t n pin t n overlap t t

t t T n N t n pin t n overlap t t

MILP (Session-based Test Scheduling)

(s) * (s, t, n, w)

(s, t

(s)

(s) (s) (s)

(s) (s

1) (s, t 2) 2 (t1,

1)

t 2)tnwL L final

Assign Assi

finish tf

tf

gn Com

t

p

s L

ts tf

16Apr 9, 2015

The decision variable ‘final’ contains 4 variables, which

makes the session-based Test scheduling a very slow process

1

1

vf_tam(t, n,pin) 1

( , ) 1

(s, t, n, w) 1 Assign(s, t) vf_tam(t, n,pin)

(s, t, n, w) vf_tam(t, n,pin)

(s, t, n, w) (s, t)

,

,

s s t t n n w c

t t n N w c

n N

n

n N

n

n N w c

Assign s t

final

final

final Assig

t T

t

n

T

t t

MILP (Session-based Test Scheduling)

17Apr 9, 2015

vf_tam(t2,n,w)-vf_tam(t1,n,w)+overlap(t1,t2)<=

1

1

* (s, t, n, w)

* (s, t, n, w)

* (s,

(t1) ts(t 2

)

)

t, n, w 0

tnw

tnw

P fi

o

nal Pbound

Wtnw final Wbound

P fin

verla

al Psessions

p ts

MILP (Session-based Test Scheduling)

18Apr 9, 2015

Overlap of tests in session-based algorithm means the start time of

tests is the same

Experiment Setup

20

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21

Results_case1

DVFS_N/DVFS_Y refer to scheduling Without/With DVFS

Same naming scheme applies to TAM_N/TAM_Y Apr 9, 2015

22

Results_case2

Apr 9, 2015

23

Results__case3

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Results__case4

Reference work doesn’t consider hardware compatibility, Voltage

Island and TAM bounds!23Apr 9, 2015

Compatibility file of d6951 1 4 52 2 3 6 93 2 3 6 94 1 4 55 1 5 46 2 3 97 7 88 7 89 2 3 6 9

25

Results__case5

WHY?

Apr 9, 2015

In this work, SoC hierarchy is not considered. In real SoC, TAM

allocation between parent cell and children cell are more difficult.

ITC’02, the most universally adopted SoC so far, is incomplete. For

more accurate test scheduling result, more details are needed.

Some faults are only detectable at certain voltage.

26

Limitation

Apr 9, 2015

Future Work

Some schedules may require individual tests to be executed

at one or more specific voltage/frequency values. The reason

for this is that some faults are voltage/frequency dependent and

can only be detected at such voltage/frequency values. Constraint

below can be forced to solve this problem:

∀pin C Assign∈ (t, n, pin) = 1 for the required t and n.

27Apr 9, 2015

Conclusion

TAM rescheduling could achieve maximally up to 61% reduction in TAT

DVFS and TAM rescheduling combined could result to TAT reduction

range from 50.9% to 69.1%.

Session-based scheduling requires a lot more time to schedule than

session-less scheduling, and we could also end up with the conclusion

that session-less is no worse than session-based in terms of TAT result.

28Apr 9, 2015

References

• [1]S. K. Millican and K. K. Saluja, “Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling,” in 22nd AsianTest Symposium (ATS), pp. 165–170, IEEE, Nov. 2013.

• [2]S. Millican and K. K. Saluja "Optimal Test Scheduling of Stacked Circuits Under Various Hardware and Power Constraints," International Conference on VLSI Design , January 2015.

• [3]V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip,”,2011

• [4]V. Sheshardi, V. D. Agrawal, and P. Agrawal, “Optimal PowerConstrained SoC Test Schedules With Customizable Clock Rates,” in IEEE International SOC Conference (SOCC), (San Jose, CA), pp. 271–276, Oct. 2012.

• [5]S. K. Millican and K. K. Saluja, “Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling,” in 22nd AsianTest Symposium (ATS), pp. 165–170, IEEE, Nov. 2013.

• [6] Sheshardi, V. D. Agrawal, and P. Agrawal, “Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages,” in 26th International Conference on VLSI Design and International Conferenceon Embedded Systems, (Pune, India), pp. 267 – 272, Jan. 2013.

29Apr 9, 2015

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[7] V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip,” IEEE Transactions on Computers, vol. 52, pp. 1619– 1631, Dec. 2003.

[8] Sheshardi, V. D. Agrawal, and P. Agrawal, “power aware SoC test optimization through dynamic voltage and frequency scaling,” in 21st International conference on VLSI-SoC, 102-107, oct, 2013

[9]ITC’02 SoC Testing Benchmark, url:http://itc02socbenchm.pratt.duke.edu/

[10] 3DIC SoC Test Benchmark url:http://3dsocbench.ece.wisc.edu/ (based on ITC’02)

References

Apr 9, 2015

31

Questions?

THANK YOU

Apr 9, 2015