Smart Car Final

8/8/2019 Smart Car Final

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SMART CAR SECURITY SYSTEM 1

CHAPTER 1


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1.1 INTRODUCTION

With the development and applications of many embedded techniques, car security

system design and analysis are constantly improving. Many new techniques, such as biometric recognition

technique, image processing technique, communication technique and so on, have been integrated into a

car security systems. At the same time, the amount of accident of cars still remains high, specially, lost.

So, one practicable car security system should be efficient, robust and reliable.

Traditional car security system rely on many sensors and costs a lot. When one car is

really lost, no more feedback could be valid to help people to find it back.We put forward the face

detection technique to be applied in car security system because this kind of technique is effective and

fast, and one alarm signal could be given to make an alarm or call the police and the host soundlessly with

the help of other modules in the system prototype.

Face detection techniques have been heavily studied in recent years, and it is an

important computer vision problem with application to surveillance, multimedia processing and consumer

products. Many new face detection techniques have been developed to achieve higher detection rate and

faster. One of the techniques used here is Principle Component Analysis (PCA)

In this proposed system

y Preach to the owner if some one tries to stolen

y Automated functions through image processing

y Security maintenance by behavior recognition

y E ffective mobile communication for entire process

y G PS module obtains the precise locality by parsing received G PS signal


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1.2 SOFTWARE AND HARDWARE REQUIREMENTS

a) software requirements:

Software : K E IL ID E , FLASH MA G IC, ORCAD

Operating system : WINDOWS XP

b) Hardware Requirements:

Hardware devices : DS89C430 Micro Controller, MAX232, G SM module, G PS module

Processor : P-4 or higher processor.

Memory : 64KB (minimum)

Ports : 2 Serial Ports.

Others : Integrating Unit, Web Camera


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BLOCK DIAGRAM

Figure 1.1: Block Diagram of Smart Car Security System


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1.3 WORKING

In this paper, we propose a low-cost extendable framework for embedded smart car security

system, which consists of a face detection subsystem, a G PS module, a G SM module and a

control platform. Comparing with traditional car security system, this system does not need any

sensor, and cost much less. Digital camera obtains pictures and then compresses them into jpg

format. The data could be handled by face detection classifiers to find out faces, which are

trained by PCA algorithm. Several methods have been applied to speedup the detection process,

such as the use of E SRAM by distribute the key code into it, and the high hit rate of cache

because the characteristics of image files and the data of cascade detector.

SCHEMATIC DIAGRAM

Fig 1.2 schematic diagram

U1

DS89C450

PSEN29 ALE30

VCC40

GND20

EA31

X119

X218

RST9

P0.0/AD039

P0.1/AD138

P0.2/AD237

P0.3/AD336

P0.4/AD435

P0.5/AD534

P0.6/AD633

P0.7/AD732

P1.01

P1.12

P1.2/RXD13

P1.3/TXD14

P1.45

P1.56

P1.67

P1.78

P2.0/A821

P2.1/A922

P2.2/A1023

P2.3/A1124

P2.4/A1225

P2.5/A1326

P2.6/A1427

P2.7/A1528

P3.0/RXD010

P3.1/TXD011

P3.2/INT012

P3.3/INT113

P3.4/T014

P3.5/T115

P3.6/WR16

P3.7/RD17

Alarm

LS1

1

2Q1

BC547

1

2

3

R1 1K

VCC_BAR

U1

MAX232

R1IN13R2IN8

T1IN11

T2IN10

C+1

C1-3

C2+4

C2-5

V +

2

V-6

R1OUT12

R2OUT9

T1OUT14

T2OUT7

V C C

1 6

G N D

1 5

RXD

TXD

P1

S E R I A L P O R T

594837261

VCC

C3

10uF

C4

10uF

C5

10uF

C110uF

D3

SSF-LXH101

IN 7805

GND

OUT

9VAC

11

22

R3

330EC6

1 0 0 u

F / 1

6 V

C5

470uF/25V

- +

D1

DB106

1

2

3

4

Eye blink sensor

Actuator LS1

1

2Q1

BC547

1

2

3

VCC_BAR

R2

RESISTOR

U1

MAX232

R1IN13R2IN8

T1IN11

T2IN10

C+1

C1-3

C2+4

C2-5

V +

2

V-6

R1OUT12

R2OUT9

T1OUT14

T2OUT7

V C C

1 6

G N D

1 5

TXD

RXD

VCCP1

S E R I A L P O R T

594837261

C3

10uF

C4

10uF

C5

10uF

C110uF


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1.4 POWER SUPPLY

1.4.1 Block Diagram

The ac voltage, typically 220V rms, is connected to a transformer, which steps that ac voltage

down to the level of the desired dc output. A diode rectifier then provides a full-wave rectified

voltage that is initially filtered by a simple capacitor filter to produce a dc voltage. This resulting

dc voltage usually has some ripple or ac voltage variation.

A regulator circuit removes the ripples and also remains the same dc value even if the input dc

voltage varies, or the load connected to the output dc voltage changes. This voltage regulation is

usually obtained using one of the popular voltage regulator IC units.

Fig 1.4.1 Block Diagram of Power supply

1.4.2 Working principle

Transformer

The potential transformer will step down the power supply voltage (0-230V) to (0-6V) level.Then the secondary of the potential transformer will be connected to the precision rectifier,

which is constructed with the help of opamp. The advantages of using precision rectifier are it

will give peak voltage output as DC, rest of the circuits will give only RMS output.

TRANSFORMER RECTIFIER FILTER IC REGULATOR LOAD


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Bridge rectifier

When four diodes are connected as shown in figure, the circuit is called as bridge rectifier. The

input to the circuit is applied to the diagonally opposite corners of the network, and the output is

taken from the remaining two corners.Let us assume that the transformer is working properly and there is a positive potential, at point

A and a negative potential at point B. the positive potential at point A will forward bias D3 and

reverse bias D4.

The negative potential at point B will forward bias D1 and reverse D2. At this time D3 and D1

are forward biased and will allow current flow to pass through them; D4 and D2 are reverse

biased and will block current flow.

The path for current flow is from point B through D1, up through RL, through D3, through the

secondary of the transformer back to point B. this path is indicated by the solid arrows.

Waveforms (1) and (2) can be observed across D1 and D3.

One-half cycle later the polarity across the secondary of the transformer reverse, forward biasing

D2 and D4 and reverse biasing D1 and D3. Current flow will now be from point A through D4,

up through RL, through D2, through the secondary of T1, and back to point A. This path is

indicated by the broken arrows. Waveforms (3) and (4) can be observed across D2 and D4. The

current flow through RL is always in the same direction. In flowing through RL this current

develops a voltage corresponding to that shown waveform (5). Since current flows through the

load (RL) during both half cycles of the applied voltage, this bridge rectifier is a full-wave

rectifier.

One advantage of a bridge rectifier over a conventional full-wave rectifier is that with a given

transformer the bridge rectifier produces a voltage output that is nearly twice that of theconventional full-wave circuit.

This may be shown by assigning values to some of the components shown in views A and B.

assume that the same transformer is used in both circuits. The peak voltage developed between


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points X and y is 1000 volts in both circuits. In the conventional full-wave circuit shownin

view A, the peak voltage from the center tap to either X or Y is 500 volts. Since only one diode

can conduct at any instant, the maximum voltage that can be rectified at any instant is 500 volts.

The maximum voltage that appears across the load resistor is nearly-but never exceeds-500 v0lts,

as result of the small voltage drop across the diode. In the bridge rectifier shown in view B, the

maximum voltage that can be rectified is the full secondary voltage, which is 1000 volts.

Therefore, the peak output voltage across the load resistor is nearly 1000 volts. With both

circuits using the same transformer, the bridge rectifier circuit produces a higher output voltage

than the conventional full-wave rectifier circuit.

IC voltage regulators

Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the circuitry

for reference source, comparator amplifier, control device, and overload protection all in a single

IC. IC units provide regulation of either a fixed positive voltage, a fixed negative voltage, or an

adjustably set voltage. The regulators can be selected for operation with load currents from

hundreds of milli amperes to tens of amperes, corresponding to power ratings from milli watts to

tens of watts.


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Fig 1.4.2 Circuit Diagram Of Power Supply

A fixed three-terminal voltage regulator has an unregulated dc input voltage, Vi, applied to one

input terminal, a regulated dc output voltage, Vo, from a second terminal, with the third terminal

connected to ground.

The series 78 regulators provide fixed positive regulated voltages from 5 to 24 volts. Similarly,

the series 79 regulators provide fixed negative regulated voltages from 5 to 24 volts.

y For ICs, microcontroller, LCD --------- 5 volts

y For alarm circuit, op-amp, relay circuits ---------- 12 volts


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CHAPTER 2

DS89C430 MICROCONTROLLER


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2.1 About Micro Controller

The DS89C430 and DS89C450 offer the highest performance available in 8051-compatible

microcontrollers. They feature newly designed processor cores that execute instructions up to 12 times

faster than the original 8051 at the same crystal speed. Typical applications will experience a speed

improvement up to 10x. At 1 million instructions per second (MIPS) per megahertz, the microcontrollers

achieve 33 MIPS performance from a maximum 33MHz clock rate.

2.1.1 Features

y High-Speed 8051 Architecture

o One Clock-Per-Machine Cycle

o DC to 33MHz Operation

o Single Cycle Instruction in 30ns

o Optional Variable Length MOVX to Access Fast/Slow Peripherals

o Dual Data Pointers with Automatic Increment/Decrement and Toggle Select

o Supports Four Paged Memory-Access Modes

y On-Chip Memory

o 16kB/64kB Flash Memory

o In-Application Programmableo In-System Programmable Through Serial Port

o 1kB SRAM for MOVX

y 80C52 Compatible

o 8051 Pin and Instruction Set Compatible

o Four Bidirectional, 8-Bit I/O Ports

o Three 16-Bit Timer Counters

o 256 Bytes Scratchpad RAM

y Power-Management Mode

o Programmable Clock Divider

o Automatic Hardware and Software E xit

y ROMSIZ E Feature


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o Selects Internal Program Memory Size from 0 to 64kB

o Allows Access to E ntire E xternal Memory Map

o Dynamically Adjustable by Software

y Peripheral Features

o Two Full-Duplex Serial Ports

o Programmable Watchdog Timer

o 13 Interrupt Sources (Six E xternal)

o Five Levels of Interrupt Priority

o Power-Fail Reset

o E arly Warning Power-Fail Interrupt

o E lectromagnetic Interference ( E MI) Reduction

2.1.2 PIN DESCRIPTION


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TABL E 2.1 MICROCONTROLL E R PIN D E SCRIPTION


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2.2 DETAILED DESCRIPTION

The DS89C430 and DS89C450 are pin compatible with all three packages of the

standard 8051 and include standard resources such as three timer/counters, serial port, and four 8- bit I/O ports. The three part numbers vary only by the amount of internal flash memory

(DS89C430 = 16kB, DS89C450 = 64kB), which can be in-system/in application programmed

from a serial port using ROM-resident or user-defined loader software. For volume deployments,

the flash can also be loaded externally using standard commercially available parallel

programmers.

Besides greater speed, the DS89C430/DS89C450 include 1kB of data

RAM, a second full hardware serial port, seven additional interrupts, two extra levels of interrupt

priority, programmable watchdog timer, brownout monitor and power-fail reset. Dual data

pointers (DPTRs) are included to speed up block data-memory moves with further enhancements

coming from selectable automatic increment/decrement and toggle select operation. The speed of

MOVX data memory access can be adjusted by adding stretch values up to 10 machine cycles for

flexibility in selecting external memory and peripherals.

A power management mode consumes significantly lower power by slowing the CPU execution

rate from one clock period per cycle to 1024 clock periods per cycle. A selectable switchback

feature can automatically cancel this mode to enable normal speed responses to interrupts.

For E MI-sensitive applications, the microcontroller can disable the

ALE signal when the processor is not accessing external memory.

Terminology

The term DS89C430 is used in the remainder of the document to refer to the

DS89C430 and DS89C450, unless otherwise specified.

Compatibility

The DS89C430 is a fully static CMOS 8051-compatible microcontroller

similar in functional features to the DS87C520, but it offers much higher performance. In most

cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately


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improving the operation. While remaining familiar to 8051 family users, the DS89C430 has

many new features. In general, software written for existing 8051-based systems works without

modification on the DS89C430, with the exception of critical timing routines, as the DS89C430

performs its instructions much faster for any given crystal selection.

The DS89C430 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes

of direct RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 8051

products. Timers default to 12 clocks-per-cycle operation to keep their timing compatible with a

legacy 8051 family systems. However, timers are individually programmable to run at the new

one clock per cycle if desired. The DS89C430 provides several new hardware features, described

in subsequent sections, implemented by new special-function registers (SFRs).

Performance OverviewFeaturing a completely redesigned high-speed 8051-compatible core, the

DS89C430 allows operation at a higher clock frequency. This updated core does not have the

wasted memory cycles that are present in a standard 8051. A conventional 8051 generates

machine cycles using the clock frequency divided by 12. The same machine cycle takes one

clock in the DS89C430. Thus, the fastest instructions execute 12 times faster for the same crystal

frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted

that this speed improvement is reduced when using external memory access modes that require

more than one clock per cycle.

Individual program improvement depends on the instructions used. Speed-

sensitive applications would make the most use of instructions that are 12 times faster. However,

the sheer number of 12-to-1 improved op codes makes dramatic speed improvements likely for

any code. These architectural improvements produce instruction cycle times as low as 30ns. The

dual data pointer feature also allows the user to eliminate wasted instructions when moving

blocks of memory. The new page modes allow for increased efficiency in external memory

accesses.

Instruction Set Summary


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All instructions have the same functionality as their 8051 counterparts,

including their affect on bits, flags, and other status functions. However, the timing of each

instruction is different, in both absolute and relative number of clocks.

For absolute timing of real-time events, the duration of software loops can

be calculated using information given in the Instruction Set table in the Ul tra-High- Speed Fl ash

M icrocontro ller U sers Guide. However, counter/timers default to run at the older 12 clocks per

increment. In this way, timer-based events occur at the standard intervals with software

executing at higher speed. Timers optionally can run at a reduced number of clocks per

increment to take advantage of faster processor operation.

The relative time of some instructions may be different in the new architecture.

For example, in the original architecture, the MOVX A, @DPTR instruction and the MOV

direct, direct instruction used two machine cycles or 24 oscillator cycles. Therefore, theyrequired the same amount of time. In the DS89C430, the MOVX instruction takes as little as two

machine cycles or two oscillator cycles, but the MOV direct, direct uses three machine cycles

or three oscillator cycles. While both are faster than their original counterparts, they now have

different execution times. This is because the DS89C430 usually uses one machine cycle for

each instruction byte and requires one cycle for execution.

Special-Function Registers (SFRs)

All peripherals and operations that are not explicit instructions in the

DS89C430 are controlled through SFRs. The most common features basic to the architecture are

mapped to the SFRs. These include the CPU registers (ACC, B, and PSW), data pointers, stack

pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR controls an individual

function or reports the functions status. The SFRs reside in register locations 80hFFh and are

only accessible by direct addressing. SFRs with addresses ending in 0h or 8h are bit addressable.

All standard SFR locations from the 8051 are duplicated in the DS89C430, and several SFRs

have been added for the unique features of the DS89C430. Most of these features are controlled

by bits in SFRs located in unused locations in the 8051 SFR map, allowing for increased

functionality while maintaining complete instruction set compatibility.

Data Pointers


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The data pointers (DPTR and DPTR1) are used to assign a memory address for the

MOVX instructions. This address can point to a MOVX RAM location (on-chip or off-chip) or a

memory-mapped peripheral. Two pointers are useful when moving data from one memory area

to another, or when using a memory-mapped peripheral for both source and destination

addresses. The user can select the active pointer through a dedicated SFR bit (S E L = DPS.0), or

can activate an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An

additional feature, if selected, provides automatic incrementing or decrementing of the current

DPTR.

Stack Pointer

The stack pointer denotes the register location at the top of the stack, which is the

last used value. The user can place the stack anywhere in the scratchpad RAM by setting the

stack pointer to the desired location, although the lower bytes are normally used for workingregisters.

I/O Ports

The DS89C430 offers four 8-bit I/O ports. E ach I/O port is represented by an SFR

location and can be written or read. The I/O port has a latch that contains the value written by

software.

Counter/Timers

Three 16-bit timer/counters are available in the DS89C430. E ach timer is

contained in two SFR locations that can be read or written by software. The timers are controlled

by other SFRs, described in the SFR B it De scri ption section of the Ul tra-High- Speed Fl ash

M icrocontro ller U sers Guide.

Serial Ports

The DS89C430 provides two UARTs that are controlled and accessed by SFRs.

E ach UART has an address that is used to read and write the value contained in the UART. The

same address is used for both read and write operations, and the read and write operations are

distinguished by the instruction. Its own SFR control register controls each UART.


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CHAPTER 3

GLOBAL SYSTEM FOR MOBILE COMMUNICATION


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3.1 MODEM

A G SM modem is a wireless modem that works with a G SM wireless

network. A wireless modem behaves like a dial-up modem. The main difference between them is

that a dial-up modem sends and receives data through a fixed telephone line while a wireless

modem sends and receives data through radio waves.

A G SM modem can be an external device or a PC Card / PCMCIA Card. Typically, an external

G SM modem is connected to a computer through a serial cable or a USB cable. A G SM modem

in the form of a PC Card / PCMCIA Card is designed for use with a laptop computer. It should

be inserted into one of the PC Card / PCMCIA Card slots of a laptop computer. Like a G SM

mobile phone, aG

SM modem requires a SIM card from a wireless carrier in order to operate.

As mentioned in earlier sections of this SMS tutorial, computers use AT commands to control

modems. Both G SM modems and dial-up modems support a common set of standard AT

commands. You can use a G SM modem just like a dial-up modem.

In addition to the standard AT commands, G SM modems support an extended set of AT

commands. These extended AT commands are defined in the G SM standards. With the extended

AT commands, you can do things like:

y Reading, writing and deleting SMS messages.

y Sending SMS messages.

y Monitoring the signal strength.

y Monitoring the charging status and charge level of the battery.

y Reading, writing and searching phone book entries.

The number of SMS messages that can be processed by a G SM modem per minute is very low --

only about six to ten SMS messages per minute.


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GSM MODEM APPLICATION

Fig 3.1 GSM MODEM APPLICATIONS


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3.2 TECHNICAL INTRODUCTION TO GSM MODEM TECHNOLOGY

3.2.1 FACTS AND APPLICATIONS OF GSM/GPRS MODEM

The G SM/ G PRS Modem comes with a serial interface through which the modem can be controlled usingAT command interface. An antenna and a power adapter are provided.

The basic segregation of working of the modem is as under

Voice calls

SMS

G SM Data calls

G PRS

Voice calls: Voice calls are not an application area to be targeted. In future if interfaces like a microphone

and speaker are provided for some applications then this can be considered.

SMS: SMS is an area where the modem can be used to provide features like:

Pre-stored SMS transmission

These SMS can be transmitted on certain trigger events in an automation system

SMS can also be used in areas where small text information has to be sent. The transmitter can be an

automation system or machines like vending machines, collection machines or applications like

positioning systems where the navigator keeps on sending SMS at particular time intervals

SMS can be a solution where G SM data call or G PRS services are not available

GSM Data Calls: Data calls can be made using this modem. Data calls can be made to a normal PSTN

modem/phone line also (even received). Data calls are basically made to send/receive data streams

between two units either PCs or embedded devices. The advantage of Data calls over SMS is that both

parties are capable of sending/receiving data through their terminals.

Some points to be remembered in case of data calls:

The data call service doesnt come with a normal SIM which is purchased but has to be requested with

the service provider (say Airtel).

Upon activation of data/fax service you are provided with two separate numbers i.e. the Data call

number and the Fax service number.


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Data calls are established using Circuit Switched data connections.

Right now the speed at which data can be transmitted is 9.6 kbps.

The modem supports speeds up to 14.4 kbps but the provider give a maximum data rate of 9.6 kbps

during G SM data call.

Technologies like HSCSD (high Speed Circuit Switched Data) will improve drastically the data rates, but still in pipeline.

Applications And Facts About GSM Data Calls:

Devices that have communication on serial port either on PC or in the embedded environment

Devices that want to communicate with a remote server for data transfer

This capability of data transfer can help in reducing processing requirements of the device

The basic aim is to provide a wireless solution keeping the existing firmware intact The clients firmware continues to work without any modifications (no changes in the existing software

required)

G SM data calls can be a good solution where data has to be transmitted from a hand-held device to a

central server

The interface on two sides can be between PCs as well as embedded devices

Fig 3.2 INTERFACING FIGURE

Calls can be established by the terminals at either side to start data calls

The Modem remains transparent during data transfer after the call is established.

Call establishment utility to be provided in case PC terminals

Call establishment to be automated in case of embedded terminals. G SM converter can be an option


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where intelligence of establishing calls has to be put in case of embedded devices. Concept of G SM

converter is discussed later in this document

3.3 GSM SECURITY

G SM was designed with a moderate level of security. The system was designed to authenticate the

subscriber using shared-secret cryptography. Communications between the subscriber and the base station

can be encrypted. The development of UMTS (UNIV E RSAL MOBIL E COMMUNICATIN G SYST E M

introduces an optional, that uses a longer authentication key to give greater security, as well as mutually

authenticating the network and the user - whereas G SM only authenticated the user to the network (and

not vice versa).

G SM uses several cryptographic algorithms for security. A large security advantage of G SM isthat the key, the crypto variable stored on the SIM card that is the key to any G SM ciphering

algorithm, is never sent over the air interface. Serious weaknesses have been found in both

algorithms, and it is possible to break A5/2 in real-time in a ciphertext-only attack. The system

supports multiple algorithms so of G SM converter is discussed later in this document operators

may replace that cipher with a stronger one.

A G SM modem is a wireless modem that works with a G SM wireless network. A wireless modem

behaves like a dial-up modem. The main difference between them is that a dial-up modem sends and

receives data through a fixed telephone line while a wireless modem sends and receives data through radio

waves. A G SM modem can be an external device or a PC Card / PCMCIA Card. Typically, an external

G SM modem is connected to a computer through a serial cable or a USB cable. A G SM modem in th

form of a PC Card / PCMCIA Card is designed for use with a laptop computer. It should be inserted into

one of the PC Card / PCMCIA Card slots of a laptop computer. Like a G SM mobile phone, a G S

modem requires a SIM card from a wireless carrier in order to operate.

Computers use AT commands to control modems. Both G SM modems and dial-up modems

support a common set of standard AT commands.


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In addition to the standard AT commands, G SM modems support an extended set of AT

commands .These extended AT commands are defined in the G SM standards.

With the extended AT commands, we can do things like:

y Reading, writing and deleting SMS messages.

y Sending SMS messages.

y Monitoring the signal strength.

y Monitoring the charging status and charge level of the battery.

y Reading, writing and searching phonebook entries.

The number of SMS messages that can be processed by a G SM modem per minute is very low --

only about six to ten SMS messages per minute.

3.4 ADVANTAGES OF GSM MODULE

y Small, lightweight and easy to integrate

y Low power consumption

y Full E TSI / R&TT E type approval

y Internal SIM card reader and option for external SIM card reader

y Full RS232 on CMOS level with flow control (RX, TX, CTS, RTS, CTS, DTR,

DSR,DCD, RI)

3.5 PRODUCT DESCRIPTION

The G SM Commercial Modem is an approved modem for embedded applications. It provides a 5V TTL

compatible serial interface to host Data terminal equipment.


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Accessories:

1.PowerAdapter

2. Standard rubber antenna , regular G SM Coverage Areas.

3.6 APPLICATIONS

Access control devices: Now access control devices can communicate with servers and security staff

through SMS messaging. Complete log of transaction is available at the head-office Server instantly

without any wiring involved and device can instantly alert security personnel on their mobile phone in

case of any problem. RaviRaj Technologies is introducing this technology in all Fingerprint Access

control and time attendance products. You can achieve high security any reliability.

Transaction terminals: E DC machines, POS terminals can use SMS messaging to confirm transactionsfrom central servers. The main benefit is that central server can be anywhere in the world. Today you

need local servers in every city with multiple telephone lines. You save huge infrastructure costs as well

as per transaction cost.

Supply Chain Management: Today SCM require huge IT infrastructure with leased lines, networking

devices, data centre, workstations and still you have large downtimes and high costs. You can do all this

at a fraction of the cost with G SM M2M technology.

What applications is suitable for GSM communication?

If your application needs one or more of the following features, G SM will be more cost-effective then

other communication systems.

Short Data Size: You data size per transaction should be small like 1-3 lines. e.g. banking transaction

data, sales/purchase data, consignment tracking data, updates. These small but important transaction data

can be sent through SMS messaging which cost even less then a local telephone call or sometimes free of cost worldwide. Hence with negligible cost you are able to send critical information to your head office

located anywhere in the world from multiple points. You can also transfer faxes, large data through G SM

but this will be as or more costly compared to landline networks.


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Multiple remote data collection points: If you have multiple data collections points situated all over

your city, state, country or worldwide you will benefit the most. The data can be sent from multiple points

like your branch offices, business associates, warehouses, agents with devices like G SM modemsconnected to PCs, G SM electronic terminals and Mobile phones. Many a times some places like

warehouses may be situated at remote location may not have landline or internet but you will have G SM

network still available easily.

High uptime: If your business require high uptime and availability G SM is best suitable for you as G SM

mobile networks have high uptime compared to landline, internet and other communication mediums.

Also in situations where you expect that someone may sabotage your communication systems by cutting

wires or taping landlines, you can depend on G SM wireless communication.

Mobility, Quick installation: G SM technology allow mobility, G SM terminals, modems can be just

picked and installed at other location unlike telephone lines. Also you can be mobile with G SM terminals

and can also communicate with server using your mobile phone. You can just purchase the G SM

hardware like modems, terminals and mobile handsets, insert SIM cards, configure software and your are

ready for G SM communication. G SM solutions can be implemented within few weeks whereas it may

take many months to implement the infrastructure for other technologies.

3.7 AT COMMANDS

3.7.1 Terms and Abbreviations:

a. Asynchronous: A serial data transmission method that uses Start and Stop bits to synchronize reception.

b. AT Commands: A group of commands that can be sent by a terminal or host computer to control the

ISU in Command mode.

c. Command E ntry: An AT command is a string of characters sent by the DT E to the ISU while the ISU is

in command mode. A command string has a prefix, a body, and a terminator. The prefix consists of the

ASCII characters AT or at. The body is a string of commands restricted to printable ASCII characters.


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The default terminator is the character.There are two format types for AT commands: basic and

extended. The basic commands consist of single ASCII characters, or single characters preceded by a

prefix character, followed by a decimal parameter.

There are a few rules about the entry of commands:

a. All commands (apart from A/ and +++) start with AT or at. The commands in a command string

(apart from A/ and +++) are executed only after the return or enter key is pressed.

b. Use all upper or lower case letters, not a combination.

c. The maximum number of characters in a command string is 128. Multiple commands can be

concatenated onto a single command line or by a semicolon.

d. Command editing can usually be performed by the backspace or delete keys.

e. If a parameter is missed from a basic command, a zero is implied (e.g. ATH implies ATH0). If an

optional parameter is skipped from an extended command, the current value is implied. Optional

parameters are enclosed by square brackets ([...]) in this document.

f. Spaces can be entered into a command string to increase clarity. These are ignored.

g. Characters that precede the AT prefix are ignored.

3.7 .2 BASIC AT COMMANDS

Commands:

+CNMI - New SMS Message Indications to DT E

Set Command : +CNMI=[[,[,[,[, ]]]]]

+CMTI: ,

SMS-D E LIV E Rs (except class 2 messages and messages in the message waiting indication group (store

message)) are routed directly to the T E using unsolicited result code:

+CMT: [], (PDU mode)

defined in =2. Messages of other data coding schemes result in indication as


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defined in =1.

Read Command: +CNMI

Read command returns the current settings for the SMS message indication. Response is in the

form:

+CNMI: ,,,,

Test Command: +CNMI

Test command returns the supported settings of the phone. Response is in the form:

+CNMI: (list of supported s),(list of supported s),(list of supported s),(list of supported

s),(list of supported s)

+CMGD - Delete SMS Message

E xec Command: +CM G D=

E xecution command deletes message from preferred message storage ( is the

selected message storage from the +CPMS command) location . If deleting fails, final result code

+CMS

+CMGR - Read SMS Message

E xec Command: +CM G R=

E xecution command returns the SMS message with location value from message storage

( is the selected message storage from the +CPMS command).

If status of the message is received unread, status in the storage changes to received read. If

reading fails, final result code +CMS E RROR: is returned.


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+CMGS - Send SMS Message

Sending the message

To send the sms message ,type the following command:

AT+CMGS="+31638740161"

Replace the above phone number with your own cell phone number. The modem will respond with:

>

we can now type the message text and send the message using the - key combination

HelloWorld!


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CHAPTER 4

SERIAL COMMUNICATION


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4.1 MAX 232

The MAX232 device is a dual driver/receiver that includes a capacitive voltage generator to supply E IA

232 voltage levels from a single 5-V supply. E ach receiver converts E IA-232 inputs to 5-V TTL/CMOS

levels. These receivers have a typical threshold of 1.3 V and a typical hysteresis of 0.5 V, and can accept

30-V inputs. E ach driver converts TTL/CMOS input levels into E IA-232 levels.

4.1.1 Logic Signal Voltage

Serial RS-232 (v.24) communication works with voltages (between -15v -3v are used to transmit a

binary 1 and =3V ...-15v to transmit a binary 0) which are not compatible with todays computer logic

voltages. On the other hand , classic TTL computer logic operates between 0V+5V (roughly 0V

+0.8V referred to as low for Binary 0,_2V .+5V for high Binary 1).Modern low-power logic

operates in the range of 0V ... +3.3V or even lower. So, the maximum RS-232 signal levels are far too

high for today's computer logic electronics, and the negative RS-232 voltage can't be grokked at all by the

computer logic. Therefore, to receive serial data from an RS-232 interface the voltage has to be reduced,

and the 0 and 1 voltage levels inverted. In the other direction (sending data from some logic over RS-232)

the low logic voltage has to be "bumped up", and a negative voltage has to be generated, too.

All this can be done with conventional analog electronics, e.g. a particular power supply and a couple of

transistors or the once popular 1488 (transmitter) and 1489 (receiver) IC s. However, since more than a

decade it has become standard in amateur electronics to do the necessary signal level conversion with an

IC from the MAX232 family (typically a MAX232 or some clone). IN fact , it is hard to find some RS-

232 circuitry in amateur electronics without a MAX232 or some clone.


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Voltage levels

RS-232 TTL Logic

-----------------------------------------------

-15V ... -3V +2V ... +5V 1+3V ... +15V 0V ... +0.8V 0

Fig: 4.1 MAX 232 DIP PACKAGE

The MAX232 from Maxim was the first IC which in one package contains the necessary drivers

(two) and receivers (also two), to adapt the RS-232 signal voltage levels to TTL logic. It became

popular, because it just needs one voltage (+5V) and generates the necessary RS-232 voltage

levels (approx. -10V and +10V) internally. This greatly simplified the design of circuitry.

Circuitry designers no longer need to design and build a power supply with three voltages (e.g. -

12V, +5V, and +12V), but could just provide one +5V power supply, e.g. with the help of a

simple 78x05 voltage converter.

The MAX232 (A) has two receivers (converts from RS-232 to TTL voltage levels) and two

drivers (converts from TTL logic to RS-232 voltage levels). This means only two of the RS-232

signals can be converted in each direction. The old MC1488/1498 combo provided four drivers

and receivers.


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Typically a pair of a driver/receiver of the MAX232 is used for

y TX and RX and the second one for

y

CTS and RTS.

4.2 RS232

When we look at the connector pinout of the RS232 port, we see two pins which are certainly used for

flow control. These two pins are RTS , request to send and CTS , clear to send. With DTE /DCE

communication (i.e. a computer communicating with a modem device) RTS is an output on the DTE and

input on the DCE . CTS is the answering signal comming from the DCE .

Before sending a character, the DTE asks permission by setting its RTS output. No information will be

sent until the DCE grants permission by using the CTS line. If the DCE cannot handle new requests, the

CTS signal will go low. A simple but useful mechanism allowing flow control in one direction. The

assumption is, that the DTE can always handle incomming information faster than the DCE can send it.

In the past, this was true. Modem speeds of 300 baud were common and 1200 baud was seen as a high

speed connection.

For further control of the information flow, both devices have the ability to signal their status to the other

side. For this purpose, the DTR data terminal ready and DSR data set ready signals are present. The DTE

uses the DTR signal to signal that it is ready to accept information, whereas the DCE uses the DSR

signal for the same purpose. Using these signals involves not a small protocol of requesting and

answering as with the RTS /CTS handshaking. These signals are in one direction only.

The last flow control signal present in DTE /DCE communication is the CD carrier detect. It is not used

directly for flow control, but mainly an indication of the ability of the modem device to communicate

with its counter part. This signal indicates the existence of a communication link between two modem

devices.


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Null modem without handshaking

How to use the handshaking lines in a null modem configuration? The simplest way is to don't use them

at all. In that situation, only the data lines and signal ground are cross connected in the null modem

communication cable. All other pins have no connection. An example of such a null modem cable without

handshaking can be seen in the figure below.

Simple null modem without handshaking

Connector 1 Connector 2 Function

2 3 Rx Tx

3 2 Tx Rx

5 5 Signal ground

FIG 4.2 DB9 CONNECTOR


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4.4.1 RS232 COMMUNICATION

Fig 4.3 Circuit Diagram Of Serial Communication

4.2.2 INTRODUCTION

In telecommunications, RS-232 is a standard for serial binary data interconnection between a DT E (Data

terminal equipment) and a DC E (Data Circuit-terminating E quipment). It is commonly used in computer

serial ports.

Scope of the Standard:

The E lectronic Industries Alliance ( E IA) standard RS-232-C [3] as of 1969 defines:

E lectrical signal characteristics such as voltage levels, signaling rate, timing and slew-rate of signals,

voltage withstand level, short-circuit behavior, maximum stray capacitance and cable length

Interface mechanical characteristics, pluggable connectors and pin identification Functions of each circuit in the interface connector

Standard subsets of interface circuits for selected telecom applications


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The standard does not define such elements as character encoding (for example, ASCII, Baudot or

E BCDIC), or the framing of characters in the data stream (bits per character, start/stop bits, parity). The

standard does not define protocols for error detection or algorithms for data compression.

The standard does not define bit rates for transmission, although the standard says it is intended for bit

rates lower than 20,000 bits per second. Many modern devices can exceed this speed (38,400 and 57,600

bit/s being common, and 115,200 and 230,400 bit/s making occasional appearances) while still using RS-

232 compatible signal levels.

Details of character format and transmission bit rate are controlled by the serial port hardware, often a

single integrated circuit called a UART that converts data from parallel to serial form. A typical serial

port includes specialized driver and receiver integrated circuits to convert between internal logic levels

and RS-232 compatible signal levels.

Circuit Working Description

In this circuit the MAX 232 IC used as level logic converter. The MAX232 is a dual driver/receiver that

includes a capacive voltage generator to supply E IA 232 voltage levels from a single 5v supply. E ach

receiver converts E IA-232 to 5v TTL/CMOS levels. E ach driver converts TLL/CMOS input levels into

E IA-232 levels.


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In this circuit the microcontroller transmitter pin is connected in the MAX232 T2IN pin which converts

input 5v TTL/CMOS level to RS232 level. Then T2OUT pin is connected to reviver pin of 9 pin D type

serial connector which is directly connected to PC.

In PC the transmitting data is given to R2IN of MAX232 through transmitting pin of 9 pin D type

connector which converts the RS232 level to 5v TTL/CMOS level. The R2OUT pin is connected to

receiver pin of the microcontroller. Likewise the data is transmitted and received between the

microcontroller and PC or other device vice versa.


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CHAPTER 5

GLOBAL POSITIONING SATELLITE


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5.1 INTRODUCTION

G PS stands for G lobal Positioning System, which is a nifty satellite that tells

you your location anywhere on planet earth. This part is all about G PS. A special radio receiver

measures the distance from your location to satellites that orbit the earth broadcasting radio

signals. G PS can pinpoint your position anywhere in the world.

You can purchase an inexpensive G PS receiver, pop some batteries in it,

and turn it on. Your location appears on the screen .No map, compass, sextant, nor is sundial

required .Just like the magic. Its not really magic, though, but has evolved from some great

practical applications of science that have come together over the last 50 years.

5.2 HISTORY OF GPS:

Military, government and civilian users all over the world rely on G PS for

navigation and location positioning, but radio signals have been used for navigation purposes

since the 1920s. LORAN (Long Range Aid to Navigation), a position- finding system that

measured the time difference of arriving radio signals , was developed during World War- 2.

The first step to G PS came way back in 1957 when the Russians launched

SPUTNIK, the first satellite to orbit the E arth. Sputnik used a radio transmitter to broadcast

telemetry information. Scientists at that Johns Hopkins applied physics Lab discovered that the

Doppler shift phenomenon applied to the spacecraft and almost unwittingly sruct gold.

A down to earth, painless example of the Doppler shift principle is when you stand

on a sidewalk and a police car speeds by in hot pursuit of a stolen motorcycle. The pitch of the

police siren increases as the car approaches you and then drops sharply as it moves away.

American scientists figured out that they knew the satellites precise orbital position,

they could accurately locate their exact position on earth by listening to the pinging sounds and

measuring the satellites radio signal Doppler shift. Satellite offered some possibilities for

navigation and positioning system .and the U.S.Deparment of Defense (DOD) explored the

concept.


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In 1973, the Air-Force was selected as the lead organization to consolidate all the

military satellite navigation efforts into a single program. This evolved into the NAVSTAR

(Navigation Satellite Timing and Ranging) G lobal positioning system, which is the official name

for the United States G PS program.

5.3 HOW GPS WORKS:

The intricacies of G PS are steeped in mathematics, physics, and

engineering, but you dont need to be a rocket scientist to understand how G PS works.

G PS is composed of three parts as shown in the below figure:

Satellites

G round stations

Receivers

FIG 5.1 BLOCK DIAGRAM OF GPS


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5.3.1 EYEING SATELLITES:

In G PS jargon, a satellite is the space segment. A constellation of 24 G PS

satellites (21 operational and 3 spares) orbits about 12,000 miles above the E arth (as shown in

figure 3-2). The satellites zoom through the heavens at around 7,000miles per hour .It takes

about 12 hours for a satellite to completely orbit the E arth, passing over the exact same spot

approximately every 24 hours. The satellites are positioned where a G PS receiver can receive

signals from at least six of the satellites at any time, at any location on the E arth ( if nothing

obstructs the signals).

FIG 5.2 WORKING OF SATELLITES


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A satellite has three key pieces of hardware:

COMPUTER: This onboard computer controls its flight and other functions.

ATOMIC CLOCK: This keeps accurate time within three nanoseconds (around three-

billionths of a second).

RADIO TRANSMITTER: This sends signals to E arth.

G PS satellites dont just help you stay found. All G PS satellites since 1980 carry NUD E T

sensors .No, this isnt some high-tech pornography-detection system.NUD E T is an acronym for

Nuclear Detonation; G PS satellites have sensors to detect nuclear attack, and help evaluate strike

damage.

The solar-powered G PS satellites have a limited life span (around 10 years).

When they start to fail, spares are activated or new satellites are sent into orbit to replace the old

ones.

GPS RADIO SIGNALS:

G PS satellites transmit two types of radio signals: C/A-code and P-code. Briefly, here are the

uses and differences of these two types of signals.

COARSE ACQUISITION (C/A CODE)

Coarse Acquisition(C/A-code) is the type of signal that consumer G PS units receive .C/A- code

is sent on the L1 band at a frequency of 1575.42 MHz


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C/A broadcasts are known as the Standard positioning Service (SPS).

C/A code is less accurate than p-code (see the following section) and is easier for U.S. military

forces to jam and spoof (broadcast false signals to make a receiver think its somewhere else

when its really not).

The advantage of C/A-code is that its quicker to use for acquiring satellites and getting an initial

position fix. Some military P-code receivers first track on the C/a-code and then switch over to

P-code.

PRECISION (P-CODE)

P-code provides highly precise location information. P-code is difficult to jam and spoof .the P-

code signal is broadcast on the L2 band at 1227.6 MHz

P-code broadcasts are known as the Precise positioning Services (PPS).

5.3.2 COVERING GROUND STATIONS

G round stations are the control segments of G PS. Five unmanned ground stations

around the E arth monitor the satellites .information from the stations is sent to a master control

station the Consolidated Space Operations Centre ( CSOC) at Schriever Air Force Base in

Colorado where the data is processed to determine each satellites ephemeris and timing errors.

An ephemeris is a list of the predicted positions of astronomical bodies such as the

planets or the Moon. E phemerides (the plural of ephemeris) have been around for thousands of

years because of their importance in celestial navigation . E phemerides are compiled to track the

positions of the numerous satellites orbiting the earth.


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The processed data is sent to the satellites once daily with ground antenna located

around the world. This is kind of like syncing a personal digital assistant (PDA) with your

personal computer to ensure that all the data is in sync between the two devices. Because the

satellites have small built-in rockets, the CSOC can control them to ensure that they stay in a

correct orbit.

5.3.3 GPS RECEIVERS

Anyone who has a G PS receiver the satellite signals to determine where he or she is located.

SAT E LLIT E DATA:

G PS units receive two types of data from the NAVSATR satellites.

Almanac:

Almanac data contains the approximate positions of the satellites. The data is constantly being

transmitted and is stored in the G PS receivers memory.

E phemeris:

E phemeris data has the precise positions of the satellites. To get an accurate location fix, the

receiver has to know how far away a satellite is. The G PS receiver calculates the distance to the

satellite by using signals from the satellite.

Using the formula Distance=Velocity x Time, a G PS receiver calculates the satellites distance.

A radio signal travels at the speed of light (186,000 miles per second). The G PS receiver needs

to know how long the radio signal takes to travel from the satellite to the receiver in order to

figure the distance. Both the satellite and the G PS receiver generate an identical pseudo-random

code sequence. When the G PS receiver receives this transmitted code, it determines how much

the code needs to be shifted (using the Doppler-shift principle) for the two code sequences to


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match .The shift is multiplied by the speed of light to determine the distance from the satellite to

the receiver.

Multiple Satellites:

A G PS receiver needs several pieces to produce position information:

Location: A minimum of three satellite signals is required to find your location.

Position: Four satellite signals are required to determine your position in three

dimensions : Latitude, Longitude, and elevation .

5.4 HOW ACCURATE IS A GPS RECEIVER?

According to the government and G PS receiver manufactures, expect your

G PS unit to be accurate within 49 feet (thats 15 meters for metric-savvy folks). If your G PS

reports that youre at a certain location, you can be reasonably sure that youre within 40 feetof that exact set of coordinates.

G PS receivers tell you how accurate your position is. Based on the quality of

the satellite signals that the unit receives, the screen displays the estimated accuracy in feet or

meters. Accuracy depends on

Receiver location

Obstructions that block satellite signals

E ven youre not a military G PS user, you can get more accuracy by using a G PS receiver that

supports corrected location data. Corrected information is broadcast over radio signals that come

from either


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Non- G PS satellites

G round based beacons

Two common sources of more accurate location data are

Differential G PS ( D G PS) Wide Area Augmentation System( WAAS)

FIG 5.3 shows the accuracy you can expect from a G PS receiver. These numbers are guidelines;

at times, you may get slightly more or less accuracy.

TABLE 5.1 GPS ACCURACY


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Clouds, rain, snow, and weather dont reduce the strength of G

PS signals enoughto reduce accuracy. The only way that weather can weaken signals is when a

significant amount of rain or snow accumulates on the G PS receiver antenna or an

overhead tree canopy.


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5.4.1 INFORMATION FROM GPS RECEIVERS:

G PS receivers provide your location and other useful information:

TIM E : A G PS receiver receives time information from atomic clocks, so its much more

accurate than your wristwatch.

LOCATION: G PS provides your location in three dimensions:

Latitude(x coordinate)

Longitude (y coordinate)

E levation

SPEE D: When you are moving, a G PS receiver displays your speed.

DIR E CTION OF TRAV E L: A G PS receiver can display your direction of t ravel if youre

moving.

If youre stationary, the unit cant use satellite signals to determine which direction youre

facing. Some G PS units have compasses that show the direction the receiver is pointed whether

youre moving or standing still.

STOR E D LOCATIONS: You can locations where youve been or want to go with a G PS

receiver. These location positions are waypoints are important because a G PS unit can supply

you with directions and information on how to get to a waypoint. A collection of waypoints that

plots a course of travel is a route, which can also be stored . G PS receivers also store tracks

(which are like an electronic collection of breadcrumb trails that show where youre been).


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5.5 THE FUTURE OF GPS:

Modern technology rapidly evolves, and the same holds true for G PS. Since

consumer G PS. Since consumer G PS receivers first became available in the mid-1990s, the

market has grown tremendously because of cheaper receives prices and new ways to use G PS. A peek into crystal ball shows what the future may hold for G PS.

MOR E ACCURAT E :

The United States has started planning the next generation of G PS, dubbed G PS III. Driving

factors are better accuracy and reliability, improved resistance to signal jamming, and the

looming E uropean G alileo system. Increasing the number of WAAS satellites in orbit is also

planned.

SMALL E R:

G PS receivers will continue to shrink . G PS units already are integrated into wristwatches,

and PC Card G PS receives can plug into a laptop or PDA.

The three limiting factors that prevent a consumer receiver from shrinking are antenna size,

screen size, and power source size.

CH E APE R:

Prices will continue to decline as manufacturing costs decrease and production quantities

increase.

E ASI E R TO US E :

Simplified and less technical user interfaces will become more of a priority as G PS receivers

become more appliances like to meet the needs of specialized markets.

MOR E INT EG RAT E D:


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G PS receivers are being integrated into cars and trucks, cellphones, PDAs, Family Radio service

(FRS) radios, and other consumer electronic devices. E xpect some new products and services

that take advantage of location-aware data.

LE SS WIR E D

Most G PS receivers transfer data from personal computers through a cable Wireless technologies

such as Bluetooth ( www.bluetooth.com ) and wireless USB are well suited for fast and easy data

transfer.

5.6 APPLICATIONS OF GPS

Location - determining a basic position

Navigation - getting from one location to another

Tracking - monitoring the movement of people and things

Mapping - creating maps of the world

Timing - bringing precise timing to the world


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CHAPTER 6

FACE RECOGNITION


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6.1 INTRODUCTION

Humans often use faces to recognize individuals and advancements in

computing capability over the past few decades now enable similar recognitions automatically.

E arly face recognition algorithms used simple geometric models, but the recognition process has

now matured into a science of sophisticated mathematical representations and matching

processes. Major advancements and initiatives in the past ten to fifteen years have propelled face

recognition technology into the\ spotlight. Face recognition can be used for both verification and

Identification (open-set and closed-set). There are two predominant approaches to the face

recognition problem: geometric (feature based) and photometric (view based). As reasercher

intrest in face recognition continued, many different algorithms were developed in which

Principle Component Analysis( PCA ) is used here.

6.2 PRINCIPLE COMPONENT ANALYSIS

6.2.1. INTRODUCTION

The Principal Component Analysis (PCA) is one of the most successful

techniques that have been used in image recognition and compression. PCA is a statistical

metho d under the broad title of factor analysis. The purpose of PCA is to reduce the large

dimensionality of the data

space (observed variables) to the smaller intrinsic dimensionality of feature space (independent

variables), which are needed to describe the data economically. This is the case when there is a

strong correlation between observed variables.

The jobs which PCA can do are prediction, redundancy removal, feature

extraction, data compression, etc. Because PCA is a classical technique which can do something

in the linear domain,applications having linear mo dels are suitable, such as signal pro cessing,

image processing, systemand control theory, communications, etc.


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Fig 6.1 FACE RECOGNITION BLOCK DIAGRAM


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Face recognition has many applicable areas. Moreover, it can be categorized into face

identification, face classification, or sex determination. The most useful applications contain

crowd surveillance, video content indexing, personal identi cation (ex. drivers licence), mug

shots matching, entrance security, etc. The main idea of using PCA for face recognition is to

express the large 1-D vector of pixels constructed from 2-D facial image into the compact

principal components of the feature space. This can be called eigenspace pro jection. E igenspace

is calculated by identifying the eigenvectors of the covariance matrix derived from a set of facial

images(vectors). The detailsare described in the following section.Section 2 describes

mathematical formulation of PCA. More details about face recognition byPCA are given in

Section 3. Implementation and some results are shown in Section 4. Finally, present critical

reviews in Section 5.

6.2.2. MATHEMATICS OF PCA

A 2-D facial image can be represented as 1-D vector by concatenating

each row (or column) into a long thin vector. Lets suppose we have M vectors of size N (=

rows of image columns of image) representing a set of sampled images. pjs represent the

pixel values.

xi = [p1 . . . pN ]T , i = 1, . . . , M ....(1)

The images are mean centered by subtracting the mean image from each image vector. Let m

represent the mean image.

And let wi be de ned as mean centered image

wi = x i m .... (3)

Our goal is to find a set of eis which have the largest possible projection onto each of the wis.


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up a nite number of image vectors, M, the rank of the covariance matrix cannot exceed M - 1

(The -1 come from the subtraction of the mean vector m).

The eigenvectors corresponding to nonzero eigenvalues of the covariance

matrix produce an orthonormal basis for the subspace within which most image data can be

represented with a small amount of error. The eigenvectors are sorted from high to low

according to their corresponding eigenvalues. The eigenvector associated with the largest

eigenvalue is one that reflects the greatest variance in the image. That is, the smallest eigenvalue

is associated with the eigenvector that finds the least variance. They decrease in exponential

fashion, meaning that the roughly 90% of the total variance is contained in the first 5% to 10%

of the dimensions.

A facial image can be pro jected onto M ( M ) dimensions by computing

where vi = eT i wi . vi is the ith coor d inat e of the facia l imag e in the new s pac e, which ca me to

be the principal component. The vectors ei are also images, so called, eigenimages, or eigenfaces

in our case, which was rst named by [1]. They can be viewed as images and indeed lo ok like

faces. So, describes the contribution of each eigenface in representing the facial image bytreating the eigenfaces as a basis set for facial images. The simplest method for determining

which face class provides the best description of an input facial image is to nd the face class k

that minimizes the Euclidean distance

where k is a vector describing the kth face class. If k is less than some prede ned threshold ,

a face is classified as belonging to the class k.


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FIG 6.2 BLOCK DIAGRAM FOR PCA


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6.2.3. FACE RECOGNITION

Once the eigenfaces have been computed, several types of decision can be made

depending on the application. What we call face recognition is a broad term which may be

further speci ed to one of following tasks:

identi cation wher e the l abel s of ind ivid ua l s must be obtain ed,

r ecognition of a person , wher e it must be de cided if the ind ivid ua l has al r eady bee n seen ,

cat e gorization wher e the face must be assign ed to a certain cl ass .

PCA computes the basis of a space which is represented by its training vectors.

These basis vectors, actually eigenvectors, computed by PCA are in the direction of the largest

variance of the training vectors. As it has been said earlier, we call them eigenfaces. E ach

eigenface can be viewed a feature. When a particular face is pro jected onto the face space, its

vector into the face space describe the importance of each of those features in the face. The face

is expressed in the face space by its eigenface co e cients (or weights). We can handle a large

input vector, facial image, only by taking its small weight vector in the face space. This means

that we can reconstruct the original face with some error, since the dimensionality of the image

space is much larger than that of face space.

In this report, lets consider face identi cation only. E ach face in the training

set is transformed into the face space and its components are stored in memory. The face space

has to be populated with these known faces. An input face is given to the system, and then it is

pro jected onto the face space. The system computes its distance from all the stored faces.

However, two issues should be carefully considered:

1. What if the image presented to the system is not a face?

2. What if the face presented to the system has not already learned, i.e., not stored as a

knownface?


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The first defect is easily avoided since the first eigenface is a good face filter which

can test whether each image is highly correlated with itself. The images with a low

correlation can be rejected. Or these two issues are altogether addressed by categorizing

following four different regions:

1. Near face space and near stored face = known faces

2. Near face space but not near a known face = unknown faces

3. Distant from face space and near a face class = non-faces

4. Distant from face space and not near a known class = non-faces

Since a face is well represented by the face space, its reconstruction should be similar

to the original, hence the reconstruction error will be small. Non-face images will have a large

reconstruction error which is larger than some threshold r . The distance k determines whether the

input face is near a known face.

6.2.4 IMPLEMENTATION AND RESULTS

It contains ten different imagesof each of 40 distinct subjects. For some subjects, the images

were taken at di erent times,varying the lighting, facial expressions (open/closed eyes,

smiling/not smiling) and facial details (glasses/no glasses). All the images were taken against adark homogeneous background with the subjects in an upright, frontal position (with tolerance

for some side movement). An experiment with a subset of the database, which only contains 12

subjects images, has been performed to ensure how well the eigenface system can identify each

individuals face. There are 5 additional test images, each of which is the known face. I also

appended 2 non-face images to test whether it can detect them correctly.

Figure 3 shows the eigenface images which are originally the eigenvectors ei of the

covariance matrix at E q.6. The first eigenface account for the maximal variation of the trainingvectors. The 10 original training images and their reconstructed versions are depicted in Figure 1

and 2. The result was very successful given the test images in Figure 4. E very test image was

correctly classified.


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Figure 1: Original Images

Fig 2:Reconstructed Images of training Images- They are almost same as the original images

Fig.3: E igen face: the first eigen face account for the maximal variation of the training vectors

and the second one accounts for the second maximal variation, etc.

Test images: the number corresponds the order of the set of original training images in figure 1r*

means the corrected image

1-th 2-th 3-th 4-th 5-th 6-th 7-th 8-th 9-th 10-th

t1 r1 t3 r3 t6 r6 t8 r8 t9 r9


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When two unknown faces in Figure 5 are input to the system, the s at E q. 10 are larger

than the prede ned threshold. In the case of two non-face images in Figure 5, the reconstruction

errors were larger than the reconstruction threshold, then they are not considered as face images.

The MATLAB source codes are attached to the appendix in the end of this summary .

some limitations of the algorithm, which I found from the experiments

y The face image should be normalized and frontal-view

y The system is an auto-asso ciative memory (p.153 in [2]). It is harmful to be overfitted.

y Training is very computationally intensive.

y It is hard to decide suitable thresholds - It is kind of Art !

y The suggested methods to deal with unknown faces and non-faces are not good enough to

y differentiate them from known faces


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CHAPTER 7

SOFTWARES USED


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7.1 KEIL IDE

Keil Software is the leading vendor for 8/16-bit development tools (ranked at first

position in the 2004 E mbedded Market Study of the E mbedded Systems and EE Times

magazine). Keil Software is represented world-wide in more than 40 countries. Since the market

introduction in 1988, the Keil C51 Compiler is the de facto industry standard and supports more

than 500 current 8051 device variants. Now, Keil Software offers development tools for ARM.

Keil Software makes C compilers, macro assemblers, real-time kernels, debuggers, simulators,

integrated environments, and evaluation boards for the 8051, 251, ARM, and XC16x/C16x/ST10

microcontroller families.

Keil Software is pleased to announce simulation support for the Atmel AT91 ARM family of

microcontrollers. The Keil Vision Debugger simulates the complete ARM instruction-set as

well as the on-chip peripherals for each device in the AT91 ARM/Thumb microcontroller family.

The integrated simulator provides complete peripheral simulation. Other new features in the

Vision Debugger include:

y An integrated Software Logic Analyzer that measures I/O signals as well as program

variables and helps developers create complex signal processing algorithms.

y An E xecution Profiler that measures time spent in each function, source line, and assembler

instruction. Now developers can find exactly where programs spend the most time.

"Using nothing more than the provided simulation support and debug scripts, developers can

create a high-fidelity simulation of their actual target hardware and environment. No extra

hardware or test equipment is required. The Logic Analyzer and E xecution Profiler will help

developers when it comes time to develop and tune signaling algorithms." said Jon Ward,

President of Keil Software USA, Inc.


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7.1.1 KIEL COMPILER

The Keil C51 C Compiler for the 8051 microcontroller is the most popular 8051 C

compiler in the world. It provides more features than any other 8051 C compiler available today.

The C51 Compiler allows you to write 8051 microcontroller applications in C that, once

compiled, have the efficiency and speed of assembly language. Language extensions in the C51

Compiler give you full access to all resources of the 8051.

The C51 Compiler translates C source files into relocatable object modules which contain full

symbolic information for debugging with the Vision Debugger or an in-circuit emulator. In

addition to the object file, the compiler generates a listing file which may optionally include

symbol table and cross reference

Nine basic data types, including 32-bit I EEE floating-point,

Flexible variable allocation with bit , data , bdata , idata , xdata , and pdata memory types,

Interrupt functions may be written in C,

Full use of the 8051 register banks,

Complete symbol and type information for source-level debugging,

Use of AJMP and ACALL instructions,

Bit-addressable data objects,

Built-in interface for the RTX51 Real-Time Kernel ,

Support for dual data pointers on Atmel, AMD, Cypress, Dallas Semiconductor, Infineon,

Philips, and Triscend microcontrollers,

Support for the Philips 8 xC750, 8 xC751, and 8 xC752 limited instruction sets,

Support for the Infineon 80C517 arithmetic unit.


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Fig 7.1 KEIL IDE


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7.2 ORCAD-PCB DESIGN.

The capability to provide fast and universal design entry makes orcad capture

design entry the most widely used schematic entry system in electronic design today. Whether

used to design a new analog circuit, revise a schematic diagram for an existing printed circuit

board (PCB), or design a digital block diagram with an HDL module, orcad capture provides the

tools needed to enter, modify, and verify the PCB design. Orcad Capture CIS integrates the

Orcad Capture schematic design application with the features of a component information

system (CIS).

Fig 7.2 ORCAD DESIGN

7.2.1 ORCAD PCB DESIGN TECHNOLOGIES


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ORCAD products have a proven track record of innovation in the PCB

personal productivity market. Available as stand-alone tools or in comprehensive suites, they

allow designers to realize products from conception to manufacturing output. E asy to use and

intuitive, they offer exceptional value, and orcad technology provides easy migration to the

platform.

7.2.2ORCAD CAPTURE

ORCAD Capture is a complete solution for design creation, management, and

reuse. Its ease-of-use allows designers to focus their creativity on design development rather than

tool operation. The hierarchical Schematic Page E ditor combines a windows user interface with

functionality and features specifically for design entry tasks and for publishing design data.

Centralized project management provides seamless interchange of schematic

data for circuit simulation, board layout, and signal integrity analysis. A configurable design rule

check (DRC) mechanism helps eliminate costly engineering change orders ( E COs). Basic bill of

materials (BOMs) outputs are created from data schematic data for circuit simulation, board

layout, and signal integrity analysis. A configurable design rule check (DRC) mechanism helps

eliminate costly engineering change orders ( E COs). Basic bill of materials (BOMs) outputs are

created from data contained in the schematic database.

7.2.3ORCAD CAPTURE CIS

ORCAD capture CIS is designed to reduce production delays and cost overruns

through efficient management of components. It reduces the time spent searching existing parts

for reuse, manually entering part information content, and maintaining component data. Users

search parts based on their electrical characteristics and orcad capture CIS automatically

retrieves the associated part. Flexible and scalable, the solution is quickly implemented.

Orcad capture CIS is ideal for individual design teams or multi-site teams who need to

collaborate across multiple locations, orcad capture CIS gives designers access to correct part

data early in the design process and enables complete component specifications to be passed to


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board designers and other members of the design team, reducing the potential for downstream

errors. It provides access to cost information so designers can use preferred, lower cost, and in

stock parts. The embedded part selector accesses information stored in MRP/ E RP systems and

engineering databases and synchronizes externally sourced data with the schematic design

database, so bills of materials can be automatically generated.

Fig 7.2 ORCAD CAPTURE

7.2.4 EATURES


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SCHEMATIC EDITOR

The full-featured schematic editor allows users to view and edit multiple schematic

designs in a single session. Design data is easily reused by copying and pasting within or

between schematics. Parts are quickly selected from a comprehensive set of functional part

libraries. Configurable design and electrical rule checkers ensure design integrity. In-line editing

of parts allows pin name and number movement. A user interface has been provided to add

critical constraints for users of the orcad capture to orcad PCB editor flow.

PROJECT MANAGER

The Project Manager simplifies organizing and tracking the various types of data

generated in the design process. An expanding tree diagram makes it easy to structure andnavigate design files, including those generated by pspice simulators, orcad capture CIS, and

other plugins. A Creation Wizard guides users through all the resources available for a specific

design flow. Users can navigate the entire schematic structure and instantly open specific

elements a schematic page, part, or net with the hierarchy browser.

HIERARCHICAL DESIGN AND REUSE

Orcad capture boosts schematic editing efficiency by enabling subcircuit reusewithout having to make multiple copies. Using hierarchical blocks, simply reference the same

subcircuit multiple times. Automatic creation of hierarchical ports eliminates potential design

connection errors. Ports and pins can be updated dynamically for hierarchical blocks and

underlying schematics. Added navigation utilities recognize block boundaries and accessibility

using keyboard shortcuts.

THE LIBRARIES AND PART EDITOR

The library editor is accessed directly from the orcad capture user interface. Users

can create and edit parts in the library or directly from the schematic page without interrupting

workflow. Intuitive graphical controls speed schematic part creation and editing. New parts are


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created quickly by modifying existing ones. New parts can also be created from spread sheets. A

library part generator automates the integration of field programmable gate arrays (FP G As) and

programmable logic devices (PLDs) into the system schematic. The G enerate Part feature

simplifies the creation of core FP G A library parts for high-pin-count devices. These parts can be

split into multiple parts.

EASY DATA ENTRY

Designers can access all part, net, pin, and title block properties, or any subset, and

make changes quickly through the orcad capture spreadsheet property editor. It simply requires

selecting a circuit element, grouped area, or entire page, and then selecting add/edit/delete part,

net, or pin properties.

BENEFITS

Provides fast, intuitive schematic editing

Boosts schematic editing efficiency by design reuse

Automates the integration of FP G A and PLD devices

Makes changes quickly through a single spreadsheet editor

Imports and exports virtually every commonly used design file format

Reduces delays caused by out-of-stock parts (CIS)

Promotes reuse of preferred components (CIS)

E ncourages reuse of known good part data (CIS)

Makes reuse of duplicate circuitry easy through hierarchical blocks (CIS)


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7.3 FLASH PROGRAMMER

Straightforward and intuitive user interface

Five simple steps to erasing and programming a device and setting any options desired

Programs Intel Hex Files

Automatic verifying after programming

Fills unused Flash to increase firmware security

Ability to automatically program checksums. Using the supplied checksum calculation

routine your firmware can easily verify the integrity of a Flash block, ensuring no

unauthorized or corrupted code can ever be executed

Program security bits

Check which Flash blocks are blank or in use with the ability to easily erase all blocks in

use

Read the device signature

Read any section of Flash and save as an Intel Hex File

Reprogram the Boot Vector and Status Byte with the help of confirmation features that

prevent accidentally programming incorrect values

Display the contents of Flash in ASCII and Hexadecimal formats

Single-click access to the manual, Flash Magic home page and NXP Microcontrollers

home page

Ability to use high-speed serial communications on devices that support it. Flash Magic

calculates the highest baudrate that both the device and your PC can use and switches to that

baudrate transparently


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Fig 7.4FLASH PROGRAMMER

Fig 7.5 HEX FILE CONVERSION


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7.4 EMBEDDED C

The C for microcontrollers and the standard C syntax and semantics are

slightly different. The former is aimed at the general purpose programming paradigm

whereas the latter is for a specific target microcontroller such as 8051 or PIC. The

underlying fact is th

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