Slipstream Processors by Pujan Joshi1 Pujan Joshi May 6 th, 2008 Slipstream Processors Improving both Performance and Fault Tolerance

Slipstream Processors by Pujan Joshi 1

Pujan Joshi

May 6th, 2008

Slipstream ProcessorsImproving both Performance and Fault

Tolerance


Analogy - NASCAR


The ParadigmIt is possible to make forward progress by executing only

a subset of the original program.Ineffectual Instructions

Non-modifying writes Unreferenced writes Correctly-predicted branches...also their dependence chains


SlipstreamingA slipstream processor creates a shorter instruction stream

by skipping the ineffectual instructions.

Two copies of the same program is run; the full program and the shortened program.


Slipstream ExecutionThe shortened program is speculatively reduced and runs

slightly ahead of the other.

The leading program is called the advanced stream (A-stream) and the trailing program is called the redundant stream (R-stream).


Advanced StreamA-stream

Executes fewer instructionNeeds some hardware supportResults are communicated to R-stream


Redundant StreamR-stream

Executes the whole programExecutes efficiently as it receives control and data output as

predictions from A-streamcompares the values against its own outcomes, if a deviation

is detected, the corrupted A-stream context is recovered from the R-stream context.


InterpretationA-stream: a program based predictor

R-stream: a fast checker

A-stream

R-stream

checker


Slipstream Architecture


Each is a conventional superscalar processor with a

branch predictor, instruction and data caches, and an execution engine and a reorder buffer.

New Components AddedInstruction Removal predictorInstruction Removal detectorDelay bufferRecovery controller

Micro-Architecture


The Instruction R emovalDetector

Monitors the R-stream.Checks for ineffective instructions.Checks for correctly predicted branches.Conveys the IR-predictor about the instructions that can

be skipped.


Removal MechanismRemoves the confident branch predictions and

computations needed for them.Removes highly value-predictable computations. Ineffectual and branch predictable instructions removed

and PC is updated.Computations replaced by the value.


Instruction Removal Predictor

• Generates PC for next block of instructions.• Removes the instructions suggested by the IR-

detector in the fetch block.

Strategy:• Built on top of conventional trace-predictor.• Added few more information like IR-vector,

Intermediate PC & Confidence Counter.


Continued..Confidence Counters:IR-detector updates this counter.Corresponding instruction is removed if the counter is

saturated.IR-vector and intermediate PCs used to remove

instruction.


Delay BufferFIFO Queue.Control flow – trace ids & IR-vectorData flow – operand register names, values & LS

addresses.A-stream enqueues & R-stream dequeues.


Recovery ControllerA-stream context can be corrupted.Maintains the address where the store instructions are

writing.Recovers the corrupted A-stream context from R-stream

(Both register and memory values).Delay Buffer flushed.PCs of A-stream restored.IR-predictor backed up to precise program counter.Entire register file copied via delay buffer.


Simulation Environment


Slipstream Performance


Doubling superscalar complexity


Results7% average performance improvement is achieved by

harnessing an otherwise unused, additional processor in a Single Chip Multi-Processor (CMP).

The performance improvement due to doubling the window size and issue bandwidth of the superscalar processor is on average of 28%.


AdvantagesExploiting existing, otherwise unused

processor in a CMPspeeds up a single programCompetitive with superscalar

1/4 speedup of larger superscalar. (Improved slipstream design performs comparably or better: MICRO-33.)


Related Work/MotivationA-Stream/R-Stream Simultaneous Multithreading.

Reduced programs with same output.


CMP/SMT: throughput and parallel program performance.

Slipstream: improved single-program performance and reliability.

AR-SMT / SRT: high reliability with little performance overhead.

More Flexible Architecture


References“Slipstream Processors: Improving both Performance and Fault

Tolerance”, Karthik Sundaramoorthy, Zach Purser, Eric Rotenberg.

“A Study of Slipstream Processors”, Zach Purser, Karthik Sundaramoorthy, Eric Rotenberg.

“A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors”, Jinson J. Koppanalil and Eric Rotenberg.

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Slipstream Processors by Pujan Joshi1 Pujan Joshi May 6 th, 2008 Slipstream Processors Improving both Performance and Fault Tolerance