Slide: 1 International Conference on Electronics, Circuits, and Systems 2010

Department of Electrical and Computer EngineeringUniversity of New MexicoAlbuquerque, NM 87111

Ryan Helinski, Thomas LeBoeuf, Colby Hoffman, and Payman Zarkesh-Ha

A Linear Digital VCO for Clock Data

Recovery (CDR) Applications

Department of Electrical & Computer Engineering

Slide: 2 International Conference on Electronics, Circuits, and Systems 2010

Outline

Motivation

Basic Building Blocks

Clock-Data Recovery Circuit

Layout Design and Fabrication

Test and Measurement Results

Conclusion

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Motivation

Demands for multi-gigabit SerDes (e.g. gigabit Ethernet, PCI express, and hard disk drive Interface)

Lower VDD requires higher gain VCO, which results in higher noise sensitivity

Dual-control VCO for fine and course tunes becomes very attractive

OutputFrequency

Dual-controlVCO

Fine Control

Course Control

Low gain

High gain

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Ring-Oscillator-Based VCO Pros

Easy to Implement in a Small Area Robustness over Process and Temperature Range

Cons Limited Control Voltage Range Limit Output Swing Highly Non-Linear Characteristics

[Sidiropoulos’00]

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Basic Proposed Delay Element

VDD

CLVin

Vout

Iref

M1 M2

M3 M4

Vin Vout

Iref

td = CL VDD

2Iref

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Detail CDR Circuit Diagram

VDD

CL

Vout

M1 M2

M3 M4

M6

M7

VDD

M8

VDD

M9

VDD

M5

Vcourse

Vfine

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High-level Block Diagram of SerDes

10 b

it S

hif

t R

egis

ter

(sta

rt b

it=

1, s

top

bit

=0)

A_0

A_1

A_2

A_3

A_4

A_5

A_6

A_7

ClockGenerator

S_out

LVDS TX LVDS RX

10 bit Shift Register(start bit=1, stop bit=0)

B_

0

B_

1

B_

2

B_

3

B_

4

B_

5

B_

6

B_

7

ClockRecovery

Serlializer DeserlializerSend

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Detail Schematic of the Serializer

DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q DSend

S/R

QDSend

S/R

Q

D QD Q

A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0

TX_CLK

SEND

The serializer clock is generated internally with a gated ring oscillator

The input digital data (A_0 to A-7) is then serialized using a chain of shift register

The input send is used to trigger the send command

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Serializer Layout

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Detail Schematic of the Deserializer

The serializer clock is generated by the CDR circuit

The input serial data S_IN is then deserialized using chain of shift registers

The deserialization starts automatically once the start bit is detected.

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D Q

Rst_clkb

D QD QD QD Q

D QD Q D QD Q D QD Q D QD Q D QD Q D QD Q D QD Q D QD Q

B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0

S_IN

CLK_REC

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Deserializer Layout

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Clock and Data Recovery (CDR) Circuit

The CDR circuit consists of Hogge phase detector, 2) Charge pump and loop filter, and 3) the proposed voltage controlled oscillator

D QD Q

D QD Q

D QbD Qb D QbD Qb

Data Input

CLK_REC

CLK Freq. Divider

Charge Pump and Loop Filter

Hogge Phase Detector

Fine Tuned VCO

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Clock and Data Recovery (CDR) Layout

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LVDS Transmitter and Receiver

Better noise control and lower power consumption is provided by low-voltage differential signaling (LVDS)

VDD

VLVDS

VLVDS VLVDS

TX

RS

LVDS Twisted Lines

LVDS Transmitter

LVDS Receiver

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LVDS Transmitter and Receiver Layout

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The SerDes Testchip Layout Photograph

Chip size = 1.5mm x 1.5mm

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The VCO Specifications

MOSIS 0.5um ON Semiconductor CMOS Process

VCO center frequency of 89 MHz

VCO gain of 6MHz/V

VCO frequency range from 81MHz to 100MHz

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VCO Frequency versus Control Voltage

80

82

84

86

88

90

92

94

96

98

100

0 1 2 3 4 5

Control Voltage [V]

Fre

qu

en

cy

[MH

z]VCO Gain = 6 MHz/VCenter Frequency = 89 MHz

Slide: 19 International Conference on Electronics, Circuits, and Systems 2010

SerDes BER Characteristics

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

84 86 88 90 92 94

Frequency [MHz]

Bit

Err

or

Ra

te [%

]

Lock Range

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SerDes Test Waveforms at 90MHz

Test patterns: 0x5C and 0x11

Successful transmission

Transmission length 10.23 feet

Lock frequency of 90 MHz

LVDS voltage of 3.705V

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SerDes Characterization Summary

Supply Voltage 5 V

LVDS Voltage 3.3V

VCO Gain 6 MHz/V

CDR Free Running Freq. 91 MHz

CDR Lock Range 4.6 MHz

SerDes Power Dissipation 35 mW

SerDes Characterization

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Conclusion

A linear dual control VCO circuit was proposed.

To prove the concept a testchip of SerDes was demonstrated using the proposed CDR concept.

The testchip was manufactured using 0.5um ON semiconductor through MOSIS.

The measurements demonstrate that the CDR concept is practical and can be scalable to higher frequency ranges.

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Acknowledgement

The support of educational MOSIS program to manufacture the chip is greatly appreciated.