Sleep Transistor Sizing Using Timing Criticalityand Temporal Currents
Anand Ramalingam, Bin Zhang, Anirudh Devgan and David Z. Pan Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712
Austin Research Laboratory, IBM Research Division, Austin, TX 78758{anandram,bzhang,dpan}@ece.utexas.edu and [email protected]
Abstract Power gating is a circuit technique that enables highperformance and low power operation. One of the challengesin power gating is sizing the sleep transistor which is used togate the power supply. This paper presents a new methodologybased on timing criticality and temporal currents to size thesleep transistor. The timing criticality information and temporalcurrent estimation are obtained using static timing analyzer. Theresults obtained indicate that our proposed technique results inarea reduction of sleep transistors by 80% and 49% comparedto module based design and cluster based design respectively.
I. INTRODUCTION
As technology scales, the supply voltage (VDD) needs tobe scaled down since it has a quadratic relationship withthe dynamic power. But scaling down VDD alone results inloss of performance. One way to maintain performance, isscaling down both VDD and VT [1]. But scaling down VTexponentially increases the subthreshold leakage current. Oneof the techniques to reduce subthreshold leakage is powergating. Power gating is a circuit technique in which the sourcenodes of the gates in the functional block which were groundedare now connected to the drain of the NMOS sleep transistor.In the active mode, the sleep transistor is turned on to retainthe functionality of the circuit. In the sleep mode, the sleeptransistor is turned off, and the source nodes of the gates in thefunctional block float, thus cutting off the leakage path. Sleep
sleep
Vsleep
Functionalblock
VDD
Fig. 1. Power gating
Functionalblock
VDD
VsleepI(t)
Rsleep
Fig. 2. Sleep transistor as a resistor
transistor sizing is one of the major challenges in power gatedcircuits. If we overestimate the size we end up wasting siliconarea and increasing the switching energy. If we underestimatethe size, the required performance might not be achieved dueto the increased resistance to the ground [2].
In the literature, various methods have been proposed to sizethe sleep transistor. In [3], module based design was proposedwhere a single sleep transistor is used for the entire circuit.In [4], the circuit is partitioned into clusters to minimize themaximum simultaneous switching current. Each cluster hasan individual sleep transistor. In [5], all the individual sleeptransistors of [4] are wired together and the resulting mesh iscalled the distributed sleep transistor network (DSTN). Thedischarging current is shared by the sleep transistor networkwhich reduces the size of the sleep transistor. The sizing inall the above methodologies are based on the maximum worstcase switching current Ipeak [5].
In [2] it was shown that the sleep transistor can be ap-proximated by a linear resistor that creates a finite voltagedrop Vsleep RsleepI(t) where I(t) is the switching currentthrough the sleep transistor as shown in Fig. 2. It is importantto notice that different gates in a given path will see switchingcurrents of different magnitude through the sleep transistor.The delay of a gate is inversely proportional to the gate driveVGS = VDD Vsleep = VDD RsleepI(t) [6]. To the firstorder, we can state that the penalty experienced by each gatedue to the sleep transistor is proportional to the current I(t)flowing through the sleep transistor when the gate is switching.Hence if we are able to estimate I(t) efficiently, we canuse I(t) to size the sleep transistor instead of Ipeak whichpenalizes different gates in a path uniformly.
In this paper, we make the following contributions.
Sleep transistor sizing making use of timing criticalityand temporal switching current I(t) of the circuit, and
An efficient method to estimate the temporal switchingcurrent I(t) of the circuit.
The results obtained indicate that our proposed techniqueresults in area reduction of sleep transistors by 80% and 49%compared to module based design and cluster based designrespectively.
The remaining part of the paper is organized as follows.Section II derives formula to size the sleep transistor. SectionIII presents a technique to estimate the switching current ofa circuit and timing criticality based sleep transistor sizing isdiscussed in Section IV. Section V presents results for variousbenchmark circuits followed by conclusions in Section VI.
II. SIZING THE SLEEP TRANSISTOR
The delay of a gate (d) can be expressed as [6],
d CLVDD(VDD VTL)(1)
where CL is the load capacitance at the gate output, VTL is thelow threshold which is 0.7V , VDD = 3.3V , and the velocitysaturation index 1 for 0.18m CMOS technology.
The delay of a gate with the sleep transistor can be ex-pressed as,
sleepd CLVDD
((VDD Vsleep) VTL)(2)
where Vsleep is the potential of the virtual ground as shown inFig. 1. Let sleepd = (1+)d, where d is the penalty due tothe sleep transistor. Applying Taylor series to the denominatorand approximating the sleep transistor as a linear resistorRsleep [2], the penalty can be written as,
d VsleepVDD VTL
d =RsleepI(t)VDD VTL
d (3)
where I(t) is the switching current through the sleep transistor.A path in a circuit consists of various gates and these gates
experience discharging currents of different magnitudes. FromEquation 3, we find that the penalty for a gate due to the sleeptransistor is proportional to I(t). Now the delay penalty for apath (pathpenalty) consisting of various gates can be written as,
pathpenalty =(
RsleepVDD VTL
) gatepath
Ilocal,maxd (4)
where d is the delay of the gate without the sleep transistorand Ilocal,max is defined as,
Ilocal,max = max[t1,t2]I(t) (5)
where [t1, t2] is the time interval over which the gate switches.Notice that the Ilocal,max is the maximum local temporalcurrent over the discharging timing window of the gate.We differ from the previous methodologies in this respectsince they use maximum global current Ipeak . RearrangingEquation 4,
Rsleep =(VDD VTL) pathpenalty
gatepath Ilocal,maxd(6)
The current through the linearly-operating sleep transistor canbe approximated as [4],
Isleep nCox(
W
L
)sleep
(VDD VTL)Vsleep
where n is the mobility of electrons and Cox is the oxidecapacitance. Since the sleep transistor is operating in the linearregion, then Rsleep VsleepIsleep . Then, the size of the sleeptransistor can be written as,(
W
L
)sleep
=1
nCox(VDD VTL)Rsleep(7)
Thus if Rsleep is known, the Wsleep can be determineddirectly. To determine Rsleep, we need an estimate of thetemporal current flowing through the sleep transistor. Thetemporal current estimation technique is described next.
III. TEMPORAL CURRENT ESTIMATION
We present a technique to estimate the worst case currentdischarged by a circuit. The current estimation technique needstiming windows of each gate and current expected to bedischarged by each gate. The timing windows is obtained usingPrimeTime [7]. The expected discharge current (Iexp) of agate is adapted from [4] and the pseudocode is shown below.
FIND-EXPECTED-CURRENT(gate)1 Find Ipeak for each gate in the library using HSPICE2 Iexp = s Ipeak s is the switching factor3 return Iexp
The switching factor s is defined as the probability of theoutput (Y ) switching. Thus s for falling output is,
s = P{Y = 1 0|Y = 1} P{Y = 1}We illustrate Iexp calculation using OR2. The switching factors = 14 34 = 316 . From HSPICE simulations, we find that theIpeak = 0.72ma. Thus the expected current for an OR2 gatein our library is, Iexp = sIpeak = 316 0.72ma = 0.12ma.
After we have calculated Iexp for all the gates in our librarywe can use it for estimating switching current of a circuit andthe pseudocode is presented below.
ESTIMATE-SWITCHING-CURRENT(circuit)1 Run PrimeTime on the circuit to get timing windows2 I(t) 03 for every gate in the circuit4 do Iexp GET-EXPECTED-CURRENT(gate)
Illustrated in Fig. 45 Igate(t) timing windows bounded by Iexp6 I(t) I(t) + Igate(t) Illustrated in Fig. 57 return I(t)
We bound both falling and rising timing windows by thefalling Iexp. The assumption is safe since for any gate, theworst case falling current through ground is always bigger thanthe short circuit current when the output rises. The switchingfactor s is the same for both falling and rising transitions.
To illustrate the current estimation procedure, consider the1-bit carry lookahead adder (CLA) shown in Fig. 3. Thetiming analyzer PrimeTime is run on this circuit to obtain thetiming windows shown in Table I. Fig. 4 shows the currentsassociated with each timing window. To illustrate reading thisgraph, consider the OR2 gate O1 in Fig. 3. The falling windowfor O1 from Table I is [73.92, 260.11]ps. The Iexp of O1 is0.12ma. Thus we have bounding rectangle of current 0.12maover [73.92, 260.11]ps as shown in Fig. 4. Finally, the currentsacross all the timing windows are summed up to find the totaldischarging current of 1-bit CLA shown in Fig. 5. Once thetemporal switching current I(t) has been estimated we canuse that current to size the sleep transistor.
![CMOS Delay-1 (H.1) Transistor Sizing - · PDF fileInverter Layout C] Transistor dimensions specified as Width / Length — Minimum size is 4), / 2R, sometimes called 1 unit In f =](https://img.pdfslide.us/doc/110x75/5a7886327f8b9aa2448d2ea4/cmos-delay-1-h1-transistor-sizing-layout-c-transistor-dimensions-specified.jpg)
