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Introduction to the CCD

•

F u n d a m e n t a l s

•

The CCD Imaging A r r a y

•

Support Electronics

S I Te CCD Technology forSuperior Performance

An Introduction to Scientific ImagingC h a r g e - C o u p l e dD e v i c e s

S C I E N T I F I C I M A G I N G T E C H N O L O G I E S , I N C .

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Table of Contents

Introduction

Fundamentals

MOS Capacitor

CCD Pixel

Dark Current

Charge Transfer Process

Quantum Efficiency

Front Illumination

Back Illumination

Enhancements

MPP

Mini channel

The CCD Imaging Array

Imaging Array Basics

Output Structure

The Functional Diagram

The Timing Diagram

Support Electronics

Architecture

Signal Processing

Gate Drivers

Scientific Imaging Technologies, Inc.

P.O. Box 569Beaverton, Oregon 97075-0569503/644-0688503/644-0798 fax

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Introduction

Charge-coupled devices (CCDs) are the key components in digital imaging cameras.

CCDs take the place of vacuum tube-based imagers and film in conventional cameras. A

high resolution camera can be constructed around this highly sensitive chip by combining

it with a suitable lens system, a cooling method, and operating electronics. CCDs have

wide application in a variety of scientific, astronomical, biomedical, and other commercial

imaging areas.

With process development and design experience dating back to the founding of the

group in 1974, Scientific Imaging Technologies, Inc. (SITe) has become an industry

leader in the research, design, and manufacture of scientific-grade CCDs and imaging

sub-assemblies which contain CCD components. SITe CCDs offer high quantum

efficiency and sensitivity, high resolution, and a dynamic range that can exceed 100dB.

SITe CCDs are sufficiently sensitive to detect reliably fewer than ten photons. Carefully

designed and matched support circuitry enables SITe devices and systems to achieve

optimum performance.

This technical note provides an introduction to the underlying concepts and operation

of the charge-coupled device. SITe assumes that the reader has some understanding of

basic solid state physics.

For more information about CCDs, contact the SITe customer service department.

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Fundamentals

The MOS Capacitor

The simplest of all MOS (Metal-Oxide-Semiconductor) structures is the MOScapacitor. This device forms the basis for the charge-coupled device; an understanding of the structure is useful in order to comprehend CCD operation.

There are two types of MOS capacitors: surface channel and buriedchannel. These devices differ only slightlyin their fabrication; however, the buriedchannel capacitor offers major advantageswhich make it the structure of choice forthe fabrication of CCDs. Virtually all CCDsmanufactured today utilize the buriedchannel structure, and we will focus onthis preferred structure.

Aschematic cross section of theburied channel capacitor is shown inFigure 1. Typically, the device is built on a p-type substrate, as shown. An n-typeregion (~1µm thick) is formed on the surface. Next, a thin silicon dioxide layer is grown (~0.1µm thick) followed by ametal or heavily doped polycrystalline silicon layer. The latter layer forms theelectrode or gate and completes thecapacitor.

Figures 2a, b, and c illustrate calculatedelectron energy and the electrostaticpotential beneath the electrode for a typicalburied channel capacitor at several different bias conditions. As usual, theelectron seeks a condition of lowest potential energy. However, since thepotential energy of the electron is

Ep = - |q |

electrons will seek a position where thelocal electrostatic potential is highest. (In this expression, q is the magnitude ofthe charge on an electron and Ψ is theelectrostatic potential.)

For the unbiased condition (Figure2a), the number of electrons in the n-typeregion is characterized by the equilibriumFermi level. The bands are flat and theelectrostatic potential is uniform within then-type region. However, when the n-typeregion is fully depleted of electrons, a minimum occurs in the electron potentialenergy. The minimum is located within then-type region and at some distanceremoved from the silicon-silicon dioxide(Si-SiO 2) interface (Figure 2b). This minimum in the energy (or maximum inthe potential) is where excess electronscollect. (The difference between the buriedand surface channel capacitors is thepresence or absence of the n-type layer;in the surface channel structure, thepotential maximum is located directly atthe Si-SiO2 interface.)

Figure 1Buried channel capacitor.

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Figure 2AEquilibrium energy band diagram.

Figure 2BEnergy band diagram andelectrostatic potential.Zero bias.

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Figure 2c illustrates the situation where abias of +10 V has been applied to theelectrode with the substrate held at groundpotential and some charge (generatedoptically, for example) has collected in the potential minimum. The region wherethe charges collect is referred to as thechannel; since this structure is below thesilicon surface, the term buried channel is used. Note that the potential in thechannel is flat (i.e. the field is zero) in theregion where the charge has collected. If itwere not, the electrons would move tomake the field zero in the channel.

Figure 2CEnergy band diagram andelectrostatic potential. 10volt bias with charge.

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The measured variation in channelpotential, with the bias applied to the electrode, is illustrated in Figure 3 for atypical buried channel capacitor. Overmuch of the range of the gate voltage, the channel potential is essentially linearlyrelated to the gate bias. However, for values of the electrode bias less thanabout -6 V the channel potential is pinnedat a fixed value. This state is termed inversion. Under these conditions, the biason the electrode is sufficiently negative toattract holes to the Si-SiO2 interface. Any further decrease in the gate voltagemerely attracts more holes to the surfaceand does not affect the underlying channelpotential. This pinned feature of the channel potential curve is utilized in MPPoperation which is discussed later. Theexact form of the channel potential curve depends principally on doping concentrations, and the oxide thickness.

Figure 3Typical channel potential asa function of gate bias.

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Figure 4 illustrates a practical buriedchannel structure. The additional featurepresented in this figure is the presence offield oxide regions on either side of theburied channel structure. These regionsusually have heavily doped p-type diffusions beneath the oxide layer andbecause of the heavy doping combinedwith the thickness of the field oxide (~0.5-1.5µm), the electrostatic potential beneath the gate in this region is relativelyinsensitive to the voltage or changes in thevoltage on the gate. In this way, chargewhich is collected in the buried channeldevice can be confined to a regionbeneath an electrode on top of thin gateoxide. These confining regions are calledchannel stops.

It is not necessary that the electrodebe surrounded on all sides by field oxide. Note that the potential energy of an electron is lower under an electrodethat is biased at +10 V than one that isbiased at 0V. Consequently, a neighboringgate can also be used to confine the charge.

In summary, the features of the buriedchannel capacitor that make it attractive inscientific imaging applications are:

• the ability to create a potential well in alocal region beneath a single electrode;

• the ability to modulate or control thepotential under the gate;

• the storage location (channel minimum)is positioned away from the Si-Si02

interface and the states located there;• low dark current makes it possible to

store signal charge for long periods of time (tens of seconds to hoursdepending on operating conditions);

• the charge that collects can be generated optically, injected electrically, or created by charged particles such as cosmic rays, protons, or high energy photons (x-rays, gamma-rays);

• the ability to move charge from a position beneath one electrode to asecond, neighboring electrode rapidlyand with very low loss.

Figure 4Practical buried channelcapacitor.

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CCD Pixel

A single CCD pixel (picture element) is illustrated in Figure 5. This figure shows three polysilicon gates orientedperpendicular to two-channel stop regions.Between the channel stop regions lies the buried channel. If the potential on themiddle electrode is more positive than thatapplied to either of the other two gates, alocal potential energy minimum will beformed under the middle gate. When photons strike the pixel, electron-holepairs are created via the photoelectriceffect. Electrons created within the potential minimum will be collected there.Electrons that are created in the channelstop region or in the substrate beneath thepixel may diffuse to the minimum and be collected. In either case, the holes diffuse to and are collected in the p-typesubstrate. The quantity of charge that iscollected in the well is linearly related tothe intensity of the photon flux and to thetime over which the light is allowed to fallon the pixel (integration time).

Other formats for the CCD pixel exist.There are structures that utilize two poly-silicon gates to define a pixel and somethat use four. There is even a technologythat uses a single gate in combination withmultiple implants to define the pixel region.However, the technology most often usedin the fabrication of scientific-grade CCDsis the three phase structure illustrated inFigure 5. The prevalence of the three

phase technology is due principally tohigher yield and process tolerance of thistechnology.

Dark Current

Dark current may be defined as theunwanted charge that accumulates inCCD pixels due to natural thermalprocesses that occur while the deviceoperates at any temperature aboveabsolute zero. At any temperature, electron-hole pairs are randomly generatedand recombine within the silicon and at thesilicon-silicon dioxide interface. Dependingon where they are generated, some ofthese electrons will be collected in theCCD wells and masquerade as signalcharges at the output. Large quantities ofdark current limit the useful full well of thedevice, because the generation process israndom, the dark current will contributenoise.

The principle sources for dark currentin order of importance are generation at the silicon-silicon dioxide interface,electrons generated in the CCD depletionregion, and electrons that diffuse to theCCD wells from the neutral bulk. The firsttwo sources usually dominate the darkcurrent. In addition, the generation ratecan vary spatially over the array leading toa fixed pattern.

Figure 5Three phase CCD pixel.

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Fortunately, dark current sources are strongly temperature dependent. Bysufficiently cooling the device, dark currentcan be effectively eliminated. The extentof cooling required depends largely on thelongest integration time desired and theminimum acceptable signal-to-noise ratio.CCDs are most commonly cooled by using a liquid nitrogen dewar or by coupling the device to a Peltier cooler. The choice depends on how cold onemust operate the device to achieve thedesired performance.

Figure 6 presents calculations of the dark generation rate in e/pix/sec as a function of operating temperature for a 24µm2 pixel. The parameter is the dark current in pA/cm2 at a reference temperature of 293K. For example, if the system requirements dictate a darkgeneration rate of less than 0.0008e/pix/sec. and one has a CCD that generates 10pA/cm2 at 293K, the devicemust be cooled to -82o C. Conversely, ifthe requirements are such that cooling to -50oC is all that is practical and integration times are <1 second, then in order to ensure that, on average,the dark current contributes less than 10electrons/pix/sec, any device with lessthan 500 pA/cm2 dark current at 293K willsuffice.

The curves in Figure 6 can be scaledfor other pixel sizes simply by multiplyingthe dark current values by the ratio pixelarea/(24µm)2.

Figure 6 Effect of temperature ondark current e/pix/sec.Parameter is pA/cm2 at293K.

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Charge Transfer Process

Acharge-coupled device consists of aregular array of individual pixels. Figure 7illustrates a linear array of pixels, eachwith three separate gates, referred to asPhase 1, Phase 2, and Phase 3 (P1, P2,and P3). As shown within the linear register, all P1 gates are connected to thesame bias or clock line; the same is truefor P2 and P3.

Asingle CCD pixel (as defined above)has no means to read out the quantity ofcharge accumulated beneath the integratingelectrode. The process of reading out thissignal charge involves moving the packetfrom the site of collection to a chargedetecting amplifier located at the end ofthe linear array. This is the charge transferprocess, which is illustrated in Figure 7.Assume that charge is collected beneaththe P2 electrodes. At time, t1, we apply a

positive bias to the P3 electrode equal tothe P2 bias, turning the P3 electrodes“on”. The charge located entirely beneaththe P2 electrodes spills to the regionbeneath P3 due to self-induced drift anddiffusion. At t2, the P2 electrodes areturned “off” (i.e., the voltage applied to theP2 gates now equals that on the P1 gates).The charge under P2 now moves rapidlyto a position beneath the P3 electrodes.Note that the charge moves from a position under the P2 gates to one underP3 gates. Indeed, the process of movingor coupling the charge from one gate to itsimmediate neighbor gives rise to the namecharge-coupled device.

Repeating the process using the P3and P1 gates results in the charge movingto a position under the P1 gates. Onemore cycle involving the P1 and P2 gatesleaves the charge packet residing underthe P2 gates again. Note that all charge

Figure 7Three phase chargetransfer process.

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packets move simultaneously one pixel tothe right. In addition, the first packetmoves to the charge detection amplifierwhere the number of signal electrons ismeasured. N such clock cycles arerequired to readout an entire N-pixel linear register.

At all times within a single pixel, a welland a barrier to the next pixel co-exist.These are required in order to store thecharge and to maintain the uniquenessand identity of each charge packet. Notethat by interchanging the roles of any twoof the gates the charge will move to theleft. This flexibility is clearly anotheradvantage of the three phase process.

The effectiveness with which thetransfer process occurs is measured bythe Charge Transfer Efficiency (CTE).Typically, charge may be transferred withan efficiency greater than 99.999% perpixel.

Quantum Efficiency

Quantum efficiency (QE) is the measure of the efficiency with which incident photons are detected. Some incident photons may not be absorbed due to reflection or may be absorbedwhere the electrons cannot be collected.The quantum efficiency is the ratio of thenumber of detected electrons divided by the product of the number of incidentphotons times the number of electronseach photon can be expected to generate.(Visible wavelength photons generate oneelectron-hole pair. More energetic photonsgenerate one electron-hole pair per each3.65 eV of energy.) The energy, E, of theincident photon in eV is

E =

where 1 is the photon wavelength in mm.For wavelengths longer than about

300 µm, the number of collected electronsper pixel per second, Ne, is related to the

Figure 8Typical quantum efficiency.

1 . 2 4

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optical input power density, P, by theexpression

Ne = 5.03 • 1 01 0 PA • Q E

where Pis the optical power density inµW/cm2. A is the pixel area in cm2, 1 is the wavelength in µm, and QE is the quantum efficiency in percent.

Front -Illuminated Devices

Figure 8 depicts the typical QE versus wavelength of various SITe CCDs.In the front illuminated mode of operation,incident photons must pass through a passivation layer as well as the gate structurein order to generate signal electrons.Photons will be absorbed in these layersand not contribute to the signal. Becauseof the high absorption coefficient for short wavelength photons in silicon, thequantum efficiency of front-illuminatedCCDs is poor in the blue and UV regions.Interference effects in the thin gate structure cause undulations in the QEcurve at the longer wavelengths.

Back-Illuminated Devices

In order to increase short wavelengthquantum efficiency, SITe has developed atechnique for thinning the silicon wafer toapproximately 15µm and mounting theCCD with the gate structure against a rigidsubstrate. Light is incident on theexposed, thinned surface. The incidentphotons do not pass through the front surface electrodes and passivation layers.An enhancement layer is then added tothe back surface to create an electric fieldthat forces photo-generated electronstoward the potential wells under the gates.An anti-reflective (AR) coating may beadded to increase optical quantum efficiency. Figure 8 shows QE versuswavelength for typical non-AR coated and AR coated SITe CCDs.

Enhancements

Multi-Phase Pinned Operation

Multi-phase pinned (MPP) deviceshave been developed to reduce or eliminate the Si-SIO2 interface state contribuiton to dark current. As the gateelectrode is driven to more and more negative voltages, a point is reached whenholes are attracted to the interface. (SeeFigure 3.) Any further negative voltagemerely attracts more holes. The presenceof the high density holes at the silicon-silicon dioxide interface fills the interfacestates and reduces or eliminates this contribution to dark current. During integration, it is desirable to bias all thegates into inversion. However, in the normal CCD with all gates inverted, thereis no barrier to separate pixel changes.

In the MPPdevice, an extra implant isplaced under one of the electrodes (usuallyP3). The effect of this implant is to changethe channel potential in such a way thatwhen all the gates are biased into inversion,the channel potential beneath P3 still formsa barrier relative to the neighboring twogates. Charge collects under P1 and P2 while remaining separated from neighboring pixels.

In MPPoperation, it is possible toobtain dark current in the range of 10 to 50pA/cm2 and in some cases less than 10pA/cm2.

Mini-channel

The mini-channel is formed by placingan extra, low dose, n-type implant in thecenter of the buried channel of a CCD register. Its function is to increase thechannel potential locally so that small signal packets (typically 4000 electrons)will be confined to the center of the channel. The advantage of the mini-channel is that it reduces low level signalinteraction with defects in the channel.These defects would otherwise reduce thecharge transfer efficiency. The addition ofthe mini-channel is particularly importantfor devices which operate in a radiationenvironment where protons and/or neutrons produce lattice damage in theCCD channel.

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The CCD Imaging Array

Imaging Array Basics

Imaging arrays usually consist ofsquare or rectangular arrays of pixels. An M x N array may be thought of as acollection of M linear registers of N pixelseach. The M linear registers are alignedvertically side by side and separated bychannel stop regions (see Figure 9).

An additional independent linear register is placed next to the array with itscharge transfer direction orthogonal to thatin the array. This serial register is arrangedso that there is a single pixel adjacent toeach of the M columns, and is terminatedin a charge detection output amplifier.

Following an integration period, arrayreadout involves simultaneously clockingall rows of charge packets one pixeltoward the serial register. This transferprocess causes the bottom row to transferinto the serial register. The charge packetsare then transferred along the serial registertoward the output amplifier where they aredetected. The resulting data stream is apixel-by-pixel, row-by-row representationof the image falling on the CCD.

Output Structure

At the end of the serial register is anoutput amplifier that converts electroniccharge to a voltage. Atypical output struc-ture is shown schematically in Figure 10.

The output structure consists of twoburied channel MOSFETs and a last gate.The function of the last gate is to isolatethe floating diffusion from the serial clocks.The last gate has a separate lead and isgenerally provided a DC bias somewhatmore positive than the low rail of the serialgates. The source of the reset FET liesadjacent to the last gate. This n +-p diodecan be modeled as a capacitor betweenthe channel and the substrate. This diffusion is also connected to the gate ofthe output FET. When the reset FETis of f,this diffusion is electrically isolated and isreferred to as the floating diffusion or theoutput node. The total capacitance of theoutput node, CT, is the capacitance of the floating diffusion plus the parasiticcapacitances associated with metal leadsand the gate of the output FET.

Reading out a pixel begins by turningon the reset FETand setting the floatingdiffusion to the reset drain voltage. The

Figure 9Imaging array.

Figure 10Floating diffusion outputstructure.

Parallel Array

Output Amplifier

Serial Register

M

N

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reset FETis then shut of f, isolating thefloating diffusion. When the final serialgate voltage is dropped, (Figure 10) anyelectrons stored under the gate passunder the last gate and onto the floatingdiffusion. The change in voltage at the output, ∆V, is directly related to the quantity of charge, ∆Q, that is transferredto the floating diffusion and the gain G atthe output FET

∆V= G

The charge of one electron on thefloating diffusion capacitance is enough tochange the output voltage by about amicrovolt. The floating diffusion chargeversus output voltage relationship is generally linear over many decades. The slope of the curve (in microvolts perelectron) is referred to as the output sensitivity or conversion gain.

Although the output signal is actuallyvoltage, it is common practice to refer tothe CCD output signal in terms of electronics.

Many SITe CCDs incorporate a lightlydoped drain (LDD), a fabrication techniquedesigned to reduce the overall capacitanceof the output sense node. The effect is toincrease the conversion gain of the output

amplifier and reduce the noise.

The Functional Diagram

The functional diagram is a schematic representation of the CCD in which eachgate is represented by a box so thatappropriate clocking may be determined.Figure 11 uses a SITe 1024 x 1024 CCDarray as an example. The imaging areaconsists of 1024 columns isolated fromeach other by the channel stop regions.Each column contains 1024 pixels definedby the polysilicon gate structure. The threephases of the parallel gate structure arerepresented by P1, P2 and P3. The parallel array is divided into halves, topand bottom. In each half, all the P1 gatesare connected together. The P2 and P3gates are similarly connected. Serial registers are located at the top and bottomof the array perpendicular to the channelsin the parallel array. The serial registersare also separated into halves, left andright. The gates in these registers are represented by S1, S2 and S3. In eachhalf, all the S1 gates are connectedtogether, all S2 gates and all S3 gates are connected in a similar fashion.

Figure 11Functional diagram.

∆QCT

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The parallel array is coupled to theserial registers through a transfer gate (TGin the diagram). This is a separate parallelgate which is driven to a high state duringtransfer of a line into the serial register,then switched to a low state while chargeis being moved along the serial register.The transfer gate also isolates an unusedserial register preventing unwanted chargefrom entering the array.

The serial registers extend beyond theparallel array. These extra pixels provide areference signal for calibration, since theydo not receive charge directly from theparallel register. At each end of the serialregisters there is a summing well (SW)adjacent to the last gate (LG). The summingwell is similar to the other serial gates butis connected separately. It’s function is toprovide a means to sum consecutivecharge packets in the register withoutadding noise in the process. An outputamplifier is located at each end of eachserial register. Thus, there are four outputsavailable for readout.

This example CCD imager may beread out with one, two, or four outputsoperating simultaneously. When operatedin the full frame mode, the entire image istransferred to one output, and all of thesame numbered phases are clockedtogether. The charge may be clocked outof any output, however; the timing must beappropriate for that output. The gates ofthe unused serial register can be clockedor held at a dc level.

The CCD may also be operated infour output (quad) mode wherein charge isclocked to all four outputs simultaneously.The charge in each quadrant is transferredto the amplifier closest to it. The gates ineach quadrant are driven as appropriatefor full frame operation of that output.

Finally, the CCD illustrated in Figure11 may be operated using two outputs simultaneously. Timing for each of thehalves much be appropriate for the selected outputs. To read out through twoamplifiers on the same serial register, theserial gates are driven as in the quadmode while the parallel array is operatedin the full-frame mode. Conversely, to read out through the amplifiers on opposite serial registers, the parallel array is operated as in quad mode, andthe serial registers are clocked to transferthe charge to the selected amplifier. Thisagain illustrates the flexibility of the threephase process.

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The Timing Diagram

Figure 12 details a typical CCD timing sequence. The parallel shift timingsequence is repeated once per row of pixels transferred to the serial register.Then the serial shift timing is repeatedsufficiently to transfer all of the pixels inthe serial register to the output.

Several rules apply in generating the serial and parallel timing. In order topreserve the identity of change in eachpixel, all gates may not be high at thesame time, and for non-MPP devices, allgates must not be low at the same time or else charge from adjacent pixels will diffuse together. As discussed earlier,MPP devices have a built-in potential barrier under one gate, so all parallelgates may be low during integration. Also, to preserve charge integrity, theMPP barrier phase must not be the last to drop nor the first to rise.

Two adjacent gates may not fall at thesame time or charge transfer efficiency willsuffer. For example, when transferringcharge from the parallel array to the serialregister, the last parallel gate must fall, followed by the transfer gate; then the

serial transfer may commence. The lastparallel gate and the transfer gate mustnot fall together.

A gate transition is started at thebeginning of a state and is assumed tohave changed to the other level by the end of the state. Each state must be longenough for the gate voltage to havechanged for all parts of the array.Particularly in the parallel array, each pixel has a capacitance and is separatedfrom its neighbors by resistance. The transitions of the gates in the center of thearray will not be completed until some timeafter the voltage at the package pin hasreached its final value.

From the functional diagram, it may beseen that there are a number of pixelsbetween the edge of the parallel array andthe output. These “lead in” pixels will beempty at the beginning of each row. Ifmore serial pixel shifts are made than thesum of the lead-in pixels and the numberof columns In the parallel array, theseoverscan pixels will also be empty. Thesetrailing pixels contain very little dark currentso that their level and noise content represent a reference dark level and system plus imager readout noise.

Figure 12Typical CCD timing.

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Support Electronics

Architecture

The architecture of typical CCD support electronics is shown in Figure 13.It consists of modules commonly found inscientific-grade CCD cameras.

At the center of the diagram is theCCD module containing the CCD imager,gate drivers, output signal preamplifier,and the low pass filters for the bias volt-ages. This module is supported by themodules around it. CCD operation is con-trolled through the logic signals which areoutputs of the timing sequencer. The tim-ing sequencer coordinates the time criticaltasks associated with reading out and digitizing an image.

Signal Processing

Anumber of methods have beendeveloped to measure small changes inoutput voltage and minimize the contributionof noise sources both on and off chip. Thelargest source of on-chip noise is the so-called reset or KTC noise. It is manifestedas an uncertainty in the floating diffusionvoltage after the reset FET has turned offand may be hundreds of microvolts inamplitude. It arises from the thermal noiseof the non-zero resistance of the resetF E T. After the reset FET is shut off, howev-e r, the floating diffusion voltage remains constant. Reset noise may be eliminatedby taking the difference between the output voltage level sampled after resetand again after the summing well hasdropped and transferred signal charge to the floating diffusion. This method ofsampling the voltage twice is known ascorrelated double sampling (CDS). All butthe highest speed CCD signal processingelectronics use this method.

There are two sources of noise in the output amplifier itself. First is the thermal(white) noise caused by the parallel resistance of the output FET and the loadresistor. Second is the 1/f or flicker noiseassociated with the surface states in the

Figure 13Typical CCD electronics.

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output FETgate region. Thermal noisecan be reduced by limiting the bandwidthand increasing the sampling time; however, at some low bandwidths, 1/fnoise will dominate the total noise.

CCD signal processing electronicsgenerally consist of a pre-amplifier, abandpass filter, a circuit that accomplishescorrelated double sampling, and an analogto digital converter (ADC). For practicalpurposes, the signal must be AC coupledat the CCD output, DC restored at somepoint, inverted, and amplified to match therange of the ADC.

There are many methods of implement-ing correlated double sampling dependingon the desired pixel rate. Two commonmethods discussed here are the dual slopeintegrator and the clamp/sample amplifier.

The dual slope integrator is a slowspeed (<500 kpixels/sec), low noiseapproach often used with 16 bit ADCs. As shown schematically in Figure 14, thecircuit involves an integrating amplifier and a means to invert the input signal.

At the beginning of the readoutsequence, the integrating capacitor isshorted to discharge it and remains shortedthrough the CCD reset period. When theoutput voltage has settled, the shortingswitch is opened and the inverted outputlevel (with no signal present) is integratedfor some time. As the summing well’scharge is transferred onto the floating diffusion, the input is switched to the non-inverted signal and integrated for thesame amount of time. Then the output signal is sampled by the ADC. This circuithas the advantage of providing high frequency filtering and gain; however, itsspeed is limited.

For higher speeds, the clamp/samplecircuit is often used. As shown schemati-cally in Figure 15, the circuit consists of astorage capacitor, a switch, and an inverting gain amplifier.

The clamp switch is closed at thebeginning of the readout sequence andremains closed through the CCD resetperiod. When the output voltage has settled, the switch is opened and the inputof the amplifier is allowed to change. Afterthe summing well has transferred itscharge onto the floating diffusion and thesignal has risen, the output may be sampled. An inverting gain amplifier isneeded to provide the gain and inversion

present in the dual slope integrator.The CCD output noise is on the order

of a few microvolts. Thus, the choice forpreamplifier is critical to obtain optimumnoise performance. To this end, it is important to select a preamplifier that ismatched to the bandwidth of the systemand has the lowest possible current andvoltage noise.

Gate Drivers

Gate drivers are essentially switchesbetween two voltage levels. Several characteristics are desirable. First, thelogic level input is usually ground referenced and needs to be isolated from gate voltage levels. The permissibleoutput transition rate is limited by the gatecapacitance and gate resistance. Toorapid a transition will adversely affect adjacent gates by reducing full well capacityon negative transitions or by driving thecharge into the Si-Si02 interface on positive transitions. The gate driversshould also have sufficiently low outputimpedance to sink the current that flowswhen adjacent gates are driven.

In summary, support electronics mustbe carefully designed to obtain the bestpossible performance from scientific-gradeCCDs.

Figure 14Dual slope integrator.

Figure 15Clamp/sample amplifier.

InputfromCCD

Invertingswitch Output

toADC

Dischargeswitch

+1

-1

InputfromCCD

Clamp

OutputtoADC

-G

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SITe Specifics

Scientific Imaging Technologies, Inc.(SITe) specializes in the research, design,and manufacture of charge-coupleddevices (CCDs) and imaging subassembliescontaining CCD components. SITe’s scientific-grade CCDs are used in applications for astronomy, aerospace,medical, military surveillance, spectroscopy,and other areas of imaging research.Commercial uses of SITe high performance CCDs include biomedicalimaging, manufacturing quality control,environmental monitoring, and nondestructive testing.

©1994 Scientific Imaging Technologies, Inc. All rights reserved. SITe products are covered byU.S. and foreign patents, issued and pending.Information in this publication supersedes that in allpreviously published material. Specifications andprice change privileges reserved. For further information, contact Scientific Imaging Technologies,Inc. P.O. Box 569, Beaverton, Oregon 97075-0569USA. Phone 503/644-0688. Fax: 503/644-0798.

S C I E N T I F I C I M A G I N G T E C H N O L O G I E S , I N C .

Scientific ImagingTechnologies, Inc.

P.O. Box 569Beaverton, OR 97075-0569503/644-0688503/644-0798 fax

With its focus on scientific-grade CCDimaging components and modules, SITeprovides standard designs, user definedcustom CCDs, and foundry services.SITe’s engineering and manufacturingteam builds custom CCD imagers for usein the most demanding applications,including NASA programs, satellite platforms, and other research projects.Devices are available as front illuminatedor thinned, back illuminated CCDs.

Innovation, process development, and design experience date back to thefounding of the group in 1974. For moreinformation about scientific-grade CCDs,please contact SITe’s customer servicedepartment.