Single Chip CMOS Direction Conversion Transceivers … · Title: C:Documents and SettingsOwnerMy DocumentsHot Chips PDF Presentations2_Monday_Conference2.prn.pdf Author: Owner Created

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© Copyr ight Sir if ic Wireless Corporat ion 2002 CONFI DENTI AL w w w .sir if ic.com

Single Chip CMOS Direction Conversion

Transceivers for WWAN and WLAN

Tajinder (Taj) [email protected]

© Copyr ight Sir i f ic Wireless Corporat ion 2002 CONFI DENTI AL w w w .sir if ic.com

Introduction

I. Market Requirements

II. Receiver Architectures

III. Sirific’s Virtual LOTM

IV. Transmitter Architectures

V. Sirific’s Transceiver Platform and Implementation

VI. Conclusion

2


Cellular Market Forecasts

Source: Deutsche Bank (Jan 2004)

0

50000

100000

150000

200000

250000

300000

2001 2002 2003 2004 2005 2006 2007 2008

Un

its

(in

th

ou

sa

nd

s)

GSM

GPRS

EDGE

WCDMA

CDMA

CDMA 1xRTT

CDMA 1xEV-DO/DV

Wireless Market Forecasts by Standard


Cellular Market Forecasts

GSM

6% GPRS

5%

EDGE

38%

WCDMA

24%

CDMA 1xRTT

7%

CDMA 1xEV-DO/DV

20%

y EDGE + WCDMA market will account for 62% of the overall worldwide wireless market

y GSM, GPRS, EDGE and WCDMA combined will dominate the cellular market share

2008 Wireless Market Forecast by Standard

3


WLAN Market Forecasts

WLAN Hotspot Locations

y Predominant increase in WLAN Hotspot locations as well as WLAN chipset units in the next few years

y Expected that 50% of units by 2006 will be multi -standard (802.11a/b/g)

Worldwide WLAN Chipset Units

y Cellular and WLAN market trends are driving for multi –standard, multi –band devices







VI. Conclusion

4

Receiver Architectures Implemented in CMOS

GSM

GPRS

EDGEEDGE

WCDMA

WLAN

Tra

dit

ion

al D

ire

ct

Co

nvers

ion

Sir

ific

’sV

irtu

al L

O™

Lo

w -

IF

y Until now, most receiver architectures have been limited either to narrow –band (GSM, GPRS, EDGE) or wide –band (WLAN, WCDMA), not both


Receiver Architecture – Direct Conversion / Zero-IF

y Advantagesy Highly integrated

y Platform for all bands and standards

y Disadvantagesy DC offsets

y 1/f Noise issues in CMOS

0

90

I

Q

0

90

I

Q

5


DC Offset Issues in Direct Conversion Radios

y DC offsets are common problem for direct conversion architecture s and result from 5 physical effects:

y RF leakage

y LO-RF leakage

y IIP2 (second order distortion) à Very bad for CMOS because of bad switching characteristics

y Thermal DC offset

y 1/f noise àLimiting factor for Direct Conversion CMOS


DC Offset Issues in Direct Conversion Radios

y In order for IIP2 to be a “stable ” measurement value, the following condition should hold:

(input referred second order harmonic) > (LO leakage level reference to the input)

IIP2 “unstable ”IM2 = -120 dBm

LO leakage = -66dBm

IIP2 “stable ”

IM2 = -60 dBm

LO leakage= -99dBm

6


1/f Noise in CMOS Circuits for Direct Conversion

frequency

x(t)

LO

x(t)

LO

input output

RF

output

1/f noise Reduces SNR

BW

input

y More important in CMOSy Limiting factor for GSM/GPRS/EDGE direct conversion CMOSy No “potential ” fixes in CMOS

y 1/f noise is more significant in CMOS technology

y 1/f noise arises at baseband due to the switching of transistors in the mixers (Darabi & Abidi, IEEE SSC, vol. 35, p 15, 2000)


LO Generation

y LO generation is the generation of signal(s ) to down convert the RF signal without corrupting the data

y Some contributors of DC offset can be combated with LO generation

No external filters as in superhetradios

LO

generation

I(t)*sin(ω t) I(t)

Has no

energy at ω Has no

energy at ω

No external filters as in superhetradios

LO

generation

I(t)*sin(ω t) I(t)

Has no

energy at ω Has no

energy at ωHas no

energy at ω

7




III. Sirific ’s Virtual LOTM



VI. Conclusion


)(tx

)(1

tφ )(2

tφ)()x(

)()x()x(21

ttx

tttx

effφφφ

=a)

)(teffφ

)(tx )()x( ttx effφ

)(1

tφ

)(2 tφ

)()()(21 ttt

eff φφφ ×=

b)

Virtual LO™ - Sirific’s Solution for LO Generation

Has several conditions

y Sirific ’s Virtual LO TM frequency planning technique eliminates the DC offset

8







VI. Conclusion

Summary of Transmitter Architectures

Tra

ns

lati

on

al

Lo

op

Po

lar

Lo

op

Dir

ec

t M

od

ula

tio

n

GSM

GPRS

EDGEEDGE

WCDMA

WLANy Direct modulation is the only

architecture that is not limited to any specific standard

9


Transmitter Architectures – Direct Modulation

00

90

I

Q

Σ

y Advantages

y Simple architecture

y Wide –band

y Single LO

y Disadvantages

y Limited gain control

y Difficult to meet noise, linearity, carrier feedthrough, and quadratureaccuracy (especially in GSM)


Direct Modulation vs. Polar Loop

+ supports other more complex

modulations (i.e. WCDMA)

+ no calibration or complex loops

- Higher noise output (may require TX filtering/switches –filters are about

<$0.20 in volume)

- Requires Linear PA

- Carrier feed -thru/sideband requires

consideration

? Lower PA efficiency (higher power)

+ Lower noise (no TX filtering)

+ Add on to past GSM solutions (i.e. translational loop)

- supports only some modulations

- Requires calibration or complex

loops that require power

- May require isolators (significant

size and >$1.00 in volume)

- May require PA controller chip

? Higher PA efficiency (lower power)

Direct Modulation Polar Loop

10


Polar Loop vs. Direct Modulation System PAE for EDGE

LDO

Pin

Amplitude Data

VDD

LDO Required only

for Polar Loop

Pout

System PAE < 20% including LDO) at

Pout = +28dBm for Polar Loop

y System PAE for a Polar Loop PA is limited by the LDO which is used for amplitude modulation

y No LDO is required for Direct Modulation, and so system PAE depends only on the linear PA

System PAE ~ 25% at Pout = +28dBm

for Direct Modulation

Pin

VDD

Pout






V. Sirific ’s Transceiver Platform and Implementation

VI. Conclusion

11

Transceiver Platform–GPRS/EDGE+802.11b/g

/ 2

or/ 4

Virtual LOTM

Loop Filter

DC

OC

DC

OC

DC

OCDCOC

Filter Tuning Control

DividerSigma-Delta

WLA

N

Baseband

Inte

rface

GSM

/GP

RS/E

DG

E

Baseband

Inte

rface

Clock Logic

(Dual Reference Clock Input)

Dual 3-Wire SerialInterface

Σ−45/+45

Un

i-D

ire

ctio

na

lOR

Bi-

Dir

ect

ion

al

Dif

fere

ntia

lA

nal

og

I/Q

Ba

seb

an

dIn

terf

ace

GSM

/GPR

S/E

DG

E

Tx

Input

GSM

/GP

RS/E

DG

E&

WLA

N

Rx

Out

put

WLA

N

Tx

Input

Sin

gle

Pole

Sw

itchable

Filte

r

and

Input

Mux

MU

X

PDCP / M

/2

or/ 4

Virtual LOTM

Loop Filter

DC

OC

DC

OC

DC

OCDCOC


DividerSigma-Delta

WLA

N

Baseband

Inte

rface

GSM

/GP

RS/E

DG

E

Baseband

Inte

rface

Clock Logic

(Dual Reference Clock Input)

Dual 3-Wire SerialInterface

Σ−45/+45

Un

i-D

ire

ctio

na

lOR

Bi-

Dir

ect

ion

al

Dif

fere

ntia

lA

nal

og

I/Q

Ba

seb

an

dIn

terf

ace

GSM

/GPR

S/E

DG

E

Tx

Input

GSM

/GP

RS/E

DG

E&

WLA

N

Rx

Out

put

WLA

N

Tx

Input

Sin

gle

Pole

Sw

itchable

Filte

r

and

Input

Mux

MU

X

PDCP / M


RX pathI and Qsignals

Phi2_1

Phi2_2

Phi2_N

Memory

Senseblocker

VLO generator

LO withinPLL loop

φ1 φ2

Compare

Powerdetector

Enable/disable

RF in

Signal tosense

blockerpresence

Timers

Virtual LO™ & Dynamic Spurious Control (DSC)

y Dynamic Spurious Control

(DSC) is used to boost radio

performance in the presence of a large out -of-band blocker

within a packet (i.e. for GSM)

y The interferer is sensed within

the high frequency path and I/Q path.

y With these two pieces of data φ2 is modified which automatically

modifies φ1.

12


Rx total chain measurements

41mW41mW41mWMixer Power

18mW18mW18mWLNA Power

-4dB4dB∆NF with -26dBm Blocker @ 3MHz

66dBm54dBm45dBmIIP2 (min)

80dB95dB95dBMaximum Gain Range

< 0.5dB< 0.5dB< 0.5dBIQ Amplitude Error

< 1°< 1°< 1°IQ Phase Error

-108dBm-103dBm-133dBmLO Re-radiation

3.5dB3.0dB2.8dBNoise Figure

WLAN1800/1900850/900Receiver


Gm-C Baseband Filter, VGA and DCOC

DC

OC

DC

OC


Fast and slow DCOC Fast and slow DCOC

13


Gm-C Capacitor Assignments

INPUT OUTPUT

REAL POLELOW-PASS

BIQUAD 1

LOW-PASS

BIQUAD 2+G

M

-GM

+G

M

-GM

-GM

+G

M

CS CB21 CB22


Gm-C Baseband Filter, VGA and DCOC

54mW20mW20mWBaseband Filter Power (Max Gain)

62dB @ 25MHz64dB @ 600kHz64dB @ 600kHzRejection

7.3MHz204kHz204kHz3dB Bandwidth

WLAN1800/1900850/900Baseband Filter

14


Tx Chain Measurements

4dBm8dBm8dBmMax output power

65mW77mW77mWPPA Power

65mW34mW34mWMixer Power

40dB41dB41dBGain Range

--149dBc/Hz-154dBc/HzPN@20MHz@max P

>35dB38dB38dBSideband Suppression

>40dB>40dB>40dBCarrier Suppression

WLAN1800/1900850/900Transmitter


EDGE Output spectrum from Tx

y EDGE modulationy Pout = 0dBm

y Passes EDGE mask

15


RF Synthesizer

÷Mf ref

fref /M

PFD CP

fast acquisition

÷N

f vco/N

÷2/÷4

Σ∆Serial

Interface

To Analog BasebandRF Input

Fast acquisition

4bit


Synthesizer Measured Performance

11mW11mWVCO Power

36mW36mWCP, Dividers, Loop Filter Power

-85dBc/Hz @ 100kHz-131dBc/Hz @ 3MHz

-90dBc/Hz @ 10kHz-140dBc/Hz @3MHz

Phase Noise (at mixer port)

-185µsSettling Time(to 100ppm)

200kHz or 1MHz200kHzResolution

4.5GHz to 5.0GHz3.4GHz to 3.9GHzVCO Frequency Range

WLANGSMSynthesizer

16


Die Photo & RF Reference Design

y Production chip is < 20mm2 y RF Reference Design

WCDMA and 802.11a Reserved Area







VI. Conclusion

17


Summary

y Multi –band, Multi -standard applications are a market requirementy Network operators and handset OEM/ODMs require low -cost high performance multi-mode

solutions

y The consumer demand for wireless data services is d riving the ED GE, WCDMA and WLAN markets

y CMOS solutions provide high integration and low cos ty Applying CMOS to narrow -band cellular standards presents many design challenges

y Direct Conversion is the receiver architecture of c hoice for mul ti-standard applicationsy Eliminating DC Offset is critical

y Direct Modulation is the transmitter architecture o f choice for multi -standard applicationsy Reducing Carrier Feedthrough and improving Quadrature Accuracy

y Sirific ’s Virtual LO ™and Dynamic Spurious Control are methods used to de sign a multi–band, multi – band direct conversion CMOS transceiver