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Since February. Clock Driver Needed Improvement. Original Version. ADC Clock outputs slow due to level shifter. Level Shifter. Buffer. Improved Version. V EE Routing Optimization. V EE ~ 5 mV. DELAY. GAIN BITS PIPELINE +OUTPUT. CLOCK I/O. V EED pad. COMMAND DECODER. - PowerPoint PPT Presentation
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P. Denes 06.02
Page 1FPPA2001_CLOCK
Since February
Since February
P. Denes 02.02
Page 13FPPA-Clock
New Clock DistributionNew Clock Distribution
Internal Clock Delay
ADC Clock buffer
ADC Clock Delay
Clock distribution Tree
Leveladapter
Clock Input
393ps 111ps 126ps285ps
511ps
126ps6.2ns
111ps
297ps111ps
t
S1 to Clock ADC delay adjustableFrom -1ns to 6ns
P. Denes 02.02
Page 13FPPA-Clock
New Clock DistributionNew Clock Distribution
Internal Clock Delay
ADC Clock buffer
ADC Clock Delay
Clock distribution Tree
Leveladapter
Clock Input
393ps 111ps 126ps285ps
511ps
126ps6.2ns
111ps
297ps111ps
t
S1 to Clock ADC delay adjustableFrom -1ns to 6ns
P. Denes 06.02
Page 2FPPA2001_CLOCK
Clock Driver Needed Improvement
Clock Driver Needed Improvement
P. Denes 02.02
Page 14FPPA-Clock
ADC Clock DelayADC Clock Delay
ADC Clock level converter
Buffer
Delay control current inputExternalresistor
Clamp voltages generators
Swing Offset
P. Denes 02.02
Page 14FPPA-Clock
ADC Clock DelayADC Clock Delay
ADC Clock level converter
Buffer
Delay control current inputExternalresistor
Clamp voltages generators
Swing Offset
P. Denes 06.02
Page 3FPPA2001_CLOCK
Original VersionOriginal Version
Level Shifter Buffer
ADC Clock outputs slowdue to level shifter
P. Denes 06.02
Page 4FPPA2001_CLOCK
Improved Version
Improved Version
P. Denes 06.02
Page 5FPPA2001_CLOCK
VEE Routing Optimization
VEE Routing Optimization
VEED
pad
GAIN BITSPIPELINE+OUTPUT
GAIN BITSPIPELINE+OUTPUT
DELAYDELAY
COMMAND DECODERCOMMAND DECODER
CLOCK I/OCLOCK I/O
VEE ~ 5 mV
P. Denes 06.02
Page 6FPPA2001_CLOCK
Digital Bias DistributionDigital Bias Distribution
II’
VEE VEE’
VBIAS~0
0
0.5
1
1.5
2
2.5
-0.020 0.000 0.020
VBE
I/I 0
P. Denes 06.02
Page 7FPPA2001_CLOCK
Timing
Timing
CKi
FixedDelay
VariableDelay
S/H(Internal clocks)
CKAD(to ADC)
Input clock (CKi) is the “observable”All subsequent timings relative to CKi
P. Denes 06.02
Page 8FPPA2001_CLOCK
T/H Timing
T/H Timing
CK H = 8.5 ns
CKi
S/H
FPUout
P. Denes 06.02
Page 9FPPA2001_CLOCK
Timing RelationsTiming
Relations
Signal
N
CKi
S/H
N+1 N+2 N+3 N+4
CKAD
S
H
ADC N-2 N-1 NN-3
N-2 N-1 NN-3FPUo
P. Denes 06.02
Page 10FPPA2001_CLOCK
FPU Output Bits
FPU Output Bits
P. Denes 06.02
Page 11FPPA2001_CLOCK
FPU Output Bit Timing
FPU Output Bit Timing
CK FPo = 14.2 ns S/H FPo = 5.7 ns
2.5 pipeline delays
P. Denes 06.02
Page 12FPPA2001_CLOCK
CKAD TimingCKAD
Timing
P. Denes 06.02
Page 13FPPA2001_CLOCK
Timing DiagramTiming
Diagram
Signal
CKi
S/H
CKAD
S
ADC
FPUo
H
N
N-2N-3
N-2N-3
8.5 ns
9 typ ns
14.2 ns
8.9 ns
