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Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs
Hao Yu, Joanna Ho and Lei HeElectrical Engineering Dept.
UCLA
Partially supported by NSF and UC-MICRO fund from IntelPartially supported by NSF and UC-MICRO fund from Intel
2New Solution for High-performance Integration
2D SoC has limited device density and interconnect performance (delay)
Potential solution: 3D Integration Fabrication Technologies: Chip-level Wafer Bonding or Die-level Silicon
Epitaxial Growth
Extra challenges: thermal integrity and power integrity
3Thermal Challenge in 3D ICs
Inter-layer dielectrics are poor thermal conductors the temperature of each die increases along third dimension, where
the heat sink is on the top
Vertical vias are good thermal conductors They can be used as thermal vias to remove the heat from each die
40c
70c
100c
130c
160c
High temperature affects interconnect and device reliability and brings variations to timing
4Power Delivery Challenge in 3D ICs
Vertical vias can minimize the returned current path and hence loop inductance
They can be used as power vias to reduce the voltage bounce for each P/G plane
The voltage bounce is significant in P/G planes at the bottom due to resonance
Large voltage bounce affects the performance of I/Os
5Via Planning Problem in 3D IC
Previous work (thermal via planning) Iterative via planning during placement [Goplen-Sapatnekar:ISPD’05] Alternating-direction via planning during routing [Zhang-Cong:ICCAD’05] Both use steady-state thermal analysis and ignore variant thermal power Both ignore that the vertical via can be also designed to remove the
voltage bounce in power supply
Motivation Staple vias from the top heat-sink to the bottom P/G planes
remove heat in silicon die and reduce voltage bounce in package plane Too many? -> signal routing congestion Too few? -> reliability by current density
Primary contributions of our work Formulate a levelized via stapling to simultaneously minimize both
temperature hotspot and voltage bounce Develop an efficient sensitivity-driven optimization with use of
structured and parameterized macromodel
6Outline
Modeling and Problem Formulation Integrity Analysis and Sensitivity based
Optimization Experimental Results Conclusions
7Electric and Thermal Duality
Temperature Voltage state variables (x(t))
Thermal-Power Input Current sources (u(t))
Thermal conductance Electrical conductance (G)
Thermal capacitance Electrical capacitance (C)
Both electric and thermal systems can be described in MNA (modified nodal analysis)
time domain: frequency domain:
( )( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
and are multi-input/output port matrices
i
T T
dx tGx t C Bu t G sC x s Bu s
dt
y t L x t y s L x s
B L
y
s the selected output response
8Two Distributed Networks for 3D IC
All device/dielectric layers and power planes are discretized into tiles
A distributed electrical RLC model for power/ground plane
A distributed thermal RC model for device/dielectric layer
Each via is modeled by a RC pair
9Thermal Model and Analysis
Steady-state thermal model and analysis Tiles connected by thermal resistance Heat sources modeled as time-invariant current sources Steady-state temperature can be obtained by directly solving a
time-invariant linear equation
Transient thermal model and analysis Tiles connected by thermal resistance and capacitance Heat sources modeled as time-variant current sources Transient temperature can be obtained by directly solving a time-
variant linear equation
10Need of Transient Thermal Modeling
Time-variant workload and dynamic power management introduce temporal and spatial thermal power variation Thermal power is the runtime average
of cycle-accurate power over thermal time-constant
Thermal power decides temperature
Pow
er
C P U C yc les
M axim u mthe rm a l-p o w er
C yc le -accu ra te p o w er
T ransien t the rm a l-p o w er
nsm s
s
Steady-state analysis needs to assume a maximum thermal power simultaneously for all regions But it rarely happens and hence can result in an over-design
Direct transient analysis is accurate but time-consuming It calls for more accurate yet efficient transient thermal modeling during the
design automation
11Need of Simultaneous Thermal/Power Co-Design
Temperature hotspots usually distribute differently from voltage bounce A thermal integrity map tends to result in a uniform via stapling
pattern A power integrity map tends to result in a biased via stapling
pattern in center
Considering thermal and power integrity separately may also lead to over-design
12Problem Formulation
It can be efficiently solved by a sensitivity based optmization The sensitivity is calculated from a structured and parameterized
macromodel
A levelized via stapling is used • Each level has a different via density Di
D0 D1 D2
Via Stapling
Minimize via number under thermal/power integrity constraint
Di levelized via density ni via number at different level Vmax power integrity constraint Tmax thermal integrity constraint Dmax congestion from signal via Dmin current density constraints
13Outline
Modeling and Problem Formulation Integrity Analysis and Sensitivity based
Optimization Experimental Results Conclusions
14Parameterized System Equation
The levelized stapling pattern is described by adjacent matrix X
1 2
34
5 6
78
1 2 3 4 5 6 7 8
1 2
3 4
5 6
7 8
1 -1
0
0
0 1
0
-1
0
0
X(2,6)=
Via conductance gi and capacitance ci are both proportional to the area Di or density (Di/a) (a is unit via area)
Both Di and Xi are parametrically added into the nominal MNA equation
iiii
T
K
iiii
XccXgg
sxLsy
sBusxscgDsCG
00
100
and where
),(),(
)(),()([
DD
D
15Separation of Nominal and Sensitivity
0
1 1 0
0
1 1 0
2 2 1 1 0
0
0 0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0
0 0 0
K Kap
K K
G
D g G
D g GG
D g G
D g D g G
D g G
( ) ( ),
has similar structure
Tap ap ap ap ap ap ap
ap
G sC x B u t y L x
C
Expanded system is reorganized into a lower-triangular-block system
1 1
1 1
( ... )1,..., 1( , ) ( )( ) ( )K Ki i i i
K Ki i
x s x s D D
D Expand state variables x(D1,…DK,s) by
Taylor expansion w.r.t. to Di [Li-Pileggi:ICCAD’05] Construct a new state variables by
nominal values and sensitivities (0) (1) (1) (1) (2)0 1 1,1 ,[ , ,..., , ,..., ]ap K K Kx x x x x x
Since system size is enlarged, we can reduce it by model reduction
16Macromodel by Model Reduction
large size
… … Small but
dense
small size
Model reduction can reduce model size and preserve accuracy by matching moments of inputs [Odabasioglu-Celik-Pileggi:TCAD’98] The projection above is non-structured, and will mess the
nominal values and their sensitivities again This can be solved by a structure-preserving reduction [Yu-
Tan-He:BMAS’05, Yu-Shi-He:DAC’06]
project
17Structured Projection (I)
Block-diagonally partition the flat projection matrix according to the size of nominal state-variable and sensitivity
2 2
0 0
1 1
1 1
K K
K K
K K
V V
V V
V V
V V
V V
Structured projection can result in a reduced system with preserved structure Nominal values and sensitivities are still separated after reduction There is only one LU-factorization of the reduced G0 in diagonal
~
0
~ ~
1 1 0
~ ~~
0
~ ~
1 1 0
~ ~ ~
2 2 1 1 0
~ ~
0
0 0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0
0 0 0
K Kap
K K
G
A g G
A g GG
A g G
A g A g G
A g G
~ ~ ~ ~ ~~(0) (1) (1) (1) (2)1 1 1,1 ,
~ ~
[ , ,..., , ,..., ]
has similar structure as
ap K K K
ap ap
x x x x x x
C G
18Time-domain Analysis
~ ~ ~ ~ ~ ~ ~
~~ ~
1 1( ) ( ) ( ) ( )
( ) ( )
ap ap ap ap ap ap ap
Tap apap
G C x t C x t h B u th h
y t L x t
Generated sensitivities can be used in any gradient based optimization
Nominal response and sensitivity can be solved separately and efficiently with BE in time-domain
We call this method as SP-MACRO
Direct sensitivity calculation
(1)
1 1 1
first-order: , e e e
s s s
t t tK K KT Tk
i k k ik k ki i it t t
yf xS dt L dt L x dt
A A A
19Sensitivity based Optimization
1iter iterD D S
Structured and parameterized reduction provides an efficient calculation of both nominal value and sensitivity The via density vector D can be efficiently updated during each iteration
Normalized sensitivity according to both temperature and voltage (T/V) sensitivities
Further speedup: adjoint Lagrangian method similar to [Visweswariah-Conn-Haring:TCAD’00]
Via optimization flow
Calculate T/V nominal+sensitivity
Check IntegrityConstraints
Update DensityVector
20Outline
Modeling and Problem Formulation Integrity Analysis and Sensitivity based
Optimization Experimental Results Conclusions
21Experiment Settings
Silicon Copper Dielectric
Sigma NA 59.6x 10^6S/m NAEpsilon NA NA 3.3
Mu NA NA 1.0Kapa_r 100W/mK 400W/mK 50W/mK
Kapa_c 1.75x10^6J/m^3K 3.55x10^6J/m^3K NA
A modest 3D stacking
layer size material number mesh
heat-sink 2cm x2cmx1mm copper 1 RC
device-layer 1cmx1cmx4um silicon 2 RC
inter-layer 1cmx1cmx1um dielectric 2 RC
P/G plane 2cmx2cm x10um copper 2 RLC
22Accuracy of Reduced Macromodel
Transient voltage responses of exact and MACRO models at ports 1 and 5 in one P/G plane with step-response input The responses of macromodels are visually identical to those exact models but
with >100 speedup
23Temperature/Voltage Reduction during OPT
The T/V are both decreased iteratively The allocated via results in a design meeting the
targeted temperature 52C and the voltage bounce 0.2V
24Steady-state vs. Transient
Transient thermal analysis reduces via by 11.5% on average compared to using steady thermal analysis
Our SP-Macro results in an efficient transient analysis that reduces runtime by 155X compared to the direct steady-state analysis
Total tile#
Level
vector
Steady-state Tran by SP-MACRO
Solve
dc (s)
Total
via
Redu
Ckt(s)
Solve
BE(s)
Total
via
Saving
ratio
620 0,1 4.06 176877 0.01 0.12 156154 11%
2140 0,1,2 26.37 187422 0.13 0.17 166971 11%
7900 0,1,2,3 167.9 235484 1.22 0.86 206482 12%
27740 0,1,2,3,4 1243.7 239379 5.12 1.07 21184 12%
55680 0,1,2,3,4,5 NA NA 15.87 3.65 216732 NA
25Sequential vs. Simultaneous
Total tile# Seq. Sim.
620 176877 118020 -32%2140 187422 127651 -32%7900 235484 140433 -36%
27740 239379 143718 -37%55680 NA 144998 NA
Simultaneous optimization reduces via by 34% on average compared to the sequential optimization
Opt-method
Level0 1 2 3 4
P/G-only 76832 3410 1901 876 /Thermal-
only/ 1157 43567 4007 79432
Sim. 67058 811 2500 2808 70541
Comparisons of via distribution at different levels for ckt (27740)
26Conclusions
Vertical vias play a critical role in 3D IC design A simultaneous thermal and power integrity driven via
planning It saves via number by 34% on average compared to a sequential
design
A structured and parameterized macromodel can be efficiently employed during the design optimization
This method can be further extended 3D signal and P/G routing Performance driven 3D design