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Simulation and design of a germanium L-shaped impact-ionization MOS transistor

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2008 Semicond. Sci. Technol. 23 015012

(http://iopscience.iop.org/0268-1242/23/1/015012)

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IOP PUBLISHING SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Semicond. Sci. Technol. 23 (2008) 015012 (6pp) doi:10.1088/0268-1242/23/1/015012

Simulation and design of a germaniumL-shaped impact-ionization MOStransistorEng-Huat Toh, Grace Huiqi Wang, Lap Chan, Ganesh Samudraand Yee-Chia Yeo

Silicon Nano Device Laboratory (SNDL), Department of Electrical and Computer Engineering,National University of Singapore (NUS), 10 Kent Ridge Crescent, S119260, Singapore

E-mail: eleyeoyc@nus.edu.sg

Received 10 August 2007, in final form 3 November 2007Published 12 December 2007Online at stacks.iop.org/SST/23/015012

AbstractThis paper reports a novel L-shaped impact-ionization MOS (LI-MOS) transistor structure thatachieves a subthreshold swing of well below 60 mV/decade at room temperature and operatesat a low supply voltage. The device features an L-shaped or an elevated impact-ionizationregion (I-region), which displaces the hot carrier activity away from the gate dielectric regionto improve hot carrier reliability and VT stability problems. Germanium, which has a lowerbandgap and impact-ionization threshold energy lower than silicon, is chosen as the materialof choice for the LI-MOS transistor structure. Device physics and design principles for theLI-MOS transistor are detailed through extensive two-dimensional device simulations. TheLI-MOS transistor exhibits excellent scalability, making it suitable for augmenting theperformance of standard CMOS transistors in future technology generations.

1. Introduction

CMOS device scaling has continued for decades, and as theminimum feature size scales below 20 nm, the conventionaltransistor structure faces formidable challenges in terms ofmaintaining good electrostatic control of the channel potentialand suppression of short channel effects [1–4]. Severedrain induced barrier lowering (DIBL) and band-to-bandtunneling (BTBT) have led to high off-state leakage currentIoff. Moreover, continuous reduction of threshold voltage VT

with device scaling results in higher subthreshold leakagecurrent and static power consumption. The crux of the powerconsumption issue lies in one of the fundamental limitationsfaced, i.e. the non-scalability of the subthreshold swing S. Fora conventional CMOS device, S is dependent on the Fermi–Dirac distribution of carriers’ energy and is limited by kT/q,where k is Boltzmann’s constant, T is the absolute temperatureand q is the electronic charge. At room temperature, S is atbest 60 mV/decade. This is further degraded with aggressivedevice scaling which has resulted in an increase of channeldoping to alleviate the short channel effects [4].

To realize S of less than 60 mV/decade at roomtemperature, a device structure that modulates the breakdown

voltage of a gated p–i–n structure to switch between the offand on states would be useful. This gated p–i–n diode iscommonly known as the impact-ionization MOS (I-MOS)transistor [5–7]. As the I-MOS device based on Si requiresa high breakdown voltage to sustain impact ionization, betterI-MOS device performance can be achieved based on Ge dueto its smaller band gap EG. The I-MOS device has an un-gated impact-ionization region (I-region) where multiplicationof carriers occurs. The I-MOS device exploits the avalancheeffect of impact ionization to realize a steep increase of currentfrom the off state to the on state. With a longer effectivechannel length (which includes the I-region) in the off state,the I-MOS transistor exhibits better control of short channeleffects than the conventional CMOS transistor. Lower Ioff

could be achieved while maintaining a high on-state currentIon. In an attempt to relocate the impact ionization activityaway from the gate dielectric region to reduce VT instabilityand hot-carrier issues, a form of the I-MOS device whichemploys an L-shaped I-region was demonstrated [7]. Aselective epitaxial growth (SEG) which forms the elevatedI-region allows accurate dopant profile engineering and easycontrollability and scalability of the I-region dimensions. Inaddition, the LI-MOS device has a compact self-aligned

0268-1242/08/015012+06$30.00 1 © 2008 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 23 (2008) 015012 E-H Toh et al

Figure 1. Schematic of an n-channel L-shaped impact-ionizationMOS (LI-MOS) transistor, or an I-MOS transistor with an elevatedimpact-ionization region (I-region), showing the equivalentresistances and dimensions in the I-region. The total length of theI-region comprises a vertical I-region of length TI and a horizontalI-region of length LS, with resistances of RV and RH, respectively.For an n-channel device, the source is doped p+ while the drain isdoped n+.

device structure to improve the packing density and is alsoCMOS-process compatible. However, optimization of deviceperformance for the LI-MOS transistor through tuning ofdevice structural and material parameters has never beeninvestigated before. In addition, the scalability of the I-MOS transistor for future technology generations has not beenstudied and benchmarked with conventional CMOS transistorperformance or to the requirements of the InternationalTechnology Roadmap for Semiconductors (ITRS). In thispaper, we report insights into the device physics and key devicedesign principles of the germanium LI-MOS transistor, andexplore its scalability for future technology generations.

2. Device structures and physics

The LI-MOS transistor has an L-shaped I-region comprisingan elevated I-region with thickness TI and resistance RV, and ahorizontal I-region with length LS and resistance RH (figure 1).The L-shaped I-region has a total length LI = TI + LS. For ann-channel LI-MOS, the drain is doped n-type and the sourceis p-type doped. The horizontal portion of the I-region hasa p-type doping concentration NB and the elevated I-regionhas a doping concentration of 1 × 1013 cm−3. The dopingconcentrations in the n+ drain and p+ source are 2 × 1020 cm−3.The buried oxide (BOX) and channel film thicknesses are1400 A and 400 A, respectively.

Synopsys TCAD tools [8] were used to study the devicephysics and design principles. While experimental Ge I-MOStransistors are not available for calibration of the simulation,the model used in this work is the same as that in [9], whichshows a good match between simulated and experimental Gep–i–n diodes. Self-consistent impact-ionization model [10]and band-to-band tunneling model [11] were used with otheressential models to accurately simulate sub-100 nm gate lengthdevices at 300 K. The generation rate of electron–hole pairsby impact ionization for an I-MOS transistor is given byGII = αn · |−→Jn |/q + αp · |−→Jp |/q, where αn and αp are theelectron and hole impact-ionization coefficients, respectively,

(a) (b)

Figure 2. Energy band diagrams illustrating the (a) off-state and(b) on-state operations of an n-channel I-MOS transistor. Theoff-state current consists of a drift of the minority carriers in areverse-biased p–i–n diode. For the on state, the gate needs toinduce a sufficient electric field in the I-region for impact-ionizationto occur. The avalanche effect creates a huge on-state current to flowfrom the source to the drain.

and−→Jn and

−→Jp are the electron and hole current densities,

respectively. The impact-ionization coefficients could bemodeled by an effective driving field model,

αn = α∞n (T ) exp

[−

(Fcrit,n

Fn

)EXN.II]

, (1)

αp = α∞p (T ) exp

[−

(Fcrit,p

Fp

)EXP.II]

, (2)

where Fn and Fp are the effective driving fields for electronsand holes, respectively. The critical electric fields used in(1) and (2) are expressed as Fcrit,n = EG(T )/qλn(T ) andFcrit,p = EG(T )/qλp(T ), where λ is the optical-phonon meanfree path. The local field models are reasonably sufficientto predict the breakdown characteristics in an ultra-smallI-region where carriers are less likely to suffer from optical-phonon scattering. Thus, electrons are easier to reach theirimpact-ionization threshold energy, resulting in a velocityovershoot effect which tends to cancel the non-local deadspace effect. Experimentally, the breakdown characteristicsare reasonably predicted using the local field models [9]. Webelieve that these models should be sufficiently accurate inour case as the dimensions are above 5 nm threshold belowwhich more profound thickness-dependent quantum effectsand interactions manifest.

The energy band diagrams of the n-channel transistoroperating in the off and on states are shown in figure 2. Inthe off state, the source is at a negative bias and the drain isat a positive bias. Hence, the off-state current is due to thedrift of the minority carriers, similar to that of a reverse-biasedp–i–n diode, and is extremely low. In the on state, the gateinduces sufficient band bending in the I-region to cause impactionization. This leads to a large on current that flows betweenthe source and the drain. Figure 3 depicts the concentrationcontours of holes generated by impact ionization in an LI-MOStransistor. Most of the hot carriers generated are confined tothe vertical and horizontal I-regions. Negligible hot carriers

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Semicond. Sci. Technol. 23 (2008) 015012 E-H Toh et al

Figure 3. Plot of the concentration contours of holes generated byimpact ionization in an LI-MOS device. The majority of the holesgenerated are confined to the I-region (gray).

are found beneath the gate dielectric. By altering the resistancevalues of RV and RH (i.e. NB, TI and LS), hot carrier reliabilitycould be improved by displacing the impact ionization activityaway from the gate dielectric region. For instance, increasingNB causes a more voltage drop across RV and increases theelectric field in the elevated I-region. As a result, the hotcarrier activity is reduced in the horizontal I-region, and mostof the hot carriers are confined in the elevated I-region.

3. Materials engineering

As the switching mechanism of the I-MOS depends on impactionization, the choice of material in the I-region plays animportant role in determining the I-MOS device performance.The material used for the I-region determines not only thebreakdown voltage at which impact ionization occurs, but alsothe off-state and on-state currents. One of the fundamentallimitations of an I-MOS device employing a Si I-region is thehigh breakdown voltage needed to sustain impact ionization.This is due to a low impact-ionization coefficient for electronsand holes in Si. Figure 4 depicts the electrons’ and holes’impact-ionization coefficients as a function of the inverse ofthe electric field for Si and Ge. Due to the lower bandgapof Ge compared to Si, Ge has impact-ionization coefficientsthat are 1–2 orders of magnitude higher than those of Si (seeequations (1) and (2)). Therefore, the use of Ge instead ofSi in the I-region of an I-MOS device would be preferred forachieving superior performance.

In this simulation, the LI-MOS device is formed on agermanium-on-insulator (GOI) substrate [12] to exploit thehigh impact ionization coefficient of Ge. Due to the lowerbandgap of Ge, electrons could easily acquire its impact-ionization threshold energy and create electron–hole pairs.Hence, the breakdown voltage of Ge is much lower than thatof Si. A reduction of up to 80% in the breakdown voltagecould be achieved. Figure 5 depicts the simulated gate transfercharacteristics for Si and Ge LI-MOS. We found that theID–VG characteristics are essentially the same when theI-region doping concentration is varied from 1 × 1013 cm−3 to

Figure 4. Variation of the impact-ionization coefficient αn and αp

as a function of the inverse of the electric field for Si and Ge,respectively. A higher impact-ionization coefficient is favorable forthe LI-MOS device operation. The impact-ionization coefficient ofGe is at least 1–2 orders of magnitude higher than that of Si.

Figure 5. A simulated ID–VG plot of Si and Ge n-channel LI-MOStransistors with a source bias VS of −5.25V and −1.8V respectively.The drain is grounded. An excellent subthreshold swing ofsub-5 mV/decade is achieved for both devices. The Ge LI-MOS hasa much superior Ion/Ioff ratio than Si LI-MOS due to the lowerbandgap of Ge.

1 × 1014 cm−3 or when the drain doping is varied from 5 ×1019 cm−3 to 2 × 1020 cm−3. Excellent subthreshold swings ofbelow 5 mV/decade are achieved for both Si and Ge LI-MOS.The threshold voltage VT is tuned to the same value of 0.1 Vfor both Si and Ge LI-MOS using different source voltages VS.A much lower VS is used for Ge LI-MOS due to the fact thatit has a larger carrier multiplication effect than Si LI-MOS.Thus, Ge LI-MOS could switch sharply from a lower Ioff toa much higher Ion at the same VT. Hence, the benefits of Gecome not only from the lower breakdown voltage, but alsofrom much lower Ioff and higher Ion (figure 5). Thus, Ge is amore appropriate material of choice than Si as the I-region forI-MOS.

We would like to point out that the Ge LI-MOStransistor may be fabricated on GOI substrates using

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Semicond. Sci. Technol. 23 (2008) 015012 E-H Toh et al

Figure 6. The summary of a generic CMOS-compatible processflow for Ge LI-MOS. Two different process flows (A and B) areillustrated, showing two different methods of forming theI-region/source. In process flow A, the I-region is defined by thesource ion implantation, the selective epitaxy thickness of Ge andthe RTA process thermal budget. For better controllability of thedimension of the I-region, process flow B is preferred whereby thevertical I-region is defined by the SEG of Ge with the source beingin situ doped.

process flows illustrated in figure 6. After active areadefinition, channel implant, gate stack and spacer formation,selective epitaxial growth (SEG) of undoped Ge could beused to form the elevated I-region or raised source/drain(S/D). Asymmetrically doped drain/source regions could beseparately formed by ion implantation (flow A). Alternatively,the drain is first implanted and activated, followed by SEG ofan in situ doped source (flow B). Dopant activation, contactand metallization would then be performed. Process flow Ballows for a more accurate control of the I-region dimension, aparameter that the I-MOS characteristics are heavily dependenton.

4. Device design and optimization

In order to explore the performance limits of Ge LI-MOS,device design and optimization are studied using a devicesimulator [8]. This allows us to design and fine tune theelectrical characteristics of the device to suit various logicapplications. Figure 7 shows the ID–VG characteristics of twoI-MOS transistors with NB of 1 × 1013 cm−3 and 5 × 1017 cm−3,illustrating the dependence of ID–VG on NB. An excellentsubthreshold swing of ∼1 mV/decade is obtained for Gen-channel LI-MOS transistors with a 35 nm gate length LG anda I-region length LI of 35 nm. The equivalent oxide thickness(EOT) simulated is 1 nm and the doping concentrations inthe n+ drain and p+ source are 2 × 1020 cm−3 with a lateralabruptness of ∼2 nm/decade. A low source voltage of −1.0 Vis employed. In a conventional MOS transistor, increasingNB increases VT as a higher gate voltage is needed to invertthe higher doped channel. In contrast, VT of the LI-MOStransistor decreases with increasing NB, as illustrated infigure 8. The depletion width and RH depend inversely onNB, and thus increasing NB reduces RH. This leads to a greatervoltage drop across the elevated I-region, therefore leading toa higher electric field, increased impact ionization and reduced

Figure 7. Simulated ID–VG plot of Ge n-channel LI-MOS transistorswith two different substrate doping concentrations NB, showing a1 mV/decade transition between the off and on states. The voltageapplied to the p+ source, VS, is −1 V. Increasing NB causes VT todrop.

Figure 8. Plot of the threshold voltage VT versus substrate dopingconcentration NB for various lengths LS, keeping TI fixed at 15 nm.The L-shaped I-region has a total length LI = TI + LS. A longer LS

causes VT to drop faster as NB increases.

VT. Moreover, the longer the horizontal I-region LS, the impactof NB on VT is greater. VT starts to drop at a lower NB whenthe ratio of LS/TI is much greater than 1. In addition, Ioff isfound to be lower in devices with lower VT (higher NB) thanin devices with higher VT (lower NB), as is seen in figure 9.This is explained by an inverse proportionality of Ioff to NB fora p–i–n diode [13]. The higher the doping, the lower is thereverse-bias leakage current. Since the variation of Ion withNB is small, the Ion/Ioff ratio increases with NB. The approachtoward device optimization for the L-shaped I-MOS deviceis different from that for a lateral I-MOS device. Unlike thelateral I-MOS [5] where changing the substrate doping NB

affects the whole I-region directly, the intrinsic region couldbe maintained in the elevated I-region while optimizing NB forbetter breakdown characteristics in the LI-MOS.

Figure 10 shows that VT increases with increasing TI,for various LS values. An effective way to control VT is

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Semicond. Sci. Technol. 23 (2008) 015012 E-H Toh et al

Figure 9. Plot of Ioff and Ion/Ioff ratios as a function of substratedoping concentrations NB. Ioff decreases as NB increases. This alsocauses the Ion/Ioff ratio to increase.

Figure 10. Threshold voltage VT generally increases with increasingTI. LS and TI are two adjustable parameters that allow for theflexibility of VT tuning.

through control of the thickness of the elevated I-region TI

by SEG. The use of SEG automatically miniaturizes the LI-MOS as there is no area penalty for including the elevatedI-region. LS may also be employed to tune VT over a widerange if needed. However, Ioff increases rapidly as LI becomescomparable to LG (figure 11). This results in a much lowerIon/Ioff ratio. Nevertheless, higher NB allows simultaneousrealization of lower VT and lower Ioff, enabling device operationat lower VDD and yet outperform the Ioff–Ion specifications inthe International Technology Roadmap for Semiconductors(ITRS-2006) [2].

5. Device scalability

I-MOS transistors may be designed to achieve low static power(LSP) or low dynamic power (LDP) while maintaining highperformance. For LSP design, the static leakage current,i.e. Ioff, needs to be as low as possible, whereas for LDPdesign, it is the power supply voltage VDD that needs to below. To illustrate the scalability of the Ge LI-MOS transistor,

Figure 11. Plot of Ioff and Ion/Ioff ratios as a function of the I-regionlength LI. Ioff increases rapidly as LI becomes comparable to LG.This also causes the Ion/Ioff ratio to decrease.

Figure 12. A comparison of VT as a function of the device gatelength for high-performance (HP) logic [2], I-MOS low static power(I-LSP) and I-MOS low dynamic power (I-LDP) technologies. VDD

values are the same for the HP and I-LSP technologies, and areindicated above the open squares. The corresponding VDD values forthe I-LDP technologies are indicated below each open triangle. Thelow VDD achievable in LDP I-MOS devices translates to a muchreduced dynamic power as compared to CMOS.

device simulations were carried out for I-MOS devices withgate lengths that match those projected in future technologygenerations [2]. For example, an I-MOS device with transistorparameters (includes gate length, gate dielectric thickness,doping profile abruptness) that are identical to those of a 32 nmhigh-performance (HP) logic technology node is labeled eitheras a 32 nm low static power LI-MOS technology (denoted byI-LSP) or as a 32 nm low dynamic power LI-MOS technology(denoted by I-LDP). The doping concentrations in the n+ drainand p+ source are fixed at 2 × 1020 cm−3 for the varioustechnology generations. For the I-LSP technology, the sameVDD as the corresponding HP logic is used, e.g. I-LSP32employs VDD = 0.9 V. A lower VDD (e.g. I-LDP employsVDD = 0.5 V) is used for the I-LDP technology (indicated nextto the data points in figure 12) than the corresponding HP orI-LSP technologies. Figure 12 summarizes the VT and VDD

trends for the LI-MOS devices. VT of LI-MOS technologies

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Semicond. Sci. Technol. 23 (2008) 015012 E-H Toh et al

Figure 13. Ge I-MOS technologies shows superior Ioff and Ion

characteristics as compared with projected Ioff and Ion targets forhigh-performance (HP) CMOS technology [2]. A low static powerLI-MOS (denoted by I-LSP) employs the same VDD and transistorstructure parameters, e.g. LG, as the corresponding HP logictechnology. For example, I-LSP32 employs VDD = 0.9 V and LG =18 nm. The low dynamic power LI-MOS (denoted by I-LDP)employs the same device structure parameters, but a lower VDD thanthat of the corresponding HP logic technology.

could generally be lower than that of HP technologies as thesubthreshold swing of LI-MOS devices is much smaller than60 mV/decade. An excellent subthreshold swing of sub-5mV/decade is achieved across all LI-MOS technologies. Thisallows VT of LI-MOS to be lowered more aggressively withoutresulting in a large Ioff. Due to the lower VDD employed forI-LDP technologies, VT of LI-MOS (I-LDP) is slightly lowerthan that of I-LSP technologies in order to sustain a high Ion.

For each device in the I-LSP or I-LDP technology, theparameters TI and LS were varied to optimize the deviceperformance. NB is kept constant at 1016 cm−3. Figure 13shows that I-LSP transistors demonstrate superb performance(lower Ioff and higher Ion) that exceeds the ITRS-2006projections. Due to the longer effective gate length andthe reverse-biased p–i–n diode, Ioff of I-LDP technologies ismuch lower than that required by HP technologies by at leasttwo orders of magnitude. With longer LI and higher VDD ascompared to I-LDP technologies, Ion of I-LSP technologiesis approximately three times higher than that required for HPtechnologies. This allows for the simultaneous achievementof both high performance and low static power consumptiondesign. I-MOS for LDP applications, i.e. I-LDP technology,may employ aggressively reduced VDD (figure 12) by LI tuningwhile satisfying the Ion specifications in ITRS-2006 [2] andhence have much reduced dynamic power. With reduced VDD,LI is aggressively reduced to sustain a high enough Ion tosatisfy the Ion specifications in ITRS-2006 [2]. However, dueto the lower VDD being employed, Ion of I-LDP technologiesare much lower than that of I-LSP technologies. Nevertheless,it is still much higher than the Ion specifications in [2]. Lowdynamic power consumption is achieved while maintaininghigh performance. In short, I-LSP technology may be chosen

when Pstatic is crucial while I-LDP technology may be chosenwhen the dynamic power consumption is critical. In terms ofcircuit design, such a technology allows flexibility for differentsystem requirements. However, it is noted that I-MOS couldnot operate rail to rail and an innovative circuit design isrequired. Further research on circuit design issues is beingcarried out and will be addressed in the future.

6. Conclusion

The Ge LI-MOS, or Ge I-MOS with an elevated impact-ionization region, is a CMOS-process-compatible technologythat is promising for augmenting the performance ofconventional CMOS transistors. Its L-shaped impact-ionization structure allows the diversion of hot carrier activityaway from the gate dielectric region, a critical improvementover the existing I-MOS structures. The Ge LI-MOS devicehas excellent scalability in future technology nodes, enablingvery significant reduction of power consumption in high-performance logic applications.

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