Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 4, APRIL 1979 501

Simple Analytical Models for the Temperature Dependent

Threshold Behavior of Depletion-Mode

Devices

Ahtruct-Threshold voltage shifts in ion-implanted depletion-mode MOSFET’s {depart substantially from the usual dose proportional shift of enhancement-mode devices. Analytic expressions for the relation- ship between threshold voltage shift and implanted donor dose and position are extended to include impurity freezeout at low temperatures, and a simple model for the observed low substrate sensitivity at low temperature is presented. Criteria to avoid parasitic subthreshold conduction in depletion-mode devices are also established using the threshold shift formulation,

NOTATION Gate oxide capacitance. A,ctive portion of implanted dose. I~nplanted dose in silicon. E,lectron energy. B’ottom of conduction band. Donor energy. Fermi energy. Energy gap. Intrinsic energy. Maximum electric field. Top of valence band. Permittivity of silicon. B;oltzmann’s constant. Acceptor density. E:ffective density of states in conduction band. Total electron concentration in channel. Donor density. Ionized donor density. Equilibrium ionized donor density. Implanted impurity density. Oxide charge density. Peak electron concentration in channel. Intrinsic concentration. Peak electron concentration in channel at threshold. Blulk potential.

Manuscript received August 17, 1978; revised November 11, 1978. R. C. Jaeger is with IBM General Systems Division, Boca Raton, FL

F. H. Gaensslen is with IBM Thomas J . Watson Research Center, 33432.

Yorktown Heights, NY 10598.

Maximum potential. Metal-oxide barrier. Surface potential. Silicon-oxide barrier. Total potential between Gmax and bulk at threshold. Elementary charge. Depleted charge. Absolute temperature. Gate oxide thickness. Flatband voltage. Gate voltage. Voltage across oxide. Substrate voltage. Threshold voltage. Depletion layer depth. Threshold depletion layer depth for uniformly doped

Implantation depth. Depth of peak potential.

device.

L I. INTRODUCTION

OW TEMPERATURE operation has been proposed as an attractive alternative for obtaining the power, re-

liability, and speed necessary for high performance operation of MOSFET’s at VLSI densities [ 1 ] and the characterization and design of very small enhancement-mode MOSFET’s for low temperature operation has been discussed in detail [ 2 ] . It is well known that the use of depletion-mode devices can offer both performance and density advantages in logic circuits, and considerable attention has been given to the depletion mode I-V characteristics in both the saturation and subthreshold regions of operation [3] - [6]. Discussions of the threshold behavior of enhancement- and (depletion-mode devices for normal operating temperatures have been pub- lished [7] - [ 151. However, recent experimental results and computer simulations have shown that impurity freezeout causes the threshold behavior of depletion-mode devices to be substantially different from that of enhancement-mode devices at low temperature [16], [ 171. This paper develops simple analytical models which accurately describe the thresh-

0018-9383/79/0400-0501$00.75 0 1979 IEEE

502 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 4, APRIL 1919

old behavior of depletion-mode devices over the temperature range 77-296 K.

The threshold voltage shift induced by the ion implantation used to tailor the threshold voltage may be split into two terms: the change in voltage across the oxide and the shift in surface potential. In the enhancement-mode cast:, the implantation does not substantially alter the surface potential at threshold, and over a wide range the threshold v,dtage shift is proportional to the implanted dose. For the depletion- mode device, however, threshold is reached with a turied channel and under varied surface potential conditions. b:odels based only upon implanted dose are insufficient to predict the threshold voltage shift for these depletion-mode devices.

We first extend the analytical expressions for the threuhold- voltage shift of depletion-mode devices at room tempei,ature [ 1 1 ] , [ 121 to include the effects of substrate bias and more equitably model the device threshold condition. The:le expressions are based upon step approximations of th: implanted impurity profile and demonstrate the differences between the enhancement- and depletion-mode devices. Excellent agreement between calculations and measured device characteristics is obtained over a wide substrate voltage range at room temperature.

The work is then expanded to model the effects of impurity freezeout at low temperatures. The calculated threshold voltages are again in good agreement with measured device thresholds from 296 to 77 K including variation with substrate bias. A simple model is presented for the low substrate sensitivity which is observed in depletion-mode devices at low temperature.

Criteria to avoid parasitic subthreshold conducticn in depletion-mode devices are also established using the threshold shift formulation.

11. EXPERIMENTAL DEVICE STRUCTURE AND DEFINITIONS

The n-channel devices used in this study were bui..t on 5 S2 * cm (100) p-type substrates using a self-aligned polysilicon gate process. The gate oxide thickness was 250 8, and the source and drain junction depths were 0.4 pm. A P31 phosphorous implantation at an energy of 30 keV with a total dose of 1.3E12 atoms/cm2 was used to form the n-channel depletion-mode devices. The characteristics of these devices were compared with those of control devices which did not receive a channel implantation. Depletion- mode devices with an additional boron channel implan.: can be treated by superposition using the same step appro,,’ .rima- tion described in [7 ]. Only electrically long and wide devices were characterized as we were initially interested in under- standing the geometry independent threshold behavicr of these devices.

The experimental threshold voltages were determined from plots of the device turn-on characteristics in the linear rcgion with a drain-to-source voltage of 0.1 V. The tangent to the linear region of the turn-on characteristic was extended to intercept the V, axis, and this voltage was reduced by 0.05 V to obtain the threshold voltage. The measurements were

performed either with the test device immersed in liquid nitrogen (77 K) or placed in a variable temperature test chamber.

Numeric simulations of the threshold voltage use a threshold definition based upon the total electron concentration in the channel. The nonimplanted device and the depletion- mode device then have equal levels of conductivity at threshold excluding mobility variations. A value of lElO electrons/ cm2 was chosen as the threshold condition [ 161, [ 171. Over the normal range of substrate doping concentrations, this value represents a good compromise especially since the threshold voltage changes very little with varying carrier concentration.

The analytical formulation to be discussed requires the peak potential in the channel at threshold to be equal to the negative of the bulk potential. This condition is similar to the usual threshold definition in an enhancement-mode device in which the surface potential at threshold is equal to the negative of the bulk potential. In the depletion-mode device this definition results in a channel concentration somewhat higher than lElO electrons/cm2 . However, the reduction in peak potential required to compensate for this error is on the order of kT/q and this difference will be neglected in the calculations. On the other hand, our threshold definition is substantially different from that of [ 1 I ] , [ 121 which allows the peak electron concentration in the channel to equal the net impurity density. This latter definition can result in channel concentrations which are substantially too high with an error in calculated depletion-mode threshold exceeding 0.1 v.

Finally, the definition of flatband used in this paper is described by Troutman [8] in which the semiconductor material is in a charge neutral condition. Under this condition the Si/Si02 interface is field free.

111. THRESHOLD SHIFT FORMULATION Energy band diagrams for enhancement- and depletion-

mode devices at threshold are compared with that of a nonimplanted device in Fig. 1. The surface potential required to reach threshold in the enhancement-mode device is essen- tially the same as that of the nonimplanted device. However, the surface potential at threshold in the depletion-mode device is substantially altered by the depletion implantation. The additional surface potential shift leads to a more complex dependence of the depletion-mode threshold voltage on the implantation characteristics than for the enhancement device.

The threshold voltage may be expressed in terms of surface potential and oxide voltage by referring to Fig. 2 . The threshold voltage changes in the presence of an implant, and this shift can be written as

AVT=AV,, f A@s.

In both the enhancement and depletion cases, AVO, is given by

JAEGER AND GAENSSLEN: THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICES 503

IMPURITY PROFILES ENERGY BAND DIAGRAMS

- 1.0-

x [ X I

TEMPERATURE T = 296K

Fig. 1. Impurity profiles and simulated energy band diagrams at threshold for a nonimplanted, n-channel device (center), a boron implanted enhancement-mode device (top), and a phosphorous implanted depletion-mode device (bottom).

-

THRESHOLD DEFINITION

VT ( + M O - +so + E, 1 2 k T ) + Vox + 4 s Fig. 2. Schematic energy band diagram around silicon dioxide/silicon

interface for definition of threshold voltage VT.

If the implant depth is less than the depletion depth X,

IAvOx I = - [D, - NA lAx,l] 4

cox

where D,, represents the implanted dose in silicon, and AX, is the change of the depletion layer width caused by the implantation. The depletion depth shrinks in the case of an enhancement-mode implantation and expands in the case of a depletion-mode implantation. In both cases, this results in a reduction of the effectiveness of the implanted dose in shifting the threshold.

In the enhancement-mode case, as shown in Fig. 1, A& = 0 and the oxide voltage term is dominant. For the depletion- mode case, however, A$, may become a significant 'fraction of the oxide voltage term. The effects of the surface potential term may be seen in Fig. 3 in which the magnitude of the threshold voltage shift is plotted versus implanted dose in

IElO lEll IE12 DOSE IN SILICON

IE13

D~ [crn-2]

Fig. 3. Magnitude of threshold voltage shift AVT plotted versus implanted dose in silicon D, for both depletion-mode (phosphorous) and enhancement-mode (boron) n-channel devices.

2 +max

+s -- - o b :

+B + VSX

Fig. 4. Simplified model for a depletion-mode device assuming a step approximation for its impurity profile.

silicon for both depletion- and enhancement-mode n-channel devices. The enhancement threshold shift follows the predicted qD,/Cox line until substantial shrinkage of the depletion layer width has occurred. Once X, has become shallower than the implantation depth Xi, the threshold voltage shift is then proportional to the square root of the implanted acceptor density. On the other hand, the depletion-mode threshold shift quickly departs from' the qD,/COx line at low dose levels, and the threshold voltage is shifted by an additional 0.5 V for a high dose of 1 El 2/cm2 combined with an oxide thickness of 250 A. For a dose exceeding approximately 1.4E12/cm2, the device can no longer be turned off for a substrate bias of zero volts.

Determination of an expression for the surface potential shift is more complicated than for the oxide voltage term. Fig. 4 gives a simplified model for the depletion device in

906. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 4, APRIL 1979

which the implanted dose is modeled by a rectangular profile of height No extending between 0 and Xi. It is assumed that the background concentration N A is constant and the depletion layer width xd exceeds the depth of the implantation. The electric field and potential of Fig. 4 are obtained by assuming full depletion between the surface and x,.

The surface potential shift in the depletion device i3 given by A@, = &,,ax - q5s where &,ax = -$JB at threshold as discussed earlier, and (pg is the potential in the p-type bulk. Using the depletion approximation the following relaticnships may be derived:

At threshold, A$s is given by (4) in which Xp is calculated with = - $ B , and the dependence of A& upon substrate voltage is contained in (3). Using (1)-(4), the expression for the overall depletion-mode threshold voltage shift, referenced to the nonimplanted device threshold at zero substrate bias, becomes

The first term is the oxide voltage shift term showing the usual dose dependence. The second term shows a dependc nce upon the first moment of the dose, and the imp1anta:ion depth Xi also enters into the third term.

Using (5), the threshold voltage shifts have been calculs.ted for an ion-implanted depletion-mode device at room t:m- perature, and are given in Table I. The actual impurity distribution is approximated by a step profile shown at the bottom of Fig. 5. The peak concentration is extended to a depth Xi to make the area under the two curves equal.

TABLE I

vsx A " 0 X A+s AVT

(volts) ( v o l t s ) ( v o l t s ) ( v o l t s )

0 .98 .32 1 . 3 0 - 1 - 2

- 8 8 .25 1.13 . 8 0 . 2 0 1.00

-3 . 7 5 -4

. 16 .E9 . I 4

. 9 1

.83 - 5 - 6

- 6 5 - 6 0 . 0 9

. I 1 .76 .69

REFERENCE POINT FOR SHIFT CALCULATIONS

-MEASURED DEVICE CHARACTERISTICS > 0 CALCULATED THRESHOLD VOLTAGES

- 1.5 ' I I I I I I J 1 2 3 4 5 6

vsx [VI T = 296K

APPROXIMATION NOX = 7EIOcm-2 T~~ = 2508

NA = 2.75E15cm-3 IMPLANTED D~ = g .3El lcm-2

PROFILE

x i

x [AI Fig. 5 , Comparison between measured and calculated depletion-mode

threshold characteristics VT versus Vsx. The calculated results are from Table I; they are based on the step approximation shown at the bottom.

Referring to Table I , the depletion layer expands with substrate bias, and the AVO, term is reduced. At the same time, Xp moves toward the surface, and the A@, term is also reduced. Thus the depletion-mode device exhibits a higher substrate sensitivity than the corresponding nonimplanted device. Fig. 5 compares these calculations to the measured depletion mode device characteristics. The dose has been reduced by approximately 5 percent to account for impurity freezeout at room temperature [16], [17] which was not included in the above formulation. At V,, = 0, the A@, term represents a 33-percent increase in shift over the AVO, term.

The above theory was developed on the assumption that &,,ax occurs below the surface. The surface potential shift term becomes zero when.Xp = 0. At this point, the device threshold behavior is similar to that of a normal surface device. The minimum junction depth required for X p > 0 is given by

which is a depth exceeded in most device designs.

Iv. THRESHOLD SHIFTS AT LOW TEMPERATURE At low temperature, donor impurity freezeout has a pro-

found effect on the threshold voltage of depletion-mode

JAEGER. AND GAENSSLEN: THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICES 505

77 1.83E16 485 2.4UEll - 0 3 .30 10 1 4.19E16 522 3.71Ell . 0 8 .50 146 8.54E16 555 F0.27Ell .20 -91 196 1.12E17 571 7.93Ell - 2 8 1 - 1 6 296 1.27E17 579 8.89B11 .32 1.32 --

c

v, >> vT DS = 9.3Ell cm-2 NA = 2.75E15 cm-3

Fig. 6 . Simulation results showing the total donor dose and the ionized portion over the temperature range from 296 to 77 K with the gate voltage well above threshold voltage VT. The low-temperature model uses the dashed approximations to the ionized portions of the donor dose.

devices [ 161, [ 1 7 ] . In the channel region, the conduction band edge bends near to the Fermi level and the donor impurities freeze out. At the same time, the acceptor impurities remain fully ionized. Donor ionization varies with position and is difficult to model in the general case. A model will be presented which is again based upon a step approximation to the actually implanted impurity profile.

Fig. 6 shows simulation results for the ionized portion of the donor dose over the temperature range 77-296 K well above tRreshold. This condition controls the apparent threshold of the surface channel device [ 161, [ 1 7 ] . Little freezeout occurs near the implantation depth Xi . Freezeout increases toward the surface, and a plateau is reached followed by strong freezeout in the region of the surface channel. Fig. 7 shows t.he ionized impurity distribution at 77 K at threshold, flatband, and well above threshold. For V, >> VT, the ionized donor distribution follows that of the flatband case which reaches a plateau in the vicinity of X,.

The a.mount of freezeout will be estimated from a model of the flatband condition of Fig. 8. Full ionization is assumed at Xi with a linear decrease to the equilibrium ionized donor density N: at X p . The constant value N$ is assumed from X , to 0, N g is calculated using the method of Putley [ 181

t X i

T = 77K Dg= 9.3Eii cm-2 NA= 2,75Ei5cm-’

I-L 800 1000

Fig. 7. Total donor dose and simulations of ionizeid impurity distribu- tions under the gate at a temperature of 77 K with the gate at threshold, flatband, and well above threshold potential.

t “t A

I

Fig. 8 . Approximated impurity profile for modeling of low-temperature threshold voltage shifts.

This model omits the strong freezeout near the surface, but this is compensated by an overestimate of freezeout in the vicinity of X , as shown in Fig. 6. As temperature is reduced, donor freezeout causes X , to move further toward the surface of the device. Ignoring the shaded area for the moment, the new value of X , may be calculated from Fig. 8 since the total charge must be equal to zero between X , and X ,

In calculating X p , x d may be assumed to be constant since it is almost independent of ND if No >>NA (see (2)) . The active dose from Fig. 8 is given by

Dact = N i x , t 4 (No t N g ) (Xi - X,) .

The AVO, term may be calculated using Daat. The A& term is estimated using NE and X , in (4).

Results of application of this model to a depletion device are given in Table I1 and Fig. 9 . Good agreement is obtained over the full temperature range.

The threshold voltage shifts in the presence of substrate bias may also be computed using the model of Fig. 8. X,

506 IEEE TRP,NSACTIONS ON ELECTRON DEVICES, VOL. ED-26, NO. 4, APRIL 1979

, v, (V)

0501 [NON-IMPLANTED DEVICE

250 300 350

DEPLETION MODE DEVICE < -SIMULATED DATA -050

DONOR DOSE IN SILICON = 93Ellcrn

Fig. 9. Depletion-mode threshold voltage VT as function of temperature T. Numerical simulation results are compared against results calculated with simple analytical model.

TABLE 111

T = lOlK N; = 4.19E16

vsx P a 'dNA x A @ s A V T

(volts) ( X ) ( /Cm2) (/cm") (volts) (volts1

0 522 3.68E11 0 - 1

.08 410 4.15Ell 9.02E10 -05

.50

.42 -2 331 4.49E11 1.54Ell .03 .37 -3 267 4.76311 2.07Ell .02 -4

.33 209

-5 5.00Ell 2.53311 -01

158 5.21E11 2.95311 .01 -29 .26

-6 110 5.24311 3.33E11 .OO -24 -.

I I I I I I I

DEVICE ( T I

0.25

- 0.25 -t /e+@--- 96K 1

#--296K 1 /- - MEASUREMENTS

CALCULATED VALUES

-1.50 -1.0 -2 .0 -3.0 -4.0 -5.0

vsx ( V I

Fig. 10. Comparison between measured and calculated threshold voltages VT as function of substrate potential V,, with temperature as parameter.

is calculated using (2), and X , is then determined from (7). A& is computed using N: and X, , and AVO, is calculilted using Dact - (X, - X:) NA . A sample of this set of calculations is given in Table 111. The threshold voltages, based upon the calculated threshold voltage shifts and the nonimplarlted device curve of Fig. 9, are displayed in Fig. 10. The simple model provides good agreement with the measured device characteristics, and also indicates that the step approximasion to the implanted profile does indeed model the dominant effects of the implantation even at low temperature.

IE l I - LOV,

V DEPLETION MODE DEVICE

IE5 /, , , , , r: ZqBK, , , , , ,I 1 ~ 4 -0 .5V

IE3 - 2 . 5 -2:O -1.5 -1.0 - 0 . 5 0 0.5 1.0

-1E161 ''

Tox=250A N,,=IE10crn-2

vG

Fig. 11. Simulations of channel carrier concentrations NCH as a function of gate voltage VG with substrate potential as parameter. This figure illustrates parasitic subthreshold conduction and its variation with substrate voltage V#,. Threshold voltage is defined for a channel carrier concentration of 1E10/cm-2.

The origin of the low substrate sensitivity which is apparent in the depletion-mode device at low temperatures can be understood more fully by referring again to Fig. 8. If the substrate potential becomes more negative, (2) and (3) show that X , will move to the left and x d will move to the right. More donors will become ionized as indicated by the shaded area on the left, and these donors compensate the increased number of acceptors uncovered in the bulk. The total change in bound charge may easily be computed from Fig. 8, again assuming that the electric field is zero at X , . First

Now, the total change in depleted charge is given by

which, typically, represents a reduction by a factor of approximately ~ N : / N D over the nonimplanted device case. Thus low substrate sensitivities should be possible for N: << N o . Note from (6), however, that N: 2 N A so that the slope of VT versus V,, must remain positive.

V. PARASITIC SUBTHRESHOLD CONDUCTION If the depletion-mode dose is too large and/or resides at

too great a depth, the device will not exhibit normal turn-off in the subthreshold region. A plateau region [l 11, [14] will exist as shown in Fig. 11 in which it is impossible to completely quench the channel with the gate. This plateau region is not desirable in logic or memory circuits requiring complete turn-off of the depletion-mode device [19]. The plateau occurs when the n-type surface reaches inversion before the channel disappears completely. Referring to Fig. 4, the desired condition is that &,ax Q 0 for @# = @B + Vsx. For this condition, the channel has disappeared by the time the surface inverts. This requirement is much stronger than the condition discussed in [l I ] since it requires complete dis- appearance of the channel rather than just merging of the surface and junction depletion regions.

JAEGER AND GAENSSLEN: THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICES 507

Solving ((3) and (4) for Xi under the conditions @, = @B t V , x and @max G 0

Using (8), the depth Xi of the dose must be less than 1550 A if a subthreshold plateau region is to be avoided for the design of Fig. 11 at V,, = 0. Using the above criteria, the device of Fig. 11 should exhibit normal subthreshold turn-off for V,, G -0.50 V which is in good agreement with the simulated behavior.

An additional interpretation of the turn-off condition can be found in Fig. 4. Under the assumption of full depletion, A@, = - @, is a constant for a given value of V,, . So if (4) yields a value of A& > @B t Vsx, then the device will not turn off when 4, = @B f V,, .

The degree of suppression of conduction in a device which does not turn off may also be estimated using (3) and (4). The ratio of peak electron concentration in the channel to that at tl~reshold is given by

(1 0)

The plateau conduction levels predicted by (9) and (10) for the device of Fig. 11 at V = 0, -0.1, and -0.25 are 1.2E8, 2.5E6, and 7.5E3 electrons/cm2, respectively. These estimates are about a factor of 5 higher than the simulated plateau levels shown in Fig. 11 for a gate voltage of -2.75 V. The dis- crepancy results from the fact that the surface potential is not pinned precisely at @B t V,,, but can decrease somewhat below this value. Therefore, these predictions represent an upper bound to the subthreshold conduction level.

VI. SUMMARY Simple analytical models have been developed for the

temperature dependent threshold behavior of depletion- mode devices. The models include the effects of impurity freezeout and accurately predict device behavior from 296 to 77 ‘K including the effects of substrate bias. A simple model for th’e low substrate sensitivity of depletion-mode devices at low temperature has also been developed. The models are based upon step approximations to the ion-implanted profiles and indicate that this approximation accurately represents the effects of the implantation even under freezeout conditions.

ACKNOWLEDGMENT It is our pleasure to acknowledge many helpful discussions

with B. L. Crowder and the excellent technical support of J. J. Walker, who performed the electrical characterization of the devices used in this study. We also wish to acknowledge the processing support of the silicon technology group at the Thomas J. Watson Research Center, Yorktown Heights, NY.

REFERENCES R. W. Keyes, E. P. Harris, and K. L. Konnerth., “The role of low temperatures in the operation of logic circuits,” Proc. ZEEE, vol. 58, pp. 1914-1932, Dec. 1970. F. H. Gaensslen, V. L. Rideout, E. J. Walker, and J. J. Walker, “Very small MOSFETs for low temperature operation,” ZEEE Trans. Electron Devices, vol. ED-24, pp. 218-229, Mar. 1977. J. S. T. Huang and G. W. Taylor, “Modeling of an ion-implanted silicon-gate depletion-mode IGFET,” ZEEE Trans. Electron Devices, vol. ED-22, pp. 995-1001, Nov. 1975.. T. E. Hendrickson, “A simplified model for subpinchoff conduction in depletion mode IGFET’s,” ZEElS Trans. Electron Devices, vol. ED-25, pp. 435-441, Apr. 1978. R. A. Haken, “Analysis of the deep depletion Mosfet . . . ,” Solid-State Electron., vol. 21, pp. 753-761, May 1978. G. R. Mohan R.ao, “An accurate model for a depletion mode IGFET used as a load device,” Solid-State Electron., vol. 21,

V. L. Rideout, F. H. Gaensslen, and A. LeBlzmc, “Device design considerations for ion implanted n-channel MOSFETs,” ZBM J. Res. Devel., vol. 19, pp. 50-59, Jan. 1975. R. R. Troutman, “Ion-implanted threshold tailoring for insulated gate field-effect transistors,” IEEE Trans. Electron Devices, vol. ED-24, pp. 182-192, Mar. 1977. S. Horiuchi, “Threshold voltage shift of n-channel Si-gate MOSFETs,” ZEEE Trans. Electron Devices, vol. ED-22, pp.

T. Tanaka, “Shift of the gate threshold voltage of MOS transistors due to the introduction of shallow impurities,” Jap. J. Appl. Phys.,vol. 10,pp. 84-91, Jan. 1971. R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistors in low voltage circuits,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 146-153, Apr. 1972. T. W. Sigmon and R. M. Swanson, “MOS threshold shifting by ion implantation,” Solid-state Electron., 7/01. 16, pp. 1217- 1232,1973. M. R. MacPherson, “Threshold shift calculations for ion implanted MOS devices,” Solid-State Electron., vol. 15, pp. 1319- 1326,1972. T. Masuhara, “Low level currents in ion-implanted MOSFET,” ZEEE Trans. Electron Devices, vol. ED-21, pp. 799-807, Dec. 1974. W. Schemmert, L. Gabler, and B. Hoefflinger, “Conductance of ion-implanted buried-channel MOS transistors,” ZEEE Trans. Electron Devices, vol. ED-23, pp. 1313-1319, Dec. 1976. F. H. Gaensslen, R. C. Jaeger, and J. J. Walker, “Low temperature threshold behavior of depletion mode devices-characterization and simulation,” in IEDM Tech. Dig., Dec. 1977, pp.

F. H. Gaensslen and R. C. Jaeger, “Temperature dependent threshold behavior of depletion mode IldOSFETs-Character- ization and simulation,” Solid-State Electron., vol. 22, pp. 423- 430. Am. 1979.

pp. 711-714, May 1978.

1038-1043, NOV. 1975.

5 20-5 24.

[18] E. H. Putley, Hall Effect and Related Phenomenon. London, England: Butterworth, 1960, pp. 122-132.

[19] R. W. Knepper, “Dynamic depletion mode-An E/D mosfet circuit method for improved performanmce,” ZEEE J. Solid- State Circuits, vol. SC-13, pp. 542-548, Oci:. 1978.

~,~ L - ~~ -

Richard C. Jaeger (SY68-M’69-SM’78) was born in New York, NY, on September 2, 1944. He received the B.S. and M.E. degrees in electrical engineering in 1966 and the Ph.D. degree in 1969, all from the Uni- versity of Florida, Gainesville.

508 X X Z Ti~.hKSACTIIONS ON ELECTRON DEVICES, VOL. ED-26, NO, 4 , APRIL 1919

Process Modeling ‘and Design Procedure for IGFtflr Thresholds

Abstruct-An empirically based process modeling system is discussed for determining ion-implant conditions used to achieve specif‘ic: IGFET thresholds. Experimental techniques are applied to insure consistmcy between physical process phenomenon and the numericall algorithms employed. Device threshold design results are presented folr active and parasitic IGFET’s in a dual polysilicon-gate technology. Tlhe utility of this design procedure in multistep processes for determining the effects of various parameters such as screen thickness, final peak concer:tra- tion, dose, and energy are considered.

INTRODUCTION

I ON IMPLANTATION as a process technology is rapidly becoming the principal method of impurity introtiuc.tior. in

semiconductor processing. The technique lends itself to be used as a predeposition, offering precise control of clopmt concentration [l] , 121. In addition, the advantages offe!,ed by uniformity within a wafer, and wafer to wafer, as well as the depth control provided by implantation, have expanced the application to include FET threshold adjustment and substrate sensitivity control [3] , [4]. The simple case of a sin,gle heat cycle is amenable to analytic techniques as previou:;ly studied [5] , [6] . However, since the dopant is often i n t o - duced early in the process and/or subjected to extensive post- implant thermal processing, numerical process models have been implemented to predict the final concentration as a furc- tion of depth [7] -[9] . Thus for multigate processes, whi:h often have at least five implant steps and multiple hr:ati:lg cycles, it is desirable to have the selection of dose and e.neri:y as a designable feature to meet device requirements. In adtli- tion, process sensitivity can be readily ascertained if the nu-

Manuscript received June 1 5 , 1978;revised December 14,1978. The authors are with the IBM General Technology Division, Essc’x

Junction, VT 05452.

merical process model is complete enough to include all relevant physical phenomena.

In this paper, a process model is described and applied to typical IGFET designs. The necessary parameters considered, together with the typical end forms of the device requirements, are explored. Empirical techniques are used to determine critical model parameters. Design of active IGFET’s with gate oxides of from 25 to 63 nm and parasitic isolation ldevices with 300 to 600 nm gate oxide thicknesses were se- llected for this study. This device class separates this work from that of other workers [ 9 ] in that the ionized acceptor concentrations are significantly lower ( 1 0 ~ ~ - 1 0 ~ ~ ~ r n - ~ range) due t o the required device characteristics. Experimental evidence is presented to support the success of the design procedure. This procedure may be employed for both n- and p-channel and depletion as well as enhancement-mode IGFET’s. In this work, the experiments and examples presented are exclusively for an n-channel enhancement technology. Furthermore, a key feature of the procedure is the use clf a process model to assess the impact of each high- temperature step on the profiles for accurate results.

DESIGN PROCEDURE AND CONSIDERATIONS

Implant parameters (energy and dose) for threshold tailoring of IGFET’s are usually driven by two factors: the final device characteristics and the particular fabrication technology. The latter must be selected to meet system or product class requirements in a reliable and economic fashion. However, ion implant and subsequent thermal effects, more than any other process, often determine whether or not the device will be realizable in a particular process technology. More specifically, the ion-implant design in concert with the total process must

0018-9383/79/0400~0.508$00.75 0 1979 IEEE

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Simple analytical models for the temperature dependent threshold behavior of depletion-mode devices