Silicon 10% test status D0 Collaboration Meeting - Plenary meeting Marian Zdražil October 13, 2000

Silicon 10% test status

D0 Collaboration Meeting - Plenary meeting

Marian ZdražilOctober 13, 2000

D0 Plenary meeting 10/13/00 2

Why the 10 % Test ?The Silicon Readout System constitutes a major challenge due to its:» Complexity : Complexity : large number of different individual readout components which have to

work together with an extreme accuracy to achieve a high data integrity.

» Scope :Scope :

PHASE 1 : testing and debugging of individual readout components ( from SVX chips to L3)

PHASE 2 : setup of complete readout system to check data integrity and noise; exercise L3 software, online monitoring with EXAMINE, SDAQ,…

PHASE 3 : readout of a full barrel+disk; exercise acquisition control; establish barrel/disk test station; cosmic test with this setup

PHASE 4 : shake down after installation in the pit

Ensure proper performance

Provide adequate operating marging for the experimental device

Exercise acquisition control and software

Address large scale system problems Establish barrel/disk test-station

No surprises wanted !!!No surprises wanted !!!

Have to make sure it works in Have to make sure it works in DABDAB


Silicon Readout Data Flow

platformplatform

SEQ

SEQ

SEQ

SEQ

SEQ

SEQ

3/6/8/9 Chip HDI

Sensor

8’ Low Mass Cable

~19’-30’ High Mass Cable (3M/80 conductor)

VRB Controller

Optical Link1Gb/s

V

B

D

V

R

B

V

R

B

V

R

B

V

R

B

68k/PwrPC

Bit3

PC

SDAQ (Silicon Graphics) L3MPM

VME1553

HV / LV

Adapter Card

I,V,T Monitoring

KSU

Interface Board

25’ High Mass Cable (3M/50 conductor)

CLKs CLKs

SEQController

Serial Command Link


The 10% Test

Complete readout system in final readout configuration installed in Lab C clean room at SiDet

Potential to readout 10% of Silicon Tracker ( ~ 80,000 readout channels )

Adapter cards & low-mass cables

Adapter cards & low-mass cables

KSU IB crateKSU IB crate

VRB crateVRB crate Seq crate & G-linkSeq crate & G-link

HV system & distribution panelHV system & distribution panelL3 nodeL3 node


Overall Status Experience with FD14 ( July 31 - Aug 11 ) : valuable experience !

• Cooling system operation continuous• Device protection tools tested and understood ( cooling interlocks, KSU

IB temperature and current trips )• Development/testing of software : DBGui download, 1553 monitoring

( Strip Tool ), SMT Examine• Many small readout problems understood and fixed. Very stable

readout system operation during two overnight runs significant degree of data integrity achieved

17 HDIs into 3 IBs/Seqs/VRBs ( 8 FW6 + 9 FW8 = 120 chips ); data transfer rate to L3 : ~700 Hz, ~80 Mevents, ERROR FREE ( 15,360 channels readout, ~ 1013 bits tested )

Readout tests with BA1 ( Aug 30 - Sept 18 ) :

• Cabling/testing procedures exercised and understood ( long & painful )• Discovered short of PriGuard to GND at the KSU IB surgical work on every low-mass cable ! ( pin lifted in the Hirosi connector; these cables do not go to the experiment and problem was solved for the final version of adapter card ) • Data integrity runs very successful - 4 overnight runs 57 ladders into 9 Ibs/Seqs/VRBs ( 30 L9 + 27 L3 = 351 chips ); data transfer rate to L3 : ~250 Hz, ~42 Mevents, ERROR FREE ( 44,928 channels, ~3 x 1013 bits tested )


Overall Status ( cont’d )

Readout tests with BA4Readout tests with BA4 ( Sept 26 - now ) :

• Discovered minor problems ( CalInject = Seq problem ); hook up and check out went smoothly ( all channels were already tested at BA1 ! )• Data integrity runs successful - 3 overnight runs 57 ladders into 9 Ibs/Seqs/VRBs ( 31 L9 + 32 L6 = 471 chips ); data transfer rate to L3 : ~200 Hz Readout of 60,288 channels ERROR FREE at 23.6 Mbyte/s !! ( whole calorimeter is 55k ! ) Combined readout tests with BA4 + FD6Combined readout tests with BA4 + FD6 ( Sept 26 - now ) :

• Discovered minor problems ( CalInject, HV PS module problems ) while connecting FD6; hook up and check out went smoothly ( using 24 low-mass cables from the experiment - extreme care has to be taken )• Data integrity runs - this weekend BA4 : 57 ladders into 9 IBs/Seqs/VRBs ( 31 L9 + 32 L6 = 471 chips ) FD6 : 24 F-wedges into 3 IBs/Seqs/VRBs ( 12 L8 + 12 L6 = 168 chips )

Future :Future : readout tests with H-disk, if time permits cosmic tests BA4 + FD6,

Barrel installed in dry boxBarrel installed in dry box

HDI connection to low-mass cableHDI connection to low-mass cable


Hardware Configuration

Readout Elements :Readout Elements :

• Most of the Hardware is production version. Exceptions : KSU IBs - kludges ( e.g. CLK compensation circuit, DVALID deglitching circuit,…) and adapter cards ( fix for PriGuard shorted to GND )• Cannot readout more than 60 ladders due to the lack of low-mass cables, Seq back-plane problems, etc. • Barrel readout requires only 9 KSU IBs/Seqs/VRBs at D0 we will have 9 VRBs in a crate. However in the 10% Test are placed 12 VRBs required for barrel + F-disk readout in one crate.• HV System : total of 168 pods => ability to apply “split bias” individually to every ladder in a barrel + F-disk ( at D0 : share HV pod among 4 ladders !! )Interlock System and Trips :Interlock System and Trips :

• Cooling System Interlocks : implemented trips based on• coolant temperature, flow through bulkhead trips power for entire KSU IB crate• humidity inside box trips chiller

• KSU IB trips : SVX power tripped off if I > 750 mA or TRTD > 40 °C ( trips occur on HDI-by-HDI basis )• HV System trips : HV tripped off if V > 100 V or I > 50 A ( large current transients during ramp up reaching 30 A ! )


Software Tools

DetectorDetector

Readout CrateReadout CrateControls CrateControls Crate

UNIX Hosts

Control Room PCs

EPICS Clients: SVX Download Low Voltage High Voltage 1553 Devices Rack Monitor

EPICS Clients: SVX Download Low Voltage High Voltage 1553 Devices Rack Monitor

Controls

Ethernet

ORACLEORACLE

HardwareDatabase

EPICS DB GeneratorEPICS DB Generator

1553

UNIX HostsControl Room PCs

Data Cable L3 SupervisorL3 Supervisor

L3 VRCL3 VRC

L3 FilterL3 Filter

Data Cable

NT Level 3

Ethernet

ExamineExamine

Collector / RouterCollector / Router

Data LoggerData

Logger

Disk

Data Distributor

Data Distributor

Download : download of SVXs, Seqs, VRBs and VBD from the hardware DB ( DBGui or spreadsheet )KSU IB Monitoring : 1553 monitoring of I, V, T and Status in KSU IB. Strip charts.HV Control and Monitoring Alarms : issue alarms before a trip condition occursSMT Examine : Online and offline data monitoring/analysis PDAQ : Raw data packed in the SiDet L3 node running Script runner and sent to the online host where it is written to disk and tape. Also exercised unpacker and cluster tool.SDAQ : Calibration run at the FE processor ( PwrPC ) computing average pedestal, sigma and gain per channel. Calibration data loaded into Calibration DB, chip threshold computed and SVX chip downloaded for sparse readout. Not exercised with BA1 but it should be exercised with BA4 !


Turn-on procedures Whole readout chain mapped out and tested before barrel installation ( 1553 monitoring of I, V and T, download and readout, HV distribution and trips, KSU IB trips Proper functionality of cooling system interlocks verified Every ladder is connected at a time. Functionality test performed : take pedestal and CalInject events with/without silicon biasing ( HV ramped up at 2 V/sec, in steps of 30%, 60% and 100% ). No cooling needed for this operation ! Simultaneous turn-on of more than 1 ladder requires cooling :

Box containing the barrel kept closed and dry ( dual system of dry air and N2 ) typically dew point inside the box ~ -10 °F Operating point : Tcoolant = 50 °F TRTD ~ 15-20 °C

Stable operation of cooling systemStable operation of cooling system


Preliminary ResultsData Integrity tests :Data Integrity tests :

Long runs in checksum mode for full device Data fixed to a known value ( 0x14 ) and shipped to the L3 node, where every bit is

checked.

The aim is to discover any readout problems associated with a large system : cross-

talk,

marginal timing issues due to the spread in the system, etc. Only summary files specifying the errors are written to disk at the end of the run

Low-mass cables in 3 bundles tightly stacked for ~50-60 cm run without foam try to

maximize cable-to-cable cross-talk. No effects observed ! Very stable DAQ - halted only a few times by L3 node ( to be understood yet ) Data transfer rate 250 Hz, depending on the number of devices read out

57 ladders 91.4 kbytes transfer rate to L3 ~ 22.7 Mbytes/sec

Total number of events read in for BA1 : ~42M 3 x 1013 bits ERROR FREE These tests have been successfully carried out for all Det Configuration by now !

# Ladders# Ladders Det Configuration 9-chip 8-chip 6-chip 3-chip Total Total # of chips Total # of Det Configuration 9-chip 8-chip 6-chip 3-chip Total Total # of chips Total # of readoutCHNreadoutCHN FD14 - 9 8 - 17 120 15,360 BA1 30 - - 27 57 351 44,928 BA4 31 - 32 - 63 471 60,288 BA4 + FD 43 - 44 - 87 651 83,328


Preliminary Results ( cont’d )

Noise studies :Noise studies :

Short runs ( ~ 1k-10k events ) performed during a daytime. Data monitoring with Online Examine and written to disk for offline analysis. Data taken in different conditions : HV on/off for all/some bundles, different Preamp

Bandwidth settings, etc.

Very good noise characteristics : total noise 2 ADC counts for reasonable SVX

settings Almost ideal Gaussian pedestal distribution for chips without noisy channels. Tails

understood whenever present. Didn’t run in sparse mode ( didn’t exercise SDAQ ) but can “simulate” it with SMT

Examine and study occupancy.


Temperature monitoring of BA4

0

5

10

15

20

25

-5 0 5 10 15 20

Delta T (degrees C)

Measured

Fit

Sigma = 1.25 degrees C

Mean = 11.1 C

Temperature versus position along path

-5

0

5

10

15

20

25

30

35

.5 4

i-6

4i-

7

4i-

8

.5 4

i-9

3i-

8

3i-

7

3i-

6

.5 2

i-3

2i-

4

.5 1

i-5

1i-

4

1i-

5

.5 1

i-2

2i-

2

.5 2

i-3

3i-

5

3i-

4

.5 3

i-3

4i-

3

4i-

4

4i-

5

.5 4

i-6

Ladder

Te

mp

era

ture

(d

eg

ree

s C

)

Unpowered

Powered

Difference

Temperature versus position along path

-5

0

5

10

15

20

25

30

35

.5 4

i-1

2

4i-

11

4i-

10

4i-

9

.5 3

i-9

3i-

10

3i-

11

.5 2

i-6

2i-

5

.5 1

i-5

1i-

6

1i-

1

.5 1

i-2

2i-

1

.5 2

i-6

3i-

12

3i-

1

3i-

2

.5 3

i-3

4i-

2

4i-

1

.5 4

i-1

2

Ladder

Te

mp

era

ture

(d

eg

ree

s C

)

Unpowered

Powered

Difference

Ladders temperature spread for both cooling channelsLadders temperature spread for both cooling channels

Powered/Unpowered ladder temperature distribution for BA4Powered/Unpowered ladder temperature distribution for BA4


Summary and Plans Exercised barrel cabling, device protection measures ( interlocks and monitoring ) and full data acquisition with almost final readout hardware. Experience gained is invaluable for commissioning at D0. Two major goals accomplished :

• certified adequate noise characteristics of BA-1 and BA-4 ( one of the most critical ones in terms of potential grounding problems ).• established unprecedented degree of data integrity of our silicon readout system in a large scale operation. First convincing prove of the principle. At this point,

Significant degree of confidence that it works out at D0 !PLANS :PLANS :

Will continue chasing system bugs and problems pushing the limits to achieve nominal 10% of readout channels : BA4 + FD6. Hope in a window of opportunity for a Cosmic Ray Test with BA4 + FD6 At the end of this month : noise studies on a H-disk. First week of November : See you at D0 !!! 50% Test turns to be a reality. Worries :Worries :

KSU IB delivery slow ! ( 15 boards a week, total of 144 IBs needed ). Anticipated complete delivery by early Jan 2001. HV PS delivery slow.

Documents

Silicon 10% test status D0 Collaboration Meeting - Plenary meeting Marian Zdražil October 13, 2000