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SHIVAM TRIPATHITelephone: 0120-4983646, Mobile: 07838010934
Email: [email protected]
A competent professional with distinction of executing prestigious projects of largemagnitude within strict time schedule
PROFILE SUMMARY
Bachelor of Electrical and Electronics Engineering with nearly 3 years of experience in Development/Verification of Memory Layout
Skilled in undertaking layout design and development, design of test routines, designing verification, functional testing.
Expertise in coordinating from different location/internal departments for ascertaining specifications
Track record completing up projects with competent cross functional skills and ensuring on time deliverables within pre set parameters
Abilities in assisting with performance tuning requests; developing tools for performance monitoring and performance testing.
Helping CAD team by providing various test cases. Helping in developing lots of automations to improve efficiency of layout. Well versed with BIST enable & redundancy Enable memory features of memory
architecture Proficient in leaf cell development of memory features of memory architecture Proficient in leaf cell development of memory compilers RAM/ROM Worked on memory compiler: Intel 14nm, Intel 22, TSMC 28nm and TSMC
40nm. Efficient organizer, motivator, team player and a decisive leader with the ability to
motivate teams to excel and win.
CORE COMPETENCIES
Coordinating every aspects of design and layout of memory compilers Designing layout, developing, testing and debugging of memory compilers Preparing technical specifications according to business needs; suggesting
improvements to existing layout designs Understanding requirements and providing use cases for functional & technical
requirements Interacting with users for requirement gathering; preparing functional
specifications and low-level design documents Participating in the layout development lifecycle right from requirement analysis,
documentation (functional specifications, technical design), LEAFCELL development and verification to maintenance of proposed application.
ORGANISATIONAL EXPERIENCE
Synopsys India Private Ltd. (Memory Layout), Noida as ASIC/Layout Design Engineer
Highlights:
Worked on memory compiler: Intel 14nm, Intel 22nm, TSMC 28nm, TSMC40nm
Received award for extra ordinary efforts for completing all the required qualitychecks for Intel 14nm to meet the business requirements.
Receives award for automation which reduces the efforts to make characterizationcells for extraction.
Key Projects (latest on top)
Description Intel 10nm Role Layout EngineerContribution
Responsibility Layout designing for leafcell.LVS/DRC cleaning after post Layout
Development/ProductivityTools
Synopsys Custom Designer , Synopsys ICV ,SynopsysHSIMRA simulation tools
Period Started working on itTeam Size 6
Description Intel 14nm Role Layout EngineerContribution
Responsibility Layout designing for leafcell.LVS/DRC cleaning after post Layout. Extraction ofchcells and solving errors related to it. Responsibilityfor making Center cells for memory and delivery offinal lef to the Customer.
Development/ProductivityTools
Synopsys Custom Designer , Synopsys ICV ,SynopsysHSIMRA simulation tools .Totem for EM/IR.
Period 1 yearTeam Size 5
Description TSMC 40nm Maintenance projectRole Layout EngineerContribution
Responsibility Fixing major ECO’s in design and have responsibilityto release it on time Fixing DRC, LVS in the layout.Solving any LVS related issues after post migration.Extraction of chcells , Solving EM/IR issues.
Development/ProductivityTools
Synopsys Custom Designer, Synopsys ICV ,SynopsysHSIMRA simulation tools , Calibre for DRC andLVS.
Period 2 monthsTeam Size 2
Description Intel 22nm Role Layout EngineerContribution
Responsibility Layout designing for leafcell.LVS/DRC cleaning after post Layout. Extraction ofchcells and solving errors related to it.
Development/ProductivityTools
Synopsys Custom Designer , Synopsys ICV ,SynopsysHSIMRA simulation tools ,Totem for EM/IR.
Period 8 monthsTeam Size 5
Description TSMC 28nm Role Layout EngineerContribution
Responsibility Fixing major ECO’s in design ,Fixing DRC, LVS inthe layout.Solving any LVS related issues after post migration.Extraction of chcells , Solving EM/IR issues.
Development/ProductivityTools
Synopsys Custom Designer , Synopsys ICV ,SynopsysHSIMRA simulation tools
Period 2 monthsTeam Size 2
IT SKILLS
Possess sound knowledge on mentor graphics, Caliber, Synopsys IC Designer,Synopsys ICV, Hsimra (Xara) ,Synopsys Hercules
ACADEMIC DETAILS
Bachelor of Electrical and Electronic Engineering from INTRGRAL UNIVERSITY , Uttar Pradesh Lucknow with 68% in 2011
PERSONAL DETAILS
Date of birth: 15th Aug 1988Languages known: English & HindiMailing address: 1473 Block I-2 Gaur Grandeur, NoidaUP- 201301
All the information provided is correct and authenticated.Date:Place:
(Shivam Tripathi)
