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Shift Register
Section 6.1-6.2
Register• A register is a group of flip-flops,
each one of which is capable of storing one bit of information.
• Issues of the circuit to the right.– You do not have an option hold
the output when you don’t want to outputs updated.
4 D flip-flops=4 bits of storage=4-bit register
4-bit Register with Parallel Load Control
Load=“1”→Update“1”
“0”
“0”
“1”
“I0”
“I0”
I0 is fed to DFF when Load is a 1.
Load=“0”→Hold!“0”
“1”
“A0”
“0”
“0”
“A0”
A0 is fed to DFF when Load is a 0. So the outputis holding!
We will revisit this ideawhen we study the universalshift register.
Four-Bit Serial Shift Register
1 2 3 4
Q of DFF1 gets SI after the first rising edge of the CLKQ of DFF2 gets SI after the second rising edge of the CLKQ of DFF3 gets SI after the third rising edge of the CLKQ of DFF4 gets SI after the fourth rising edge of the CLK
Linear Feedback Shift Register
1 1 0 1
Exclusive OR
Content of Four-Bit Shift Register1 1 0 1
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
1 0 0 0
0 1 0 0
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
1 0 1 1
0 1 0 1
1 0 1 0
Block Diagram of a Universal Shift Register
This is called the universal shift register because it has both shifts and parallel load capabilities.
Functionality of the Universal Shift Register
Clear: to clear the register to 0.CLK: to synchronize the operations.{S1,S0} for mode control.A_par: register outputI_par: register inputMSB_in and LSB_in: serial inputs
Detail Implementation
Four-to-one-line Mux
Four-to-one-line Mux
1
0
11
I2 I2
0
0
00
0
0I2
Mode Control
S0=0, S1=0 [No Change Mode]
S0=0, S1=0
S0=1, S1=0 [Shift Right Mode]
S1=0 , S0=1
S0=0, S1=1 [Shift Left Mode]
S1=1 , S0=0
S0=1, S1=1 [Parallel Load Mode]
S1=1 , S0=1
Breadboard Implementation
Universal shift regsiter
Random Number Generator
Waveform
CLK
Random
A3
A2
A1
A0
4-Bit Universal Shift Register
Behavioral Vs. Structural Description
• Behavioral Description– Behavior model of a shift register• Describe the operation of the register
without a preconceived structure.
– Random number generator• Binary values of msb_in, lsb_in, i_par
• Structural Description–Models the circuits in terms of a
collection of components such as gates, flip-flops…
Behavioral Model of Shift Regsiter
a_par[3] a_par[2] a_par[1] a_par[0]
Test Bench
1. Generate random numberWith matlab2. Read random numberat the neg edge of the clock
Test all input combinations by flipping {S1, S0}
Read numbers to i_par[3:0],msb_in, lsb_in at the negedge of t_clock
[s1,s0=[1,1], Load
i_par=0111a_par=0111
[s1,s0]=[0,0], No Change
i_par=0111a_par=0011
[s1,s0]=[1,0], Shift Left
1101 1011
LSB_in
[s1,s0]=[0,1], Shift Right
Synthesized Schematic
Structural Modeling of a 4-Bit Universal Shift Register
clr
clk
select
Q
i0i1
i2i3
Waveform
Load No Change Shift Right Shift Left
4-bit Universal Shift Register
Verilog Code of Each Stage
In-Class Exercise
Load=“1”→Update“1”
“0”
“0”
“1”
“I0”
“I0”
I0 is fed to DFF when Load is a 1.
Load=“0”→Hold!“0”
“1”
“A0”
“0”
“0”
“A0”
A0 is fed to DFF when Load is a 0. So the outputis holding!
We will revisit this ideawhen we study the universalshift register.
S0=0, S1=0 [No Change Mode]
S0=0, S1=0
S0=1, S1=0 [Shift Right Mode]
S1=0 , S0=1
S0=0, S1=1 [Shift Left Mode]
S1=1 , S0=0
S0=1, S1=1 [Parallel Load Mode]
S1=1 , S0=1
If time permits
Serial Transfer Using Shift Register
Information in A is made to circulate by connecting SO to SI.
Parallel Transfer Versus Serial Transfer
Parallel TransferTransfer all the bit in one clock cycle.Require combinatorial circuits.
(Serial Transfer)
Take multiple clock cyclesto transfer data.
Assume n=4, each shift Register has 4 DFF.
Augend, Addend & Sum
1011+1001______10100
AugendAddend
Sum
Serial Adder
1
1
0
1
Feed “1” to zat the next rising edge of the CLK
Assuming a shift-right register, the left most position becomes availablefor storage after the second rising edge of the clock.
Note thatThe sum can bestored in a thirdregister.
But if you want to save shift register, you can store it in A since more and moreslots in SRA become available.
(Augend)
(Addend)
Serial Adder At the end of T4
A3A2A1A0
B3B2B1B0
________________
CoS3S2S1S0
S2S1S0A3
S3
Co
D2D1D0B3
Allowing the Serial Adder to Accumulate
Co
S3 S2 S1S0
D3D2D1D0
________________
Ro T3 T2 T1 T0
T2T1T0S3
T3
Ro
X2X1X0D3
Accumulate with a Shift Register
• A, B and D, each represents a 4 bit sequence.• We want to perform A+B+D• Store A in shift register A.• Store B in shift register B.• Allow the CLK to go on for a couple of cycles.• Store the sum bits of A+B in Shift A and allow
D to enter shift register B.• Allow more cycles of CLK. • Add D to A+B, and allow A+B+C to enter shift
register A.
