8/2/2019 SET 2 P III Q
1/2
Institute of Technology & Marine Engineering
Paper Name: Digital Electronics & Integrated Circuits
Paper Code: EC 402, Periodical III ExaminationECE 2nd Year,
Sem-4, Date: 27/04/12
Time: 50 Mins Full Marks: 20
Answer any four questions (45=20 marks)
1.What is a shift register? With a neat schematic explain how
J-K flip-flops can
be arranged to operate as a four-bit shift register. (5) (5)
2. What are the advantages of CMOS gates? Briefly explain an
NMOS two-
input NAND gate. (5)
3. What is the advantage of using Schottky transistors in a TTL
gate withtotempole output? Draw the circuit of a 2-input Schottky
TTL gate and
explain its features? (5)
4. Explain the working of a positive-edge-triggered Master-Slave
JK
flipflop. What are its advantages over a normal JK flipflop? If
all NAND
gates used in the flipflop have a propagation delay of 5 ns,
compute the
delay of the Master-Slave. (5)
5. Show how a SR flipflop can be constructed using NOR gates and
explain
the different states of the SR flipflop. (2+3)
6. What do you mean by MOD-number of a counter? Write the
step-by-step
procedure to construct any MOD-N ripple counter, where N is less
than ,
with n denoting the number of flip-flops. . (5)
7. Write the basic structure of a sequence generator using a
shift register and
design a sequence generator to generate the sequence 1101011.
(5)
8. In what type of applications is the ECL recommended? Justify
its suitability
in such application. Write the circuit of a 3-input ECL OR/NOR
gate and
mention its features. What is its logic symbol? (5)
9. Draw the circuit of a 3-input open-collector TTL NAND gate
and explain
its operation. (5)
Institute of Technology & Marine Engineering
Paper Name: Digital Electronics & Integrated CircuitsPaper
Code: EC 402, Periodical III Examination
ECE 2nd Year, Sem-4, Date: 27/04/12
Time: 50 Mins Full Marks: 20
Answer any four questions (45=20 marks)
1.What is a shift register? With a neat schematic explain how
J-K flip-flops can
be arranged to operate as a four-bit shift register. (5) (5)
2. What are the advantages of CMOS gates? Briefly explain an
NMOS two-
input NAND gate. (5)
3. What is the advantage of using Schottky transistors in a TTL
gate with
totempole output? Draw the circuit of a 2-input Schottky TTL
gate and
explain its features? (5)
4. Explain the working of a positive-edge-triggered Master-Slave
JK
flipflop. What are its advantages over a normal JK flipflop? If
all NAND
gates used in the flipflop have a propagation delay of 5 ns,
compute the
delay of the Master-Slave. (5)
5. Show how a SR flipflop can be constructed using NOR gates and
explainthe different states of the SR flipflop. (2+3)
6. What do you mean by MOD-number of a counter? Write the
step-by-step
procedure to construct any MOD-N ripple counter, where N is less
than ,
with n denoting the number of flip-flops. . (5)
7. Write the basic structure of a sequence generator using a
shift register and
design a sequence generator to generate the sequence 1101011.
(5)
8. In what type of applications is the ECL recommended? Justify
its suitability
in such application. Write the circuit of a 3-input ECL OR/NOR
gate and
mention its features. What is its logic symbol? (5)
