Session - I

MICROPROCESSORS-THE SOLUTION IN SEARCH OFPROBLEMS

In December 1970, Gilbert Hyatt filed a patent application entitled “Single Chip

Integrated Circuit Computer Architecture”, the first basic patent on the microprocessor.

The microprocessor was invented in the year 1971 in the Intel labs. The first processor

was a 4 bit processor and was called 4004.The following table gives chronologically the

microprocessor revolution.

Microprocess

ors

Year of

Introduct

ion

Word

Length

Memory

Addressi

ng

Pins Clock Remarks

4004 1971 4 bits 1KB 16 750KHz Intel’s 1st P

8008 1972 8 bits 16KB 18 800KHz Mark-8 used this;1st computer for

the home.

8080 1973 8 bits 64KB 40 2 MHz 6000trs, Altair-1stPC

8085 1976 8 bits 64KB 40 3-6 MHz Popular

8086 1978 16 bits 1 MB 40 5-10 MHz IBM PC, Intelbecame one offortune 500companies.

8088 1980 8/16 bits 1MB 40 5-8MHz PC/XT

80186 1982 16 bits 1 MB 68 5-8MHz More aMicrocontroller

80286 1982 16 bits 16 MB

real,

4GBv

68 60-

12.5MHz

PC/AT, 15million PC’ssold in 6 years

80386DX 1985 32 bits 4GB real, 132 20-33MHz 2,75,000transistors

64TBv PGA

80386SX 1988 16/32

bits

16MB

real,

64TBv

100 20MHz 32b int16b ext

80486DX 1989 32 bits 4 GB real,

64TBv

168

PGA

25-66MHz Flaot pt cop,Command lineto point andclick

Pentium 1993 64 bits 4 GB, 16

KB cache

237

PGA

60-200

MHz

2 intr. At a time,Process realworld data likesound, handwritten andphoto images.

Pentium Pro 1995 64 bits 64Gb,256K/512K L2Cache

387PGA

150MHz Speedy CAD

Pentium II 1997 64 bits 64Gb 242 400MHz Capture, edit &share digitalphotos viaInternet

Pentium IIXeon

1998 64 bits 512k/1M/2M L2cache

528pinsLGA

400MHz Workstationsthriving onbusinessapplications

Pentium IIIXeon

1999 64 bits 16 k L1data + 16k L1 instr;512 kB/1MB/2 MBL2

370PGA

1GHz e-commerceapplications

Pentium 4 2000 64 bits 514,864KB

423PGA

1.3 - 2GHz 1.5 GHz,Professionalquality movies,rendering 3Dgraphics.

Xeon 2001 64 bits 8 MB iL3cache

3.33 GHz Choice ofoperating system

Itanium 2001 64 bits 2MB/4MB L3cache

418pinsFCPGA

800 MHz Enabling e-commercesecuritytransactions

Itanium 2 2002 64 bits 1.5 – 611 200 MHz Business

9MB L3cache

pinsFCPGA

applications

Centrinomobile

2003 64 bits Mobile specific,increased batterylife.

Pentium 4processorextreme

2003 64 bits 2 MB L2cache

423pinsPGA

3.80 GHz Hyper threadingtechnology,games

Centrino M(mobile)

2004 64 bits 90nm,2MB L2cache400MHzpower-systemoptimizedsystem bus

MOTOROLA:

Microprocess

ors

Year of

Introduct

ion

Word

Length

Memory

Addressi

ng

Pins Clock Remarks

6800 1974 8 bits 64 KB 40 1MHz

6809 1979 8 bit 64 KB 40 4-8 MHz More powerful

68000 1979 16 bit 16 MB 64 10-25 MHz Popular

68008 1982 8 bit 1/4 MB 48/52pins

68010 1983 16 bit 16 MB IIW for VM

68012 1983 16/32

bits

2GB 84

pins

Increased

memory

addressing

capacity

68020 1984 32 bit 4 GB 114P

GA

12.5-

33MHz

256B instr cache

68030 1987 32 bit 4 GB 20-33MHz MMU

68040 1989 32 bit 4GB 20-25 MHz Floating pt cop

68060 64 bit 4GB +

16K cache

50MHz

PowerPC 64 bit 4GB +

32K cache

Apart from Intel, Motorola, Zylog Corporation, Fairchild and National (Hitachi, Japan)

are some of the other microprocessor manufacturers.

Microprocessors are used in all modern appliances, which are Intelligent, meaning that

they are capable of different modes of working. For example an automatic washing

machine has different wash options, one for woolen and the other for nylon etc., Also in a

printing Industry right from type setting to page lay out to color photo scanning and

printing and cutting and folding are also taken care of by microprocessors.

The applications of microprocessors can be sub divided into three categories. The first

and most important one is the computer applications. The second one is the control

application (micro controllers, embedded controllers etc.) and the third is in

Communication (DSP processors, Cell phones etc.).

The basis of working of all the microprocessors is binary arithmetic and Boolean logic.

The number system used is Hexadecimal (base 16) and the character code used is ASCII.

Many assemblers are available to interface the machine code savvy processor to English

language like programs of the users.(CP/M, MASM, TASM etc.).

For Games we have joysticks, electronic guns and touch screens. Nowadays laptop and

palmtop computers are proliferating and in future nano computing, bio computing,

molecular and optical computing also are contemplated.

Session - II

ADVANCED MICROPROCESSORS

Contents

• Microprocessor Based Personal Computer System

• Different Devices

• Summary of Simple Microcomputer Bus Operation

Microprocessor Based Personal Computer System

Different Components of Computers

• Microprocessor – 8086, 8088, 80186, 80188, 80286, 80386, 80486, Pentium,

Pentium Pro, Pentium II, Pentium III, Pentium IV

• Memory System – DRAM, SRAM, Cache, ROM, Flash Memory, EEPROM,

SDRAM, RAMBUS

• I/O System – Printer, Serial communications, Floppy Disk Drive, Hard Disk

Drive, Mouse, CD-ROM drive, Plotter, Keyboard, Monitor, Tape backup,

Scanner, DVD, Pen Drive

ADDRESS BUS

CONTROLBUS

CONTROLBUS

INPUTDEVICE

OUTPUTDEVICE

I/O PORTSCENTRAL

PROCESSINGUNIT (CPU)

MEMORY(RAM AND

ROM)

DATA BUS

Execution of a three-step computer program

0 1 2 3

4 5 6 7

8 9 + -

PORT 01 PORT 03

MEMORY

DA

TA

BU

S

AD

DR

ESS

BU

S

CONTROL BUS

CONTROL BUS

CPU

I/O

KEYBOARD DISPLAY

6A 5A 4A 3A 2A 1A 1B 2B 3B 4B 5B 6B

1C 2C 3C 4C 5C 6C

6D 2D2E 6F 2F 6E

PROGRAM

1. INPUT A VALUE FROM PORT 01

2. ADD 7 TO THIS VALUE

3. OUTPUT THE RESULT TO PORT 02

SEQUENCE

1A CPU SENDS OUT ADDRESS OF FIRST INSTRUCTION TO MEMORY

1B CPU SENDS OUT MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

1C INSTRUCTION BYTE SENT FROM MEMORY TO CPU ON DATA BUS

2A ADDRESS NEXT MEMORY LOCATION TO GET REST OF INSTRUCTION

2B SEND MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

2C PORT ADDRESS BYTE SENT FROM MEMORY TO CPU ON DATA BUS

2D CPU SENDS OUT PORT ADDRESS ON ADDRESS BUS

2E CPU SENDS OUT INPUT READ CONTROL SIGNAL TO ENABLE PORT

2F DATA FROM PORT SENT TO CPU ON DATA BUS

3A CPU SENDS ADDRESS OF NEXT INSTRUCTION TO MEMORY

3B CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

3C INSTRUCTION BYTE FROM MEMORY SENT TO CPU ON DATA BUS

4A CPU SENDS NEXT ADDRESS TO MEMORY TO GET REST OF INSTRUCTION

4B CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

4C NUMBER 07H SENT FROM MEMORY TO CPU ON DATA BUS

5A CPU SENDS ADDRESS OF NEXT INSTRUCTION TO MEMORY

5B CPU SENDS MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

5C INSTRUCTION BYTE FROM MEMORY SENT TO CPU ON DATA BUS

6A CPU SENDS OUT NEXT ADDRESS TO GET REST OF INSTRUCTION

6B CPU SENDS OUT MEMORY READ CONTROL SIGNAL TO ENABLE MEMORY

6C PORT ADDRESS BYTE SENT FROM MEMORY TO CPU ON DATA BUS

6D CPU SENDS OUT PORT ADDRESS ON ADDRESS BUS

6E CPU SENDS OUT DATA TO PORT ON DATA BUS

6F CPU SENDS OUT OUTPUT WRITE SIGNAL TO ENABLE PORT

Summary of Simple Microcomputer Bus Operation

1. A microcomputer fetches each program instruction in sequence, decodes the

instruction, and executes it.

2. The CPU in a microcomputer fetches instructions or reads data from memory by

sending out an address on the address bus and a Memory Read signal on the

control bus. The memory outputs the addressed instruction or data word to the

CPU on the data bus.

3. The CPU writes a data word to memory by sending out an address on the address

bus, sending out the data word on the data bus, and sending a Memory write

signal to memory on the control bus.

4. To read data from a port, the CPU sends out the port address on the address bus

and sends an I/O Read signal to the port device on the control bus. Data from the

port comes into the CPU on the data bus.

5. To write data to a port, the CPU sends out the port address on the address bus,

sends out the data to be written to the port on the data bus, and sends an I/O Write

signal to the port device on the control bus.

Session - III

ADVANCED MICROPROCESSORS

Contents

• Block Diagram of 8086

• segment registers

• 8086 flag register format

8086 Internal Block diagram (Intel Corp.)

The block diagram of 8086 is as shown. This can be subdivided into two parts, namely

the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment

registers, adder to generate 20 bit address and instruction prefetch queue.

Once this address is sent out of BIU, the instruction and data bytes are fetched from

memory and they fill a First In First Out 6 byte queue.

Execution Unit:

The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX

and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as

source index and destination index registers. The 16-bit scratch pad registers can be split

into two 8-bit registers. For example, AX can be split into AH and AL registers. The

segment registers and their default offsets are given below.

Segment Register Default Offset

CS IP (Instruction Pointer)

DS SI, DI

SS SP, BP

ES DI

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The

results of these operations can affect the condition flags.

Different registers and their operations are listed below:

Register Operations

AX Word multiply, Word divide, word I/O

AL Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic

AH Byte Multiply, Byte Divide

BX Translate

CX String Operations, Loops

CL Variable Shift and Rotate

DX Word Multiply, word Divide, Indirect I/O

Generation of 20-bit Physical Address:

IP

SR

DI

SI

BP

SP

DX

CX

AX

BX

ES

SS

DS

CS

Instruction Pointer

Code Segment Register

Data Segment Register

Stack Segment Register

Extra Segment Register

AH

Stack Pointer Register

AL

BE BL

CE CL

DH DL

Break Pointer Register

Source Index Register

Destination Index Register

Status Register

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

FFFFF16

00000016

8086/8088 MPU MEMORY

LOGICAL ADDRESS

SEGMENT REGISTER 0000

ADDER

20 BIT PHYSICAL MEMORY ADDRESS

8086 flag register format

There are three internal buses, namely A bus, B bus and C bus, which interconnect the

various blocks inside 8086.

The execution of instruction in 8086 is as follows:

The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and

fetches the first instruction of a program from the memory. Subsequent addresses are sent

out and the queue is filled upto 6 bytes. The instructions are decoded and further data (if

(a) : CARRY FLAG – SET BY CARRY OUT OF MSB(b) : PARITY FLAG – SET IF RESULT HAS EVEN PARITY(c) : AUXILIARY CARRY FLAG FOR BCD(d) : ZERO FLAG – SET IF RESULT = 0(e) : SIGN FLAG = MSB OF RESULT(f) : SINGLE STEP TRAP FLAG(g) : INTERRUPT ENABLE FLAG(h) : STRING DIRECTION FLAG(i) : OVERFLOW FLAG

(i)

(h)

(g)

(f)

(e)

(d)

(b)

(c)

(a)

0123456789101112131415

U U U U 0F DF IF TF SF ZF U AF U PF U CF

U= UNDEFINED

BIT

necessary) are fetched from memory. After the execution of the instruction, the results

may go back to memory or to the output peripheral devices as the case may be.

Session - IV

ADVANCED MICROPROCESSORS

Contents• Real mode memory addressing

• Segment Over Ride Prefix

Real mode memory addressing

The segment registers have contents of 16-bits. Hence, 216 = 64Kb of memory can be

addressed by segment registers. Normally, the segment base register contains three zeroes,

so that each segment can start from say E0000 to EFFFF. The segments namely code

segment, data segment, stack segment and extra segment for a particular program can be

contiguous, separate or in case of small programs overlapping even. i.e., for example,

code segment is supposed to have 64Kb and in case of small programs data segment may

be within the code segment. To give you an example of the segment base and offset, we

can consider the telephone numbers. For example, 23322651 is a telephone number out

of which, 2 is a universal code, 332 is the area code, and 2651 is the offset in that area. In

other words, the area telephone numbers can occupy 23320000 to 23329999.

Fig: One way four 64-Kbyte segment might be positioned within the 1-Mbyteaddress space of an 8086

5FFFFH

70000H

7FFFFH

FFFFFH

PHYSICALADDRESS MEMORY

EXTRA SEGMENT BASEES=7000H

HIGHEST ADDRESS

TOP OF EXTRA SEGMENT

STACK SEGMENT BASESS = 5000H

TOP OF CODE SEGMENT

TOP OF STACK SEGMENT

CODE SEGMENT BASECS=348AH

TOP OF DATA SEGMENT

BOTTOM OF DATA SEGMENT

64K

64K

64K

64K

50000H

4489FH

348A0H

2FFFFH

20000H

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