SESSION 1

ADVANCED POWER SEMICONDUCTORS

Degraded Blocking Performance of 4H-SiC Rectifiers under High dV/dt Conditions

Sponsored by: DARPA

P. A. Losee, L. Zhu, T. P. Chow, I. B. Bhat and R. J. Gutmann

D1.1

20052005

Device Description

Experimental Results

Motivation•Study the blocking performance of 4H-SiC rectifiers under fast dV/dt, pulsed conditions

Static and pulsed breakdown of in-house Schottky rectifier

(Area=4x10-4cm-2,IL taken at midpoint of 2μs pulse)

High Voltage Pulse Testing Setup

Summary and Future Work

-4

-3

-2

-1

0

1

-5 0 5 10 15 20 25 30 35Time (us)

IL (m

A)

100°C 75°C 25°C

T

-500

-400

-300

-200

-100

0-5 0 5 10 15 20 25 30 35

Time (us)

VR

(Vol

ts)

0

5

10

15

20

0 200 400 600VR (Volts)

Leak

age

Cur

rent

(mA)

Curve Tracer Measurement

Floor of Pulsed Measurement

100°C

75°C

25°C

T

Simulation Results

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

P- JTE

OxideAnode

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

P- JTE

OxideAnode

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

Oxide

P+ (Aluminum)

Anode

P+ (Boron)

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

Oxide

P+ (Aluminum)

Anode

P+ (Boron)

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

Oxide

P+ Anode (Boron)

P+ Anode (Aluminum)

N- Drift Layer

N+ Substrate

Cathode

P- JTE(Boron)

Oxide

P+ Anode (Boron)

P+ Anode (Aluminum)

4H-SiC Schottky 4H-SiC pin 4H-SiC Junction Barrier Schottky (JBS)

•Co-fabricated Schottky, pin and JBS (same chip)

•JBS and pin have Aluminum/Carbon/Boron co-implanted anode with NA 1x1019cm-3 (Box profile, xj=0.8μm)

•1600°C, 5min, Argon activation anneal

•30μm single-zone JTE (Boron) with 5μm field plate over 0.8μm field oxide

•WD=12μm, ND=8x1015cm-3

PVM-4210 High Voltage

Pulse Generator Module (DEI Inc.)

Pulse/Function Generator

DC Power Supply

Oscilloscope

Probe Station(shielded box)

2*

3*

*2,3 SHV connectors

+HV Out

-HV Out

HV Adjust

GND

P5200 High Voltage

Differential Probe

RPOT 0-50KΩ

RPOT

DUT

Chuck*

*MetalizedSapphire Wafer

t

VR

tVTTL

Tektronix Current Probe

PVM-4210 High Voltage

Pulse Generator Module (DEI Inc.)

PVM-4210 High Voltage

Pulse Generator Module (DEI Inc.)

Pulse/Function Generator

Pulse/Function Generator

DC Power Supply

Oscilloscope

Probe Station(shielded box)

2*2*

3*3*

*2,3 SHV connectors

+HV Out

-HV Out

HV Adjust

GND

P5200 High Voltage

Differential Probe

RPOT 0-50KΩ

RPOT

DUTDUT

Chuck*

*MetalizedSapphire Wafer

t

VR

t

VR

t

VR

tVTTL tVTTL

Tektronix Current Probe

•Reverse pulse voltage to >1kV

•Fast dV/dt signal up to 25V/ns

•Output signal follows digital signal generator giving variable pulse width from 50ns to dc using same setup

•Curve tracer and pulsed reverse characteristics of in-house diodes and commercial 600V 4H-SiC Schottky rectifiers

0

0.25

0.5

0.75

1

0 500 1000 1500

Reverse Voltage, V R (Volts)

IL

(mAmps)

pinSchottkyJBS (4um, 2um)

Area=4x10-4cm2Le

akag

e C

urre

nt (m

A)

0

0.02

0.04

0.06

0.08

0.1

0 100 200 300 400 500 600 700 800 900

Reverse Voltage, VR (Volts)

Leak

age

Cur

rent

(mA)

Curve Tracer Blocking Measurements

Commercial 600V 4H-SiC Schottky rectifierIn-house 4H-SiC Schottky, pin, and JBS rectifiers

High dV/dt Pulse Blocking Measurements

-1200

-1000

-800

-600

-400

-200

0-0.5 0 0.5 1 1.5 2 2.5

Time (us)

VR

(Vol

ts)

-20-15-10

-505

101520

-0.5 0 0.5 1 1.5 2 2.5

Time (us)

IL (m

A)

-1200

-1000

-800

-600

-400

-200

0-0.5 0 0.5 1 1.5 2 2.5

Time (us)

VR

(Vol

ts)

-20-15-10

-505

101520

-0.5 0 0.5 1 1.5 2 2.5

Time (us)

IL (m

A)

-500

-400

-300

-200

-100

0-0.5 0 0.5 1 1.5 2 2.5

Time (us)

VR

(Vol

ts)

-20-15-10

-505

101520

-0.5 0 0.5 1 1.5 2 2.5

Time (us)

IL (m

A)

-500

-400

-300

-200

-100

0-0.5 0 0.5 1 1.5 2 2.5

Time (us)

VR

(Vol

ts)

-20-15-10

-505

101520

-0.5 0 0.5 1 1.5 2 2.5

Time (us)

IL (m

A)

-700

-600

-500

-400

-300

-200

-100

0-5 0 5 10 15

Time (μs)

VR

(Vol

ts)

-5

-4

-3

-2

-1

0

1

2

3

4

5

-5 0 5 10 15IL (m

A)

-700

-600

-500

-400

-300

-200

-100

0-5 0 5 10 15

Time (μs)

VR

(Vol

ts)

-5

-4

-3

-2

-1

0

1

2

3

4

5

-5 0 5 10 15IL (m

A)

Pulsed blocking of in-house JBS rectifierTop – Reverse voltage pulse

Bottom – Measured leakage current (Area=4x10-4cm-2)

Pulsed blocking of in-house Schottky rectifierTop – Reverse voltage pulse

Bottom – Measured leakage current (Area=4x10-4cm-2)

Pulsed blocking of commercial Schottky rectifierTop – Reverse voltage pulse

Bottom – Measured leakage current

Elevated Temperature Pulse Blocking Measurements

Pulsed blocking of Schottky rectifierTop – Reverse voltage pulse

Bottom- Leakage current at elevated temperature

•In-house 4H-SiC Schottky rectifiers exhibit premature breakdown under reverse pulse blocking

•Leakage currents as much as 103

times lager than their dc values are observed with Schottky rectifiers

•In-house 4H-SiC pin and JBS rectifiers safely block over 1kV reverse pulse voltage

•600V commercial 4H-SiC Schottky rectifiers do not show pulsed failure until the reverse voltage exceeds their specified product rating

•Time constants as long as >10μs have been recorded as Schottky leakage currents relax back to their static values

•Increased acceptor ionization and faster emission from deep levels result in reduced pulsed leakage currents and faster relaxation at elevated temperatures

Simulated potential contours and electric field profile for (left) JBS and (right) Schottky Rectifiers

VR (JBS) = 1kV, VR (Schottky) = 400V

•Assume that tramp is much less than emission time from contributing acceptor or trap level (Boron JTE region modeled as intrinsic-like)

•Aluminum modeled with as-implanted concentration and associated electrical ionization

•BV > 1kV for JBS and pin rectifiers

•BV ~ 0.7kV for 4H-SiC Schottky rectifiers

•Schottky rectifiers exhibit large electric fields at the contacts at lower voltages

•Despite having identical termination designs, Schottky rectifiers (without aluminum implantations shielding the contact edges) show premature failure under reverse pulse conditions

•Using elevated temperature transient response and numerical simulations, we show further evidence that deep acceptor levels or associated trap states are limiting the pulse blocking performance of in-house 4H-SiC Schottky rectifiers

•The low-temperature pulse blocking characteristics of the rectifiers will be measured

•The pulse testing setup will be expanded to measure higher voltages to characterize up to 10kV designs

AcknowledgementThis work was primarily supported by DARPA under contract number #DAAD19-02-1-0246 and made use of shared facilities of the National

Science Foundation under Award Number EEC-9731677. 1

Novel High Voltage 4H-SiC Schottky Rectifiers

Sponsored by: CPES, ARMY CTA

Lin Zhu, Peter Losee and T. Paul Chow

D1.2

20052005

MotivationImprove performance for 4H-SiC Schottky rectifiers

• LC-JBS rectifiers with WS from 4 to 6μm show less than 1.8V forward drop at 100A/cm2

• PiN-like reverse leakage characteristics have been achieved for optimized LC-JBS rectifiers, having more than 109 on/off current ratio

• The design trade-offs between forward drop and reverse leakage current have been quantified

• 4H-SiC LC-JBS rectifiers exhibit ~50% reduction of junction capacitance and ~60% increase of cut-off frequency

Future WorkFurther optimize LC-JBS rectifier to improve the trade-off between forward drop vs. leakage current

Further study of novel structures using charge balance techniques

P N

N+

Schottky

Experimental Results

Schematic of the MeV ion implantation facility

Trade off between Specific on-resistance and breakdown voltage

• SiC superjunction Schottky rectifiers can achieve better performance than conventional Schottky rectifiers due to the non-planar 3D electric field shaping

• Advantage of the superjunction approach will be more significant with scale-down of pillar width

LC-JBS rectifier structure Superjunction rectifier structure

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+02 1.E+03 1.E+04 1.E+05Breakdown Voltage (V)

Ron,

sp ( Ω

.cm

2 )

Conventional limit

SJS S=3um

SJS S=2um

SJS S=1um

PN channel

N drift-region

N+

Oxide

W /2s

W /2O Tepi

Schottky

Cathode

0.E+00

1.E-11

2.E-11

3.E-11

4.E-11

5.E-11

6.E-11

0 2 4 6 8 10Reverse Bias (V)

Cap

acita

nce

(F)

SchottkyLCJBS(3,3)LCJBS(4,4)LCJBS(5,5)

Area=6.25x10-4cm-2

LC-JBS Rectifier Superjunction Rectifier

•Low leakage current

•Relatively higher specific on-resistance•Require epi-regrowth

•Low specific on-resistance

•Complicate fabrication process•High leakage current

Simulation Results

Advantage: Advantage:

Disadvantages: Disadvantages:

Forward Characteristics of LC-JBS rectifiers

Reverse Characteristics of LC-JBS rectifiers

Trade-offs between forward drop and leakage current

of LC-JBS rectifiers

C-V Characteristics of LC-JBS rectifiers

Process Options

fT(Schottky)=134MHzfT(LC-JBS 355)=222MHzfT(LC-JBS 344)=197MHz

• Conventional superjunction structure is formed by multiple implantation-epi regrowth technique

• Using MeV ion implantation to form superjunction can reduce the complexity of fabrication

2

High-Voltage Injection-Enhanced 4H-SiC N-Channel IGBTs with Forward Drop approaching

that of a PiN Junction Rectifier

Sponsored by: DARPA

Lin Zhu and T. Paul Chow

D1.3

20052005

MotivationImprove performance for 4H-SiC IGBTs by optimizing the device design and structure

Future WorkExperimental demonstration of 4H-SiC IGBTs with injection enhancement

• With proper design of the D/W ratio and the injection efficiency from the anode, symmetric carriers distribution throughout the drift region can be achieved. By doing so, the IGBTs can achieve a forward drop close to a PiN rectifier of the same blocking voltage.

• Efficient charge extraction during turn-off can be achieved with sufficiently high emitter transparencies.

• The simulated trade-offs between Vce(sat) and Eoffare shown on right, indicating that this new device structure can achieve much better trade-offs than conventional SiC IGBTs.

Schematic cross-section of proposed IGBT structure

Carrier distribution in the drift region during forward conduction with

different trench depths

Forward Conduction Simulations

N-buffer

Cathode

Anode

N-drift150 m2x10 cm

μ14 -3

P-baseN+ P+

P-emitter

W/2

D

Device Structure

1.E+15

1.E+16

1.E+17

0 50 100 150

Drift region distance(um)

Car

rier C

onc.

(cm

-3)

D=5umD=10umD=20um

15kV N-channel IGBT

Taun=10usW=1um

1.E+15

1.E+16

1.E+17

0 50 100 150Drift region distance(um)

Car

rier C

onc.

(cm

-3)

W=1umW=3umW=5um

15kV N-channel IGBT

Taun=10usD=10um

0

20

40

60

80

100

120

0.0E+00 2.0E-07 4.0E-07 6.0E-07 8.0E-07 1.0E-06Time (s)

Cur

rent

Den

sity

(A/c

m2 )

taun=1ustaun=10ustaun=100us

W=1umD=10umVa=10kV

Switching SimulationsForward conduction simulation with different design parameters

Carrier distribution in the drift region during forward conduction with

different mesa widths

Simulated turn-off waveform of the proposed IGBT

Design trade-off between Vce and Eoff

3

Design and Implementation of GaN MOS-Gated Bi-Directional Switch

Sponsored by: CPES

W. Huang, T. Khan, T.P. Chow

T1.1

20052005

Why GaN ? • Silicon power devices cannot operate properly when the temperature exceeds 200 oC

• GaN is suitable for high temperature, high power applications due to its wide band gap and large critical electric field

• GaN power devices can be integrated with optoelectronics and microwave components and can be grown on silicon substrates

Device Structure• Lateral, self-aligned, accumulation-mode GaN MOSFETs in series with Schottky/JBS rectifiers is shown below

• AlGaN layer is used for the suppression of back-channel at GaN/Sapphire interface

• For simulations, doping of n-GaN = 9x1017 cm-3; thickness of n-GaN = 0.1 µm & the polarization charge density A –1×1013cm-2 at GaN/AlGaN interface is assumed

Device Simulation• Forward breakdown voltage is at 725V and Reverse breakdown voltage is at 1007V

• Specific on-resistance of 8.6mΩ⋅cm2 at VGS=30V is projected

Equipotential Lines & Surface Field at Forward Blocking 725V

Equipotential Lines & Surface Field at Reverse Blocking 1007V

0.0E +00

1.0E -05

2.0E -05

3.0E -05

4.0E -05

5.0E -05

6.0E -05

7.0E -05

8.0E -05

9.0E -05

0 10 20 30 40 50Drain V oltage(V)

Dra

in C

urre

nt(A

/um

)

VG =-10V(M edic i)VG =0V(M edic i)VG =10V(M edic i)VG =20V(M edic i)VG =30V(M edic i)VG =-10V(Saber)VG =0V(Saber)VG =10V(S aber)VG =20V(S aber)VG =30V(S aber)

Incr. G ate vo ltage

0.0E+00

2.0E-11

4.0E-11

6.0E-11

8.0E-11

1.0E-10

1.2E-10

-12 -10 -8 -6 -4 -2 0 2 4 6 8Gate Voltage (V)

Cap

acita

nce

(F)

1kHz2kHz3kHz6kHz10kHz20kHz30kHz60kHz100kHz200kHz300kHz600kHz1MHz

1 MHz

1 kHz

0.0E+00

2.0E-11

4.0E-11

6.0E-11

8.0E-11

1.0E-10

1.2E-10

-12 -10 -8 -6 -4 -2 0 2 4 6 8

Gate Voltage (V)

Capa

cita

nce

(F)

25C50C75C100C125C

25 C 125 C

0

0.2

0.4

0.6

0.8

1

1.2

-10 -5 0 5 10 15 20

Gate Voltage (V)

Cap

acita

nce

(F)

Calculated

Measured

UV

Forw ard w /o UV

Ideal

Reversew / UV

1.0E-13

1.0E-12

1.0E-11

1.0E-10

1.0E-09

1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07w (1/s)

Gp/

w (S

s/cm

2)

0 V-1 V-2 V-3 V-4 V

y = -7E+09x + 2E+11

-8E+11

-7E+11

-6E+11

-5E+11

-4E+11

-3E+11

-2E+11

-1E+11

0

1E+110 25 50 75 100 125 150

Temperature (C)

Pola

rizat

ion

char

ge (q

/cm

2)

Summary• Lateral, self-aligned, accumulation-mode GaN MOSFETs in series with Schottky/JBS rectifiers on the sapphire substrate was designed and optimized

• A extremely low interface charge density at GaN/oxide interface was obtained

• Pyroelectric voltage coefficient of 1.3×105 V/m-K was estimated as compared to our previous result of 7×104 V/m-K

Future Work• Completion of the first lot of bi-directional blocking device

• Demonstrate n & p channel inversion-mode GaN MOSFETs

Output Characteristics using Medici and saber• Comparison of Saber device model and numerical (Medici) simulation

Evaluation of gate insulator for GaN MOS capacitors and FETs• C-V and G-ω characteristics of GaN MOS capacitor at room temperature are shown below

•MOS capacitor parameters: Area=1.96×10-3cm2; ND=4×1016cm-3; tox=61.5nm; ΦB=1.58 eV; CFB/Cox=0.89; CFB=98 pF

• C-V curves show a near zero frequency dispersion, while the observed Gp/ωvalue is small and shows no bell-like peak

A peak interface charge density of 6×1011cm-2eV-1 is observed 0.16eV below conduction band which decreases to 9×109cm-2 eV-1 as we go towards the middle of the bandgap, much lower than our previous experimental results

UV induced flatband voltage shift indicates a net interface charge of –2×1012q/cm2

An increase in flatband voltage is observed with an increase in the temperature (shown below), indicating a net reduction in Qtotal, which we attribute to the increase in the Polarization charge

Polarization charge temperature dependence is also shown below, indicating a Pyroelectric voltage coefficient of 1.3×105 V/m-K

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8Ec-E (eV)

Dit

(/cm

2-eV

)

25C75C125CDit frm C_V

4

20052005

Sponsored by: CPES

K. R. Varadarajan and T. P. Chow

T1.2

Develop 30V-80V integrable Si Lateral Trench Power MOSFETs with low gate charge and low specific-on-resistance for Power IC applications

Objective

Novel Lateral Trench Power MOSFET with a reduced Gate-to-Drain

capacitanceSynchronous Buck-type DC-DC Converter

Q1 : Control Switch

Q2 : Synchronous Rectifier

Features

• Gate and Drain are formed in different trenches, separated by the source formed on the mesa. This reduces the Gate-to-Drain capacitance significantly.

• Further reduction can be brought about by having a thicker oxide at the gate trench bottom.

• The voltage rating of the device can be varied by varying the oxide spacer between the mesa and the drain plug.

• Compatible with a Trench CMOS process, without significant additional processing steps.

SEM cross-sections of the device

Present Status and Future Work• Completed fabrication of the first lot of devices.• Optimize the device design and fabrication process based on the results from the first lot of devices.

Design and Fabrication of Low Voltage Silicon Lateral Trench Power MOSFETs for

High Efficiency DC/DC Converters

N+

Source Drain Source

N+

N+

N - epi

P -base

P-substrate

P -base

P+ P+

Substrate

Gate Gate

Oxide spacer formation in the drain trench

Cross-section of the fabricated device

GateSource

Oxide Spacer

DrainGate

SourceOxide Spacer

Drain

Device Simulation ResultsDevice Fabrication Process Flow

Thermal oxidation followed by gate trench etch

Oxide deposition followed by patterned drain trench etch

Multi-step oxide deposition/etch to form the spacer

N-plus drain formation followed by polysilicon drain plug

LOCOS oxidation at the trench bottom followed by gate oxidation

and polysilicon deposition

Two level metallization (Al) to form gate, source and drain pads

Equipotential and Impact ionization plots for the 80V device at breakdown

Key Performance metrics

Starting Material : n-epi on p-substrate, Epi doping : 1e16/cm3, Epi thickness= 2 μm

Process details:• Gate oxide thickness = 75 nm.• Gate trench depth = 1.2 μm • Drain trench depth = 1.0 μm • 9 levels of masking used• Minimum feature size = 0.5 μm

Key Process Features

The oxide spacer is formed by a plasma TEOS deposition process. Thicker spacers (1um, 2um) are formed by a multi-step deposition/etch process.

Breakdown Voltage (V)

Ron-sp(m Ω -cm2)(@VGS=15V)

Qg

(nC-cm2)FoM

(mΩ-nC)

55 0.62 265 165

80 1.15 195 225

35 0.38 305 116

Commercial Benchmarking*

Fairchild IR

120

345

368

322

402

97

* From Commercial data sheets

Breakdown Voltage (V)

Ron-sp(m Ω -cm2)(@VGS=15V)

Qg

(nC-cm2)FoM

(mΩ-nC)

55 0.62 265 165

80 1.15 195 225

35 0.38 305 116

Commercial Benchmarking*

Fairchild IR

120

345

368

322

402

97

* From Commercial data sheets

Experimental Results • Threshold voltage of the device is about 5V.• Good gate control observed beyond threshold voltage

while in forward conduction. • Breakdown voltage of the device is about 8V, limited by

punchthrough of the p-body region.• High levels of leakage current observed possibly due to

non-isolation of the devices.

5

Scalable Power Semiconductor Switch (SPSS)

Hongfang Wang, Alex Q. Huang, Fred Wang

NP1.1

20052005

Project ObjectiveProject Objective: Develop a new power semiconductor switch with scalability in terms of voltage, current and frequency for high power converter application.

p

n

o

Control I/O

Gate Drive

Power supply

Static balance

Dynamic balance

Control I/O

Gate Drive

Power supply

Static balance

Dynamic balance

p

SPSS

n

o Optically controlled three terminal devicewith scalable V, I, f

SPSS Principle

Key characteristics:Key characteristics:Scalable V, I and fthree terminal optical controlled device

Applications:Applications:HVDC transmissionDistributed power systemElectric motor driveEnergy storage systemFACTs

10 pulses, 15 kHz Burst Mode Operation Voltage balance during the SPSS turn-off

Bus Voltage: 2000VTurn Off Current: 300A

Transient waveform

Vce1,Vce2,Vce3,Vce4

ic

Drive power supply

Vce

(4800V, 300A, 10 kHz SPSS)

Present Series IGBT TechniquesPresent Series IGBT Techniques: : -- on the Device Side

Passive SnubberZener Voltage ClampActive Voltage Clamp

-- on the Gate Sidedv/dt control during turn offReference ramp voltage approachActive Gate Control

Proposed approach:Proposed approach:Combine the device side and gate side togetherVoltage control current sourceBuilt-in gate drive supplyOptical gate signal commutation

6

Current Sharing of Power MOSFETs Paralleling Operation

Hongfang Wang, Fred Wang

NP1.2

20052005

Objectives: Objectives: investigate the current sharing of investigate the current sharing of power MOSFETs paralleling operation for higher power MOSFETs paralleling operation for higher power output; static and dynamic current power output; static and dynamic current balance issues due to the device parameters balance issues due to the device parameters mismatch.mismatch.

BeforeUse active gate control to achieve current balance

Power MOSFETs parallel dynamic current unbalance map

Power MOSFETs parallel steady state current unbalance

Test setup (power MOSFET 600V/73A)

300V

300V

Vgs1

Vgs1

Id1

Id1

Id2

Id2

turn on

turn off

20A/div

20A/div

Id1300V

Vgs1

300V

Vgs1

Id1

Id2

Id2

turn on

turn off

20A/div

20A/div

Sponsored by: Army Research Laboratory

After

During conduction period, the Rds(on) mismatch causes current unbalance.

transconductance mismatch

threshold voltage mismatch

Parasitic inductance,capacitance mismatch

The current unbalance due to the transconductance, threshold voltage etc mismatch can be solved using active gate control. 7

Power Device Selection for Three Phase High Power Density Converter

Sponsored by: Boeing Inc.

Hongfang Wang, Fred Wang

NP1.3

20052005

MotivationMotivation: to develop the design guideline for power devices three-phase high power density converter application.

Define the IGBT power module high power density Figure-of-Merit:

( ) 2/1,,,,, )/(1 DpackDthspacksthrrDvoffonv ARARKKKKKPDFOM +=

Different package candidatesSingle switch Dual switch Half bridge

The total power module loss = IGBT power loss + Diode power loss

AC ACFor the three phase high power converter the IGBT module(1200V/800A) are selected as an example.

8

New Unipolar Power Device Figure-of-Merit for High Power Density Application

Hongfang Wang, Fred Wang

NP1.4

20052005

Define:

MotivationMotivation: to develop the design guideline for unipolar power device high power density converter application.

Switching waveforms of a generic Switching waveforms of a generic unipolar power deviceunipolar power device

Qth Qgs1 Qgd Qov

Qg

ID

VD

Charge Time

Voltage or Current

td tr tf tov

)/(}/)(4{ ,4/3

min, μcavgDDBrmsloss EifkIVVIP =

chipth

dieth A

WRσ

=

thcavgDDBrmschip E

ifkIVVIATσμ 2,

4/34/7max

1}/8{=Δ

thcm EPDFOM σμ 2=

To compare the relative advantages of different semiconductor materials in converter applications

Define:

To compare the relative advantages of the same semiconductor power devices in converter applications

packthgdond ARQR

PDFOM 1=

Sponsored by: Army Research Laboratory

9