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Semicon2012 Keynote - FPGAs Xilinx
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© Copyright 2012 Xilinx
Ivo Bolsens,Senior Vice President & CTO
All Programmable: from Silicon to System
Page 1
Moore’s Law: The Technology Pipeline
Page 2 © Copyright 2012 Xilinx
Industry Debates Variability
Page 3 © Copyright 2012 Xilinx
Industry Debates on Cost
Page 4 © Copyright 2012 Xilinx
Nothing New: Power Challenge
Page 5 © Copyright 2012 Xilinx
Source: Intel
MultiMulti--CoreCore
ESL DesignESL Design FlowFlowIP IP ReRe--UseUse
Nothing New: Productivity Gap
Source: SEMATECH
Page 6 © Copyright 2012 Xilinx
Page 7
Nothing New: I/O Bandwidth Gap
© Copyright 2012 Xilinx
Source: Xilinx, Inc.
MultiMulti--GigabitGigabitSerDesSerDes
“Doubt is not an agreeable condition,
but certainty is absurd.”
François-Marie Arouet de Voltaire,
French Philosopher
Page 8 © Copyright 2012 Xilinx
Photo Source: Wikipedia
“Don’t believe everything you read on
the Internet.”
Abraham Lincoln,
U.S. President
Page 9 © Copyright 2012 Xilinx
Photo Source: Wikipedia
Page 10 © Copyright 2012 Xilinx
Add Value : Programmable System Integration
–Programmability
–3D Integration
Collaborate
–Supply Chain
• Wider – more Complexity
• Deeper – earlier Engagement
–From System to Silicon
Extending and Leveraging Moore’s Law
Partial Reconfiguration
–Time-multiplexing hardware
Lower Power
Value of Programmability: Configurability
Page 11 © Copyright 2012 Xilinx
Value of Programmability: I/O
Page 12 © Copyright 2012 Xilinx
6.6Gb/s
28.05Gb/s
13.1Gb/s
12.5 Gb/s
Quad B Ch 1 TX
Quad A Ch 0/1/2/3 TX
Optical
SFP+ Test Board
Quad A Ch 1 RX
Quad B Ch 0/1/2/3 RX
Quad B Ch 0/2/3 TX
Quad A Ch 0/2/3 RX
Backplane
Value of Programmability: GOPS/Watt
Page 13
AcceleratorAccelerator Accelerator
Interface
AXI_DMA
m m
s
AXI_DMA
m m
s
s s
AXI4 LITE interconnect
s sm
ACP
256 KB On-Chip Memory
Snoop Control Unit (SCU)
DMA Configuration
512 KB L2 Cache
Timers / Counters
General Interrupt Controller
Cortex™-A9 MP Core™
32/32 KB I/D Caches
NEON™/FPU Engine
Cortex™-A9 MP Core™
32/32 KB I/D Caches
NEON™/FPU Engine
ARM® CoreSight™ Multi-core & Trace Debug
AMBA® Switches
© Copyright 2012 Xilinx
From 100 Watt to 2 Watt
10x Performance Acceleration
Future Challenge: HW + SW co-design
Page 14
FPGA
Vid
eo co
dec
Encryp
tion
Packe
tP
roce
ssing
FF
T
Searc
h
Application-Specific
ARM Processor
A9 A9
HW-SW Integration
Commercial Software
Ecosystem
OpenCL
C
Compile / Debug
C-HLS
Accelerator synth
© Copyright 2012 Xilinx
Exploit Parallelism and Heterogeneity
3D Integration: Add Value
Page 15 © Copyright 2012 Xilinx
Value of 3D Integration: Bandwidth/Watt
Page 16
1x
10x
100x
Total Die-to-Die Connections
10x 100x 1,000x
BW
/ W
att
SerDes &
Standard I/O
3D
Interconnect
100x bandwidth/watt advantage over conventional methods
© Copyright 2012 Xilinx
Value of 3D Integration: Cost/Gate
Page 17
Big Single Monolithic Die Multiple Small Die Slices
Greater capacity, faster yield ramp
Area
Die
Co
st
Value of 3D Integration: Heterogeneous ICs
Page 18
Mixed functionsMemoryMemory
AnalogAnalog ProcessorProcessor
MemoryMemory
LogicLogic PLDPLD
Mixed processes
© Copyright 2012 Xilinx
Highest bandwidth FPGA with 2.78 Tb/s
serial connectivity
Electrically-isolated 28G transceivers for optimal signal integrity
Value of 3D Integration: Heterogeneous ICs
Different silicon
processes
Passive interposer
Homogeneous
digital logic
Noise isolation
28GTransceivers
28GTransceivers
13G
Transceivers
Page 19 © Copyright 2012 Xilinx
Page 20
Value of 3D Integration: Lower Power
Silicon Interposerwith 28nm FPGA Slices
28 nm FPGA Slice
28 nm FPGA Slice
28 nm FPGA Slice
28 nm FPGA Slice
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
0 500 1000 1500 2000
Ma
x S
tati
c P
ow
er
LCs/1000
Virtex-7 Multi-Slice
-Virtex-7 Monolithic
Slow Fast
A B C
Very Leaky
D
7 Series Static Power vs. Logic Cellsat Tj=85C and Max Process
© Copyright 2012 Xilinx
Improve Cost
– Wafer backside processing is complicated
– “Device quality” wafers used for interposers
– KGD methodologies still emerging
Scalability
– Micro-bump scaling is limited
– Super-sized interposers.
– Improve TSV aspect ratio
Design Support
– Multi-die analysis without Multi-mode
Multi-corner explosion
– Thermal modeling based on vertical hotspots
Page 21
3D Integration: Challenges Ahead
© Copyright 2012 Xilinx
Page 22
3D Integration: Industry Call-to-Action
© Copyright 2012 Xilinx
Design Enablement Manufacturing Standards
� Models
� 3D Process Development Kit
� DFM rules for TSV, µ-bump
� Materials TSV, µ-bump
� Thermal budget
Test
� Test HW
� Known-good-die method
� µ-bump probing
� Burn-in bare die
� Thin wafer handling
� Shipping methods
� Chip-to-chip interfaces
Interoperability of Silicon
Supply Chain Collaboration: Early Engagement
2006
28nm
Test Vehicle
Completed
90nm Process
Integration
And Modular
Development
Stacked
Silicon
Interconnect
Development
Started
65nm
Test Vehicle
Completed
90nm
Test Vehicle
Completed
Design
Tools
Available
2007 2008 2009 2010 2011 2012
Initial
Reliability
Assessment
Design
Enablement
and Supply
Chain
Validation
Process
Qualification
Design
Validation
TodayWorld’s First 3D
Stacked Silicon
Interconnect
Device
Heterogeneous
Stacked Silicon
Interconnect
Technology
Page 23 © Copyright 2012 Xilinx
3D Integration
Supply Chain Collaboration: Early Engagement
Technology
path finder
Integration
and basic
devices
Basic
elements:
RAM, RF,
Std Cell, etc.
Circuit blocks,
process-design
interactions,
pilot prep
More circuit
blocks, & later
products
20092008
TV0
2010 2011
© Copyright 2012 XilinxPage 24
TV1 TV2 TV3 TV4 TV5
28nm
starts
28nm Process Technology
Wafer Sort
Root Cause
Analysis
Yield Improvement
Advanced InAdvanced In--Line Line
InspectionInspection
FAB FPGA
Continuous, early feedback loop for initial rampingEnables accelerated learning – days vs. months
Page 25
Supply Chain Collaboration: Product Ramp Up
© Copyright 2012 Xilinx
Defect Reduction:
quick to detect defects If you can’t find it, you can’t fix it
The FPGA is a powerful yield learning vehicle with
multiple layers of programmable features
Process Control:
powerful to measure variationsIf you can’t measure it, you can’t improve it
FPGA architecture drives yield & quality improvements
Supply Chain Collaboration: Mutual Benefit
© Copyright 2012 XilinxPage 26
Supply Chain 1998 - 2010
Page 27
FAB BumpDB
Outside
In-house
Test
Bin FGMark
© Copyright 2012 Xilinx
Assy
PP
Today’s Supply Chain
Page 28 © Copyright 2012 Xilinx
FABµ
BumpDBbins
PP
Top die attach
Outside
In-house
Test
Bin FG
Std
Sort
Die
S
ep
Mark
eFuse1
eFuse2
Inter-poser
Top side proc.
Bot side proc.
BumpI-poser attach
Chip-on-Die3rd party
die
Inter-poser
3rd party
die
Top side proc.
Pkg assy
Bot side proc.
Bump
Die stack
Chip-on-Wafer
Wider and Deeper
R&D Consortia
EDA,Equipment Suppliers
From Silicon to System
Page 29
System Company
FablessVendor
Supplier
Applications SWApplications SW
System ArchitectureSystem Architecture
Product FeaturesProduct Features
Product IP/HW/SWProduct IP/HW/SW
DFMDFM
PackagePackage
WaferWafer
How to monetize SW?
How to ramp yield faster?
Who controls 3D supply chain?
Power, performance
cost, integration
© Copyright 2012 Xilinx
Conclusions
Page 30 © Copyright 2012 Xilinx
Moore’s Law:
- From mostly cost reduction to more value-based innovation
System figure of merit defines value
Xilinx programmable system integration
- Programmability
- 3D integration
Supply chain partnerships to enable
- Efficiency
- Standardization
- Innovation
Page 31
What Xilinx Makes Possible:
ALL PROGRAMMABLE
ALL Programmable Electronic Systems
ALL Programmable Technologies
ALL Programmable Devices
Follow Xilinx
Page 32 © Copyright 2012 Xilinx
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