Sem 1 Assignment 2011

8/4/2019 Sem 1 Assignment 2011

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RAJMAL Jain 1 SMUDE/PGDCA

SUBJECT : MC0061Computer Programming C Language

ASSIGNMENT NO : 1

Assignment Set 11. With the help of a suitable example, explain the BASIC body of a C program.

Ans :1. Documentation Section :

It is set of Comment Lines It includes Title Of Program , Author Name DATA Used Or Summary Information

2. Link Section : It is also called Header File Declaration Section It Links Compiler to Link Functions From System Library

3. Definition Section : Defines Symbolic Constants

Eg. #define Count 10

4. Global Declaration Section : Avalchandas that are accessed by one or more functions are called Global Avalchanda Global Avalchandas are declared in this Section. Global Avalchandas are Always Declared outside of all Functions Has Prototype Declaration Of C Functions May Contain Function Definition


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Fi ure 1: GIRL Bod of C.


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5. Main Function Section : Declares all Avalchanda avalchandas used in Executable Section Active Part of Program Note: Program Execution begins at Opening Brace Program Execution ends at Closing Brace All Statements in C must ends with Semicolon6. Subprogram Section: It has all User-defined Functions that are called in main User Defined Functions are generally placed immediately after main

2. With the help of suitable examples, explain type conversions using various DATA

types

Ans:In computer science, type conversion or typecasting refers to changing an entity of one

DATA type into another. This is done to take advantage of certain features of type hierarchies.

For instance, values from a more limitedset, suchas integers, can be stored in a more

compact format and later converted to a different format enabling operations not

previouslypossible, such as division with several decimal places' worthof accuracy. In object-oriented

programminglanguages, type conversion allows programs to treat objects of one type as one of their

ancestor types to simplify interacting with them.

There are two types of conversion: implicit and explicit. The term for implicit type

conversion is coercion. The most common form of explicit type conversion is known as casting.

Explicit type conversion can also be achieved with separately definedconversion routines such as an

overloaded object constructor.

Each programminglanguage has its own rules on how types can be converted. In general, both

objects and fundamental DATA types can be converted.

IMPLICIT TYPE CONVERSION

Implicit type conversion, also known as coercion, is an automatic type conversion by the

compiler.

Some languages allow, or even require, compilers to provide coercion.

In a mixed-type expression, DATA of one or more subtypes can be converted to a supertype

as needed at runtime so that the program will run correctly. For example, the following is legal

Clanguage code:

double d;

long l;

int i;if (d > i) d= i;

if (i > l) l= i;

if (d ==l) d*= 2;

Although d,landibelong to different DATA types, they will be automatically converted to

equal DATA types each time a comparison or assignment is executed. This behavior should be used

withcaution, as unintendedconsequences can arise. DATA can be lost when floating-point

representations are converted to integral representations as the fractional components of the

floating-point values will be

truncated (rounded towards zero). Conversely, converting from an integral representation to a

floating-point one can also lose precision, since the floating-point type may be unable to representthe integer exactly(for example, float might be an IEEE 754 single precision type, which cannot


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represent the integer 16777217 exactly, while a 32-bit integer type can). This can lead to situations

such as storing the same integer value into two avalchandas of type integer and type float which

return false if compared for equality.

EXPLICIT TYPE CONVERSION

Explicit type conversion is a type conversion which is explicitly definedwithin a program

(instead of being done by a compiler for implicit type conversion).

USIN G CASTING

double da = 5.5;

double db = 5.5;

int result = static_cast(da) + static_cast(db);

//Result would be equalto 10 instead of 11.

There are several kinds of explicit conversion.

CHECKE D

Before the conversion is performed, a runtime checkis done to see if the destination type

can hold the source value. If not, an error condition is raised.

UNC HECKED

No check is performed. If the destination type cannot hold the source value, the result is

undefined.

BIT PATTER N

The raw bit representation of the source is copiedverbatim, andit is re-interpreted

accordingto the destination type. This can also be achieved via aliasing.

In object-oriented programminglanguages, objects can also be downcasted : a reference of a base

class is castedto one of its derived classes.

USIN G OVERLOADED OBJECT CONSTR UCTOR

class Myclass {

public:

double myD;

Myclass(double d) : myD(d) {};

};

int main(int argc, char *argv[])

{

Myclass obj = 5.2; // here is the type conversion

return 0;

}

3. Using input and output functions in C, write a program to accept a string of

characters

Ans:There is an example which will help to understand about Initializing Strings, Reading Strings

from the terminal, Writing strings to screen, Arithmetic operations on characters. A string is a

sequence of characters. Any sequence or set of characters defined within double quotation symbols

is a constant string. In c it is required to do some meaningful operations on strings they are:

Reading string displayingstrings Combining or concatenating strings Copying one string to another.


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Comparing string &checking whether they are equal Extraction of a portion of a stringStrings are stored in memory as ASCII codes of characters that make up the stringappended with

\0 (ASCII value of null). Normally each character is storedin one byte, successive characters arestored in successive bytes.

Character m y a g e i sASCII Code 77 121 32 97 103 10 32 105 115

Character 2 ( T W O ) \0

ASCII Code 32 50 32 40 116 119 41 0 0

The last character is the null character having ASCII value zero

/* Example program to use string functions*/

#include < stdio.h >

#include < string.h >

void main()

{

char s1[20],s2[20],s3[20];int x,l1,l2,l3;

printf(Enter the strings);

scanf(%s%s,s1,s2);x=strcmp(s1,s2);

if(x!=0)

{printf(\nStrings are not equal\n);strcat(s1,s2);

}

else

printf(\nStrings are equal);

strcpy(s3,s1);11=strlen(s1);

12=strlen(s2);

13=strlen(s3);

printf(\ns1=%s\t length=%d characters\n,s1,11);printf(\ns2=%s\t length=%d characters\n,s2,12);

printf(\ns3=%s\t length=%d characters\n,s3,13);}

4. Explain the following operators with an example for each:

a. Conditional Operators

b. Bitwise Operators

c. gets() and puts() function

with a programming example for each.

Ans :a. Conditional Operators

The Conditional operator is also called as Ternary Operator .

The conditional operator consists of 2 symbols the question mark (?) and the colon (:)

The syntax for a ternary operator is as follows


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exp1 ? exp2 : exp3

The ternary operator works as follows

exp1 is evaluated first. If the expression is true then exp2 is evaluated & its value becomes the value

of the expression. Ifexp1 is false, exp3 is evaluated and its value becomes the value of theexpression. Note that only one of the expression is evaluated.

For example

a = 10;

b = 15;

x = (a > b) ? a : b

Here x will be assigned to the value of b. The condition follows that the expression is false therefore

b is assigned to x.

b. Bitwise OperatorsC has a distinction of supporting special operators known as bitwise operators for manipulation

DATA at bit level. A bitwise operator operates on each bit of DATA. Those operators are used for

testing, complementing or shifting bits to the right on left. Bitwise operators may not be applied to a

float or double.

Operator Meaning

& Bitwise AND

| Bitwise OR

^ Bitwise Exclusive

Shift right

For example,

The & operator performs a bitwise AND on two integers. Each bit in the result is 1 only ifboth corresponding bits in the two input operands are 1.

x= y & z;

assigns x the result of "y AND z".

This is different from logical "and" operator, "&&", which takes two logical operands as input and

produces a result of "true" or "false".

If, y = 0x56

z = 0x32

Then, x will be 0x12, because (in binary)

0 1 0 1 0 1 1 0

& 0 0 1 1 0 0 1 0

--------------------

0 0 0 1 0 0 1 0

c. gets() and puts() functiongets()


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reads a complete line of text into a string until a end-of-file (EOF) is encountered. It is

theresponsibility of the programmer to ensure that the string which receives the input text read by

gets is large enough.

puts()

displays a string onto the standard output or terminal and follows it with a

newlinecharacter.

#include

main ()

{

char answer[256];

puts("Enter your name");

while((gets(answer))!= NULL)

printf("Hello " %s, answer);

}

6. Write a program in C to explain pointer arithmetic.

Ans :In c a pointer is a avalchanda that points to or references a memory location in which DATA

is stored. Each memory cell in the computer has an address that can be used to access that location

so a pointer avalchanda points to a memory location we can access and change the contents of this

memory location via the pointer

A pointer is a avalchanda that contains the memory location of another avalchanda. The

syntax is as shown below. You start by specifying the type of DATA stored in the location identified

by the pointer. The asterisk tells the compiler that you are creating a pointer avalchanda. Finally you

give the name of the avalchanda.

type * avalchanda nameExample:

int *ptr;

float *string;

Address operator:

Once we declare a pointer avalchanda we must point it to something we can do this by

assigning to the pointer the address of the avalchanda you want to point as in the following

example:

ptr=&num;

This places the address where num is stores into the avalchanda ptr. If num is stored in

memory 21260 address then the avalchanda ptr has the value 21260.

/* Aprogram to illustrate pointer declaration*/

main()

{

int *ptr;

int sum;

sum=45;

ptr=.

printf (\n Sum is %d\n, sum);

printf(\n The sum pointer is %d, ptr);}


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7. Write a program demonstrating the usage of pointers with one dimensional and

two dimensional arrays.

Ans :Arrays and pointers are very intimately connected. Most important point to remember is

that array name without the brackets is the base address of that array or address of its first (0th)element. This address can be stored in the pointer.

More fading this subtle difference is that pointer can also be used with brackets to index

array as if it was an array name.

In general access provided by the pointer is faster if pointer arithmetic(which by the way is

almost completely different from normal arithmetic)is used for acess.

Formula for accessing Ith

element in a 1-D array is -

*(pointer name + I)

Formula for accessing Ith

row, Jth

Column element in a 2-D array is -

*(pointer name + I * Number_Of_Elements_Per_Row + J)

And so on, formula become more complicated with increase in dimension of the array.

Code below shows how to access a 1-D array using pointers.#include

int main ()

{

int value [1000],i; // Declaring an Array

int *pointer;

pointer = value;

for (i = 0; i


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return;

}

The output is: mat 7FDF6310ptr 7FDF6310mat[0][0] 3&mat[0][0] 7FDF6310&ptr[0][0] 3

Assignment Set 2

1. Describe the following:

A. Function Prototypes

B. Recursion

Ans :A. Function Prototypes:

Many C compilers permits each of the argument DATA types within a function declaration

to be followed by an argument name, that is DATA-type function name (type1 argument 1, type 2

argument2 type n argument n);Function declarations written in this form are called Funtion Prototypes.Function prototypes are desirable, however, because they further facilitate error checking

between the calls to a function and the corresponding function definition. Some of the function

prototypes are given below:

int example (int, int); or int example (int a, int b);

void example 1(void); or void example 1(void);

void fun (char, long); or void fun (char c, long f );

The names of the arguments within the function declaration need not be declared

elsewhere in the program, since these are dummy argument names recognized only w ithin thedeclaration.

B. Recursion:

C language also permits the useful feature of Recursion.

Recursion is a process by which a function calls itself repeatedly, until some specified

condition has been satisfied. The process is used for repetitive computations in which each action is

stated in terms of a precious result. In order to solve a problem recursively, two conditions must be

satisfied. The problem must be written in a recursive form, and the problem statement must include

a stopping

condition. The best example of recursion is calculation of factorial of a integer quantity, in which the

same procedure is repeating itself.

Let us consider the example of factorial:


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#include

main()

{

int number;

long int fact(int number);

printf(Enter number);scanf(%d, & number);printf(Factorial of number is % d\n, fact(number));}

long int fact(int number)

{

if(number


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while(status == 0) break;

}

printf("\n\n\nSUM of entered integers : %ld",SUM);

printf("\nPRODUCT of entered integers: %ld",PRODUCT);

getch();

}

3. With the help of a recursive function, write a program to fin the factorial of a

number between 1 and 1000 ?

Ans:#include

#include

int factorial(int);

void main(){

int n;

clrscr();

printf("Enter number to find factorial : ");

scanf("%d",&n);

printf("Factorial = %d",factorial(n));

getch();

}

int factorial(int n)

{if(n


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1) Creator/constructor: These functions create a new instance of the designated type.

2) Transformers: These functions also create an instance of the designated type, generally by using

one or more other instances.

3) Observers/reporters: These functions provide information about an instance of the type, but

they do not change the instance.

b. Stack as an Abstract DATA TypeA stack is simply a list of elements with insertions and deletions permitted at one end called

the stack top. That means that it is possible to remove elements from a stack in reverse order from

the insertion of elements into the stack. Thus, a stack DATA body exhibits the LIFO (last in first out)

property. Push and pop are the operations that are provided for insertion of an element into the

stack and the removal of an element from the stack, respectively. Shown in Figure 1 are the effects

of push and pop operations on the stack.

Figure 1: Stack operations

Since a stack is BASICally a list, it can be implemented by using an array or by using a linked

representation.

Array Implementation of a Stack

When an array is used to implement a stack, the push and pop operations are realized by

using the operations available on an array. The limitation of an array implementation is that thestack cannot grow and shrink dynamically as per the requirement.

A complete C program to implement a stack using an array appears here:

#include

#define MAX 10 /* The maximum size of the stack */

#include

void push(int stack[], int *top, int value)

{

if(*top < MAX )

{

*top = *top + 1;

stack[*top] = value;}

else

{

printf(The stack is full can not push a value\n);exit(0);

}

}

void pop(int stack[], int *top, int * value)

{

if(*top >= 0 ){


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*value = stack[*top];

*top = *top 1;}

else

{

printf(The stack is empty can not pop a value\n);exit(0);

}

}

void main()

{

int stack[MAX];

int top = -1;

int n,value;

do

{do

{

printf(Enter the element to be pushed\n);

scanf(%d,&value);push(stack,&top,value);

printf(Enter 1 to continue\n);scanf(%d,&n);} while(n == 1);

printf(Enter 1 to pop an element\n);

scanf(%d,&n);while( n == 1){

pop(stack,&top,&value);

printf(The value popped is %d\n,value);

printf(Enter 1 to pop an element\n);

scanf(%d,&n);}

printf(Enter 1 to continue\n);scanf(%d,&n);} while(n == 1);

}

c. Queue as an Abstract DATA TypeA queue is also a list of elements with insertions permitted at one endcalled the rear, and

deletions permitted from the other endcalled the front. This means that the removal of elementsfrom a queue is possible in the same order in which the insertion of elements is made into the

queue. Thus, a queue DATA body exhibits the FIFO (first in first out) property. insert and delete are

the operations that are provided for insertion of elements into the queue and the removal of

elements from the queue, respectively. Shown in Figure 6.3 are the effects of insert and deleteoperations on the queue. Initially both front and rear are initialized to -1.


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Array Implementation of a QueueWhen an array is used to implement a queue, then the insert and delete operations are

realized using the operations available on an array. The limitation of an array implementation is that

the queue cannot grow and shrink dynamically as per the requirement.

A complete C program to implement a queue by using an array is shown here:#include

#define MAX 10 /* The maximum size of the queue */

#include

void insert(int queue[], int *rear, int value)

{

if(*rear < MAX-1)

{

*rear= *rear +1;

queue[*rear] = value;

}else

{

printf(The queue is full can not insert a value\n);exit(0);

}

}

void delete(int queue[], int *front, int rear, int * value)

{

if(*front == rear)

{printf(The queue is empty can not delete a value\n);

FIG 2. Queue operation


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exit(0);

}

*front = *front + 1;

*value = queue[*front];

}

void main()

{

int queue[MAX];

int front,rear;

int n,value;

front=rear=(-1);

do

{

do

{

printf(Enter the element to be inserted\n);scanf(%d,&value);insert(queue,&rear,value);

printf(Enter 1 to continue\n);

scanf(%d,&n);} while(n == 1);

printf(Enter 1 to delete an element\n);

scanf(%d,&n);while( n == 1)

{

delete(queue,&front,rear,&value);printf(The value deleted is %d\n,value);printf(Enter 1 to delete an element\n);scanf(%d,&n);}

printf(Enter 1 to continue\n);

scanf(%d,&n);} while(n == 1);

}

7. Describe the following with suitable programming examples:

a. Input/Output operations on filesb. Predefined Streams

c. Error handling during I/O operations

d. Random access to files

Ans:a. Input/Output operations on files

For each of the I/O library functions weve been using so far, theres a companion functionwhich accepts an additional file pointer argument telling it where to read from or write to. The

companion function to printf is fprintf, and the file pointer argument comes first. To print a string to

the output.dat file we opened in the previous section, we might call

fprintf(ofp, "Hello, world!\n");

The companion function to getchar is getc, and the file pointer is its only argument. To reada character from the input.dat file we opened in the previous section, we might call


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int c;

c = getc(ifp);

The companion function to putchar is putc, and the file pointer argument comes last. To

write a character to output.dat, we could call

putc(c, ofp);

Our own getline function calls getchar and so always reads the standard input. We couldwrite a companion fgetline function which reads from an arbitrary file pointer:

#include

/* Read one line from fp, */

/* copying it to line array (but no more than max chars). */

/* Does not place terminating \n in line array. */

/* Returns line length, or 0 for empty line, or EOF for end-of-file. */

int fgetline(FILE *fp, char line[], int max)

{

int nch = 0;int c;

max = max - 1; /* leave room for '\0' */

while((c = getc(fp)) != EOF)

{

if(c == '\n')

break;

if(nch < max)

{

line[nch] = c;nch = nch + 1;

}

}

if(c == EOF && nch == 0)

return EOF;

line[nch] = '\0';

return nch;

}

Now we could read one line from ifp by calling

char line[MAXLINE];

...

fgetline(ifp, line, MAXLINE);

b. Predefined StreamsBesides the file pointers which we explicitly open by calling fopen, there are also three

predefined streams. stdin is a constant file pointer corresponding to standard input, and stdout is a

constant file pointer corresponding to standard output. Both of these can be used anywhere a file

pointer is called for; for example, getchar() is the same as getc(stdin) and putchar(c) is the same as

putc(c, stdout). The third predefined stream is stderr. Like stdout, stderr is typically connected to the

screen by default. The difference is that stderr is not redirected when the standard output is

redirected. For example, under Unix or MS-DOS, when you invoke


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program > filename

Anything printed to stdout is redirected to the file filename, but anything printed to stderr

still goes to the screen. The intention behind stderr is that it is the standard error output; errormessages printed to it will not disappear into an output file. For example, a more realistic way to

print an error message when a file cant be opened would be

if((ifp = fopen(filename, "r")) == NULL){

fprintf(stderr, "can't open file %s\n", filename);

exit or return

}

where filename is a string avalchanda indicating the file name to be opened. Not only is the

error message printed to stderr, but it is also more informative in that it mentions the name of the

file that couldnt be opened.c. Error handling during I/O operations

The standard I/O functions maintain two indicators with each open stream to show the end-

of-file and error status of the stream. These can be interrogated and set by the following functions:#include

void clearerr(FILE *stream);

int feof(FILE *stream);

int ferror(FILE *stream);

void perror(const char *s);

clearerr clears the error and EOF indicators for the stream.

feofreturns non-zero if the streams EOF indicator is set, zero otherwise.

ferror returns non-zero if the streams error indicator is set, zero otherwise.perror prints a single-line error message on the programs standard output, prefixed by the stringpointed to by s, with a colon and a space appended. The error message is determined by the value of

errno and is intended to give some explanation of the condition causing the error. For example, thisprogram produces the error message shown:

#include

#include

main()

{

fclose(stdout);

if(fgetc(stdout) >= 0){

fprintf(stderr, What no error!\n);exit(EXIT_FAILURE);

}

perror(fgetc);

exit(EXIT_SUCCESS);

}

/* Result */

fgetc: Bad file number

d. Random access to files

The file I/O routines all work in the same way; unless the user takes explicit steps to change

the file position indicator, files will be read and written sequentially. A read followed by a write

followed by a read (if the file was opened in a mode to permit that) will cause the second read to

start immediately following the end of the DATA just written. (Remember that stdio insists on the

user inserting a buffer-flushing operation between each element of a read-write-read cycle.) To

control this, the Random Access functions allow control over the implied read/write position in the


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file. The file position indicator is moved without the need for a read or a write, and indicates the

byte to be the subject of the next operation on the file.

Three types of function exist which allow the file position indicator to be examined or

changed. Their declarations and descriptions follow.

#include

/* return file position indicator */

long ftell(FILE *stream);

int fgetpos(FILE *stream, fpos_t *pos);

/* set file position indicator to zero */

void rewind(FILE *stream);

/* set file position indicator */

int fseek(FILE *stream, long offset, int ptrname);

int fsetpos(FILE *stream, const fpos_t *pos);

ftell returns the current value (measured in characters) of the file position indicator if stream refers

to a binary file. For a text file, a magic number is returned, which may only be used on asubsequent call to fseek to reposition to the current file position indicator. On failure, -1L is returned

and errno is set.

rewind sets the current file position indicator to the start of the file indicated by stream. The fileserror indicator is reset by a call of rewind. No value is returned.

fseek allows the file position indicator for stream to be set to an arbitrary value (for binary files), or

for text files, only to a position obtained from ftell, as follows:

In the general case, the file position indicator is set to offset bytes (characters) from a pointin the file determined by the value of ptrname. Offset may be negative. The values of

ptrname may be SEEK_SET, which sets the file position indicator relative to the beginning ofthe file, SEEK_CUR, which sets the file position indicator relative to its current value, and

SEEK_END, which sets the file position indicator relative to the end of the file. The latter is

not necessarily guaranteed to work properly on binary streams.

For text files, offset must either be zero or a value returned from a previous call to ftell forthe same stream, and the value of ptrname must be SEEK_SET.

fseek clears the end of file indicator for the given stream and erases the memory of anyungetc. It works for both input and output.

Zero is returned for success, non-zero for a forbidden request.Note that for ftell and fseek it must be possible to encode the value of the file position

indicator into a long. This may not work for very long files, so the Standard introduces fgetpos and

fsetpos which have been specified in a way that removes the problem.

fgetpos stores the current file position indicator for stream in the object pointed to by pos.

The value stored is magic and only used to return to the specified position for the same streamusing fsetpos.

fsetpos works as described above, also clearing the streams end-of-file indicator andforgetting the effects of any ungetc operations.

For both functions, on success, zero is returned; on failure, non-zero is returned and errno is

set.


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NAME : RAJMAL JAIN

REGISTRATION NO : 5252552

LEARNING CENTER

NAME: ITS

LEARNING CENTER CODE : 01964

COURSE : PGDCA

SUBJECT: MC0062 - Digital Systems, Computer Organization and

Architecture

SEMESTER : 1

MODULE NO :DATE OF SUBMISSION :


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MARKS AWARDED :

DIRECTORATE OF DISTANCE EDUCATION

SIKKIM MANIPAL UNIVERSITY

IT

NARKAGAR

OPP. RAVAN NI OFFICE , ABOVE RAM BHAROSE RESTAURANT

BHAGU BHAI NO VANDO FAKIRCHAND 5252552

SIGN OF COORDINATOR SIGN OF CENTER SIGN OF EVALUATOR

IT

NAME OF STUDENT : RAJMAL JAIN


COURSE : PGDCA

SEMESTER : 1

SUBJECT : MC0062 - Digital Systems, Computer Organization and

Architecture

ASSIGNMENT NO : 1

DATE OF SUBMISSION : _______________________________

SIGNATURE OF STUDENT : SIGNATURE OF COUNCELLER WITH

SEAL


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Assignment Set 11. Explain the following logic with neat diagram:

A). NOT logic

B). NAND logicC). XOR logic

Ans: A). NOT gateThe NOT gate performs the BASIC logical function called inversion or complementation. NOT

gate is also called inverter. The purpose of this gate is to convert one logic level into the opposite

logic level. It has one input and one output. When a HIGH level is applied to an inverter, a LOW level

appears on its output and vice versa.

If X is the input, then output F can be represented mathematically as F = X', Here apostrophe

(') denotes the NOT (inversion) operation. There are a couple of other ways to represent inversion,

F= !X, here ! represents inversion. Truth table and NOT gate symbol is shown in the figure below.

Symbol

Truth Table

X Y=X'

0 1

1

0

NOT gate using "transistor-resistor" logic is shown in the figure below, where X is the input

and F is the output.

The NOT gate is an electronic circuit that produces an inverted version of the input at its

output. It is also known as an inverter. If the input avalchanda is A, the inverted output is known as

NOT A

Circuit


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When X = 1, The transistor input pin 1 is HIGH, this produces the forward bias across the

emitter base junction and so the transistor conducts. As the collector current flows, the voltage drop

across RL increases and hence F is LOW.

When X = 0, the transistor input pin 2 is LOW: this produces no bias voltage across the

transistor base emitter junction. Thus Voltage at F is HIGH.

The diagrams below show two ways that the NAND logic gate can be configured to produce

a NOT gate. It can also be done using NOR logic gates in the same way.

B). NAND gate

NAND gate is a cascade of AND gate and NOT gate, as shown in the figure below. It has two

or more inputs and only one output. The output of NAND gate is HIGH when any one of its input is

LOW (i.e. even if one input is LOW, Output will be HIGH).

NAND From AND and NOT

If X and Y are two inputs, then output F can be represented mathematically as F = (X.Y)',

Here dot (.) denotes the AND operation and (') denotes inversion. Truth table and symbol of the N

AND gate is shown in the figure below.

Symbol


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0 0 0

0 1 1

1 0 1

1 1 0

The 'Exclusive-OR' gate is a circuit which will give a high output ifeither, but not both, of its

two inputs are high. An encircled plus sign ( ) is used to show the EOR operation

2. Use Boolean algebra to simplify the logic function and realize the given function and

minimized function using discrete gates. babdcbaf

Ans: i) Direct realization of the function

ii) Simplified realization of the function

3. Simplify the given logic expressions with the given three inputs.

mm

,,,fand,,,,,f 6542765210 21

Ans:

Or

a

b

c

f


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Case i.) Output is with

Case ii.) Output is with

Case ii) has a common term . Therefore realization requires lesser number of gates

Case i.) Output is with

Case ii) Output is with


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4. Explain the following for Instructions:

A). DATA processing

B).DATA storage

C). DATA movement

D). Control

Ans:A). DATA processing

DATA transfer

s the most fundamental type of machine instruction. The DATA transfer must specifiy1. the location of the source and destination each location can be memory, register or top ofstack

2. the length of the DATA to be transfered3. The mode of addressing for each operand

If both the operands are CPU registers, then the CPU simply causes DATA to be transfered

from one register to another. This operation is internal to the CPU. If one or both operands are in

memory, then the CPU must perform some or all of the following actions:

Calculate the memory address, based on the address mode. if the address refers to virtual memory, translate from virtual to actual memory address. Determine whether addressed item is in cache.

If not issue command to memory module.For example: Move, Store, Load (Fetch), Exchange, Clear (Reset), set, Push, Pop


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Arithmetic

Most machines provide BASIC arithmetic functions like Add, Subtract, Multiply, Divide. They

are invariably provided for signed integer numbers. Often they are also provided for floating point

and packed decimal numbers. Also some operations include only a single operand like Absolute that

takes only absolute value of the operand, Negate that takes the compliment of the operands,

Increment that increments the value of operand by 1, Decrement that decrements the value ofoperand by 1.

Logical

Machines also provide a variety of operations for manipulating individual bits of a word

Oftern refered to as bit twiddling. They are based on boolean operations like AND, OR, NOT, XOR,

Test, Compare, Shift, Rotate, Set control avalchandas.

B).DATA storage

Computer DATA storage, often called storage or memory, refers tocomputercomponents

and recording media that retain digital DATA used for computing for some interval of time.

Computer DATA storage provides one of the core functions of the modern computer, that of

information retention. It is one of the fundamental components of all modern computers, andcoupled with a central processing unit (CPU, a processor), implements the BASIC computer model

used since the 1940s.
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Primary storage

Primary storage (or main memory or internal memory), often referred to simply as

memory, is the only one directly accessible to the CPU. The CPU continuously reads instructions

stored there and executes them as required. Any DATA actively operated on is also stored there inuniform manner.

Secondary storage

Secondary storage (also known as external memory or auxiliary storage), differs from

primary storage in that it is not directly accessible by the CPU. The computer usually uses its

input/output channels to access secondary storage and transfers the desired DATA using

intermediate areain primary storage. Secondary storage does not lose the DATA when the device is

powered downit is non-volatile. Per unit, it is typically also two orders of magnitude less expensivethan primary storage. Consequently, modern computer systems typically have two orders of

magnitude more secondary storage than primary storage and DATA is kept for a longer time there.

Tertiary storage

Tertiary storage or tertiary memory,[4]

provides a third level of storage. Typically it involvesa robotic mechanism which will mount(insert) and dismountremovable mass storage media into a
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storage device according to the system's demands; this DATA is often copied to secondary storage

before use. It is primarily used for archiving rarely accessed information since it is much slower than

secondary storage (e.g. 560 seconds vs. 1-10 milliseconds). This is primarily useful forextraordinarily large DATA stores, accessed without human operators. Typical examples includetape

librariesandoptical jukeboxes.

C). DATA movementInstructions to copy DATA and perform arithmetic operations on the MSP=430 reference

two operands. The first called the "source" (abbreviated as src) describes an operand (avalchanda)

from which DATA is only obtained, and the second operand, called the destination (dst or dest)

describes a avalchanda to whom the operation is applied. By default, two-operand instructions

operate on words (2-bytes=16 bits) at a time. This default option can be explicitly specified by a ".w"

suffix. To operate on bytes, a ".b" suffix can be specified instead.

For example,

mov.b &0x1000, &1002 ; move 1 byte from 0x1000 to 0x1002

Is a "byte move" instruction, which implements an assignment operator (=). This instruction

copies one byte from from (source) address 0x1000 to the (destination) address 0x1002. The

ampersand (&) is required.

Listing of two-operand instructions

opcode mnemonic meaning flags affected**

4 movmove

dest = srcnone

5 add dest += src all

6 addc add with carrydest += src + C

all

7 subcsub with carry

dest -= (src + C)all

8 sub*subtract

dest -= srcall

9 cmp*compare

(like sub; result not saved)

dest - src

all

0xa=10 dadd decimal adjust ZCN

0xb=11 bitbit test

(AND, but result not stored)

N,Z;

C= !Z; V=0

0xc=12 bicbit clear

dst &= ~srcnone

0xd=13 bisbit set (OR)

dst |= srcnone

0xe=14 xor dst ^= src arcane**

0xf=15 and dst &= src Z, N
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C=!Z; V=0

D). Control

The control unit is the part of acomputerthat controls the computer's operation. BASICally,

each part of the computer requires control signals to arrive at particular times for each instruction of

the computer'ssoftware. The control unit provides those control signals

he control system's function is as followsnote that this is a simplified description, andsome of these steps may be performed concurrently or in a different order depending on the type of

CPU:

1. Read the code for the next instruction from the cell indicated by the program counter.2. Decode the numerical code for the instruction into a set of commands or signals for each of

the other systems.

3. Increment the program counter so it points to the next instruction.4. Read whatever DATA the instruction requires from cells in memory (or perhaps from an

input device). The location of this required DATA is typically stored within the instruction

code.

5. Provide the necessary DATA to an ALU or register.6. If the instruction requires an ALU or specialized hardware to complete, instruct the

hardware to perform the requested operation.

7. Write the result from the ALU back to a memory location or to a register or perhaps anoutput device.

8. Jump back to step (1).

5. Explain the Virtual address translation method with neat diagram.

Ans:Virtual address translation method

A virtual address translation method based on the concept of fixed length pages is shown inFig. 6.20. Each virtual address generated by the processor is interpreted as a page number followed

by a word number. Information about the disk or the main memory is kept in a page table in the

main memory.
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The starting address of this table is kept in a page table base register. By adding the page

number to the contents of this register, the address of corresponding entry in the page table isobtained. The content of this location gives the starting address of the page if that page currently

resides in the main memory. Otherwise they indicate the location where the page is to be found in

the secondary storage. In this case the entry in the table usually points to an area in the main

memory where the secondary storage address of the page is held. Each entry also includes some

control bits to describe the status of the page while it is in the main memory. One control bit

indicates whether the page has been modified when it was in the main memory.

If the page table is stored in the main memory unit, then the two main memory accesses

must be made for every main memory access requested by the program. This may result in a

degradation of speed by a factor of two. However a specialized cache memory is used in most of the

systems to speed up the translation process by storing recently used virtual to physical address

translation.Virtual memory increases the effective size of the main memory. Only the active space of

the virtual address space is mapped onto locations in the physical main memory, whereas the

remaining virtual addresses are mapped onto the bulk storage devices used. During a memory cycle

the addressing spacing mechanism (hardware or software) determines whether the addressed

information is in the physical main memory unit. If it is, the proper information is accessed and the

execution proceeds. If it is not, a contiguous block of words containing the desired information are

transferred from the bulk storage to main memory displacing some block that is currently inactive.

6. Explain the addition of a two floating point numbers with examples.

Ans:

The steps (or stages) of a floating-point addition:


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1. The exponents of the two floating-point numbers to be added are compared to find thenumber with the smallest magnitude

2. The significand of the number with the smaller magnitude is shifted so that the exponents ofthe two numbers agree

3. The significands are added4. The result of the addition is normalized5. Checks are made to see if any floating-point exceptions occurred during the addition, such as

overflow

6. Rounding occursFloating-Point Addition Example

Example: s = x + y

numbers to be added are x = 1234.00 and y = -567.8 these are represented in decimal notation with a mantissa (significand) of four digits six stages (A F) are required to complete the addition

StepA B C D E F

X 0.1234E4 0.12340E4

Y -0.05678E3-0.05678E4S 0.066620E40.6662E30.6662E30.6662E3

Assignment Set 2

1. Implement the following SOP expressionAns:

A). m

,,,,,,,f 15141276321

B). m

,,,f 14761

C). m

,,,,,,f 1412108642

D). m

,,,,,,,f 15131197531


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2. What do you mean by latch? Explain the working of NAND gate based latch

operation.

Ans:The latch is a bi-stable device. The term bi-stable refers with respect to the output of the

device that can reside in either of two states and a feedback mechanism is used. These are similar tothe flip-flops in that even flip-flops are bi-stable devices. The difference between the two is in the

method used for changing their output state.

Active Low S-R Latch ( NAND Gate S-R Latch)

A NAND gate active high S-R latch can be constructed and is shown in figure 1 which has two

cross connected or coupled NAND gate circuitry.

Figure 1: active LOW S-R Latch

Inputs OutputComments

S R

0 0 ? ? Invalid

0 1 1 0 SET

1 0 0 1 RESET

1 1 No change

Table 1: Truth table of S-R Latch

The operation of the active-LOW NAND latch can be summarized as follows

1. SET = 0 and RESET = 0: the condition tries to set and reset the output of the latch at thesame time or output is unpredictable. This state is referred as invalid state.

2. SET = 0 and RESET = 1: always sets the output = 1 and = 03. SET = 1 and RE4. SET = 0: always resets the output = 0 and = 15. SET = 1 and RESET = 1: has no effect on the output state from its previous state.Active HIGH NAND latch can be implemented whose circuit diagram is shown in figure 2 and its

truth table is shown in table 2


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Figure 2: active HIGH S-R Latch

Inputs OutputComments

S R

0 0 No change

0 1 0 1 RESET

1 0 1 0 SET

1 1 ? ? Invalid

Table 2: Truth table of S-R Latch

3. How does a synchronous counter differ from an asynchronous counter? Explain the

working of 4-bit binary synchronous counter.

Ans:

Asynchronous counter V/S Synchronous CounterIn an asynchronous counter, an external event is used to directly SET or CLEAR a flip-flop

when it occurs. In a synchronous counter however, the external event is used to produce a pulse

that is synchronised with the internal clock. An example of an asynchronous counter is a ripple

counter. Each flip-flop in the ripple counter is clocked by the output from the previous flip-flop. Only

the first flip-flop is clocked by an external clock

A synchronous counter has the same sequence of counting as in an asynchronous or ripple

counter. Flip-flops changes state when a synchronous counter is incremented on the positive or

negative edge of a clock pulse. Where as in the asynchronous counters the flip-flop changes state for

the positive or the negative edge of the preceding flip-flops output. Thus all the flip-flops areconnected to a same clock signal and changes state at the same time.

A Four-bit Synchronous Binary Up-counterFigure 1 shows a four-bit binary up counter and Figure 2 gives its timing diagram. The

reasoning behind the J and K input control for the first three flip-flops is the same as presented

previously for the three stage counter. For the fourth stage, FFD, changes only twice in the

sequence. And notice that during both of these transitions occur following the times, QA, QB and QC

are all HIGH. This condition is denoted by a three input AND gate. For all other times inputs J and K

of FFD are LOW, and it is in a no-change condition.


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Figure 1: A Four bit synchronous up counter.

Figure 2: Timing diagram for the four bit synchronous up counter.

4. Write notes on:

A). I/O commands

B). I/O instructionsAns:A). I/O commands:

To execute an I/O related instruction, the CPU issues an address, specifying the particular

I/O modu;e and external device and an I/O command. Four types of I/O commands can be received

by the I/O module when it is addressed by the CPU. They are

A control command: is used to activate a peripheral and tell what to do.Example: a magnetic tape may be directed to rewind or move forward a record.

A test command: is used to test various status conditions associated with an I/O module andits peripherals. The CPU wants to know the interested peripheral for use. It also wants to

know the most recent I/O operation is completed and if any errors have occurred.

A read command: it causes the I/O module to obtain an item of DATA from the peripheraland place it in an internal buffer. The CPU then gets the DATA items by requesting I/O

module to place it on the DATA bus.

A write command: it causes the I/O module to take an item of DATA from the DATA bus andsubsequently transmit the DATA item to the peripheral.

A flow chart for input of a block of DATA using programmed I/O is as shown in figure 1. Itread in a block of DATA from a peripheral device into memory.


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Figure 1: input of block of DATA using programmed I/O

DATA is read in one word at a time. For each word read in, the CPU keeps checking thestatus until the word is available in I/O modules DATA register. That is the possible sequence of I/Ocommands and actions are:

CPU issues address Identifies module (& device if >1 per module) CPU issues command Control telling module what to do e.g. spin up disk Test check status e.g. power? Error? Read/Write

Module transfers DATA via buffer from/to deviceFrom the flow chart it is clear that the main disadvantage of this technique is that it is time

consuming process that keeps the processor busy unnecessarily.

B). I/O instructions

Addressing I/O Devices

Under programmed I/O DATA transfer is very like memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address)

I/O Mapping

When the CPU, main memory, and I/O module share a common bus two modes of addressing are

possible.

1.

Memory mapped I/O Devices and memory share an address space


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I/O looks just like memory read/write No special commands for I/O Large selection of memory access commands available1. Isolated I/O Separate address spaces Need I/O or memory select lines Special commands for I/O Limited set

Consider an example: The processor can monitor the keyboard status flag SIN and transfer a

character from DATAIN to register R1 using the following sequence of operations:

READWAIT Branch to READWAIT if SIN = 0

Input from DATAIN to R1

The Branch operation is usually implemented by two machine instructions. The first

instruction tests the status flag and the second performs the branch. Although the details vary from

computer to computer, the main idea is that the processor monitors the status flag by executing a

short wait loop and proceeds to transfer the input DATA when SIN is set to 1 as a result of a key

being struck. The Input operation resets SIN to 0.Another example for transferring output to the display. The sequence of instructions are:

WRITEWAIT Branch to WRITEWAIT if SOUT = 0.

Output from R1 to DATAOUT

Again, the Branch operation is normally implemented by two machine instructions. The wait

loop is executed repeatedly until the status flag SOUT is set to 1 by the display when it is free to

receive a character. The Output operation transfers a character from R1 to DATAOUT to be

displayed, and it clears SOUT to 0.

We assume that the initial state of SIN is 0 and the initial state of SOUT is 1. This initialization

is normally performed by the device control circuits when the devices are placed under computer

control before program execution begins. Until now, we have assumed that the addresses issued by

the processor to access instructions and operands always refer to memory locations. Manycomputers use an arrangement called memory-mapped I/O in which some memory address values

are used to refer to peripheral device buffer registers, such as DATAIN and DATAOUT.

Thus, no special instructions are needed to access the contents of these registers; DATA can

be transferred between these registers and the processor using instructions that we have already

discussed, such as Move, Load or Store. For example, the contents of the keyboard character buffer

DATAIN can be transferred to register R1 in the processor by the instruction

MoveByte DATAIN, R1

Similarly, the contents of register R1 can be transferred to DATAOUT by the instruction

MoveByte R1,DATAOUT The status flags SIN and SOUT are automatically cleared when the buffer

registers DATAIN and DATAOUT are referenced, respectively. The MoveByte operation code signifies

that the operand size is a byte, to distinguish it from the operation code Move that has been used

for word operands. We have established that the two DATA buffers may be addressed as if they

were two memory locations. It is possible to deal with the status flags SIN and SOUT in the same

way, by assigning them distinct addresses. However, it is more common to include SIN and SOUT in

device status registers, one for each of the two devices.

Let us assume that bit b3 in registers INSTATUS and OUTSTATUS corresponds to SIN and

SOUT, respectively. The read operation just described may now be implemented by the machine

instruction sequence READWAIT Testbit #3, INSTATUS Branch=0 READWAIT MoveByte DATAIN, R1.

The write operation may be implemented as WRITEWAIT Testbit #3, OUTSTATUS.

Branch=0 WRITEWAIT

MoveByte R1, DATAOUT

The Testbit instruction tests the state of one bit in the destination location, where the bit

position to be tested is indicated by the first operand. If the bit tested is equal to 0, then the


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condition of the branch instruction is true, and a branch is made to the beginning of the wait loop.

When the device is ready, that is, when the bit tested becomes equal to 1, the DATA are read from

the input buffer or written into the output buffer.

The program shown in Figure 2 uses these two operations to read a line of characters typed

at a keyboard and send them out to a display device. As the characters are read in, one by one, they

are stored in a DATA area in the memory and then echoed back out to the display. The programfinishes when the carriage return character, CR, is read, stored and sent to the display. The address

of the first byte location of the memory DATA area where the line is to be stored is LOC. Register R0

is used to point to this area, and it is initially loaded with the address LOC by the first instruction in

the program. R0 is incremented for each character read and displayed by the Autoincrement

addressing mode used in the Compare instruction.

Figure 2: program for read from a keyboard and write output to a display device

5. What are the functional requirements of a CPU? Discuss the significance of DATA

Path and Control Signal

Ans:

Functional Requirements

The functional requirements of control unit are those functions that the control unit must

perform. And these are the basis for the design and implementation of the control unit.

A three step process that lead to the characterization of the Control unit:

Define the BASIC elements of the processor Describe the micro-operations that the processor performs Determine the functions that the control unit must perform to cause the micro-operations

to be performed.

BASIC Elements of ProcessorThe following are the BASIC functional elements of a CPU:

o ALU: is the functional essence of the computer.o Registers: are used to store DATA internal to the CPU.

As discussed earlier, Some register also contain status information needed to manage

instruction sequencing ex: program status word. Some register contain DATA for transfer

between ALU, memory, I/O modules.

o Internal DATA paths: are used to move DATA between the registers and ALUo External DATA paths: are used to link registers and I/O modules, often by a system

bus.

o Control Unit: The control unit causes operations to happen within the CPU. Types of Micro-operation


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The execution of a program as seen earlier consists of operations involving these CPU

elements. These operations consist of a sequence of micro operations. All micro instructions

fall into one of the following categories:

o Transfer DATA between registerso Transfer DATA from register to externalo Transfer DATA from external to registero Perform arithmetic or logical ops

All micro operations need to perform one instruction cycle.

Functions of Control UnitNow we define more explicitly the function of control unit. The control unit perform two

tasks:

o Sequencing: The control unit causes the CPU to step through a series of micro-operations in proper sequence based on the program being executed.

o Execution: The control unit causes each micro-operation to be performed.These tasks are accomplished using Control Signals

Control Signals

For the control unit to perform its function, it must have inputs that allow it to determinethe state of the system and outputs that allow it to control the behaviour of the system. These are

the external specifications of the control unit. Internally, the control unit must have the logic

required to perform sequencing and execution functions.

Let us take a close look on the general model of the control unit given in figure 1. The model

is indicated with all of its inputs and outputs. As from earlier section we know that the function of

control unit is sequencing and then execution of instruction. Hence the control unit organization

can be considered as shown in figure 2.

Fi ure 1:


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Figure 2: Control Unit Organization

Control unit Inputs

The possible inputs for the control units are:

Clock: The control unit uses clock to maintain the timings. The control unit causes one micro-

instruction (or set of parallel micro-instructions) per clock cycle. This is sometimes referred to as the

processor clock time or the clock cycle time.

Instruction register: Op-code of the current instruction is used to determine which micro-

instructions to be performed during the execution cycle.

Flags: These are needed by the control unit to determine the status of the CPU and outcome

of previous ALU operations.

Example: As seen earlier the instruction ISZ, which is increment and skip if zero, the control

unit will increment the PC if the zero flag is set.

Control signals from control bus: the control bus portion of the system bus provides signals

to the control unit, such as interrupt signals and acknowledgements.

Control Signals output

The following are the control signals which are output of the control unit:

Control signals within CPU: There are two types

1. Signals that cause DATA to be moved from one register to another.2. Signals that activate specific ALU functions

Control signals to control bus: There are two types

1. signals to memory2. signals to I/O modules

DATA paths and control signals

To illustrate the DATA paths and control signals we will consider an example as shown in

figure 3. This is a simple machine whose CPU has a single accumulator.


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The control unit receives inputs from the clock, the IR, and the flags. With each clock cycle,

the control unit reads all of its inputs and emits a set of control signals. Control signals go to three

separate destinations.

ALU: the control unit controls the operation of ALU by a set of control signals. This signalactivates the various logic devices and gates within the ALU.

DATA paths: the control unit controls the internal flow of DATA. For each DATA path to becontrolled there is a gate indicated by a circle in figure 3. A control signal temporarily opensthe gate to let DATA pass.

Figure 3: DATA paths and control signals

Table 1: Micro-Operations and Control Signals

Micro-Operations Timing Active Control Signals

Fetch:

t1: MAR


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6. write short note on:

A).super scalar processors.

B).RISC

C).CISC

Ans:

A).super scalar processors.A CISC and RISC can be improved with the superscalar or vector architecture. In a

superscalar processor, multiple instruction pipelines are used. That is multiple instructions are issued

per cycle and multiple results are generated per cycle.

The emergence and spread of superscalar processors

The path to widespread use of superscalar instruction issue in main-line processors took

quite some time. As is usual in technology-related developments, superscalar processors emerged in

three consecutive phases. First, the idea was conceived then a few architecture proposals and

prototype machines appeared, and finally, in last phase the commercial products reached the

market.

The idea of superscalar issue was first formulated as early as 1970. It was later reformulated

more precisely in the 1980s. Super scalar RISC processors emerged according to two differentapproaches. Some appeared as the result of converting an existing (scalar) RISC line into a

superscalar one. Examples of this are the Intel 960, MC 88000, HP PA (Precision almost identical to

the Architecture), and RISC lines. The other major approach was to conceive a new architecture, and

to implement it from the very beginning as a superscalar line.

Owing to their higher complexity, superscalar CISC processors appeared on the market after

a considerable delay. Higher than RISC complexity is caused by two reasons. First, in contrast with

RISCs, superscalar CISC processors have to decode multiple avalchanda length instructions. Second,

it is more demanding to implement CISC-type memory architecture than a simple RISC-type

load/store architecture. The Pentium and the MC 68060 are examples of the first superscalar CISC

machines, which have been available since 1993. Both were the result of converting existing CISC

lines into superscalar ones.All of these superscalar CISC processors have a low issue rate of around 2 due to the

additional complexity of superscalar CISC processors mentioned above. We note that some CISC

processors, for instance the Pentium, the Nx586 and the K5, are implemented using a superscalar

RISC core. In the processors the RISC core typically has an issue rate of 4, which is equivalent to a

CISC rate of about 2. Clearly, the market includes different classes of super scalar processors with

varying application fields, performance levels and architectures. The Intel 960 and the Am 29000

superscalar processors are typically intended for high-performance desktop and workstation market.

The PowerPC 602 and PowerPC 603 are exceptions, being low cost, low power models.

Specific tasks of superscalar processing

Super scalar processing can be broken down into a number of specific tasks, which, we will

review based on Figure 1. Since super scalar processors have to issue multiple instructions per cycle,the first task necessarily is parallel decoding. Clearly, decoding in superscalar processors is a

considerably more complex task than in the case of scalar processors and becomes even more

sophisticated as the issue rate increases. Higher issue rates, however, can unduly lengthen the

decoding cycle or can give rise to multiple decoding cycles unless decoding is enhanced. An

increasingly common method of enhancement ispredecoding. This is a partial, decoding performed

in advance of common decoding, while instructions are loaded, into the instruction cache.


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Therefore, in order to achieve higher performance, superscalar processors have introduced

intricate instruction issue policies, involving advanced techniques such as shelving, register renaming

and speculative branch processing. As a consequence, the instruction issue policy used becomes

crucial for achieving higher, processor performance.

B).RISC:

A RISC (reduced instruction set computer) is a microprocessor that is designed to perform asmaller number of types of computer instruction so that it can operate at a higher speed (perform

more million instructions per second, or millions of instructions per second). Since each instruction

type that a computer must perform requires additional transistors and circuitry, a larger list or set of

computer instructions tends to make the microprocessor more complicated and slower in operation

RISC characteristics

Simple instruction set.In a RISC machine, the instruction set contains simple, BASIC instructions, from which more

complex instructions can be composed.

Same length instructions.Each instruction is the same length, so that it may be fetched in a single operation.

1 machine-cycle instructions.Most instructions complete in one machine cycle, which allows the processor to handleseveral instructions at the same time. This pipelining is a key technique used to speed up

RISC machines.

RISC Pros and Cons

The advantages of RISC

Implementing a processor with a simplified instruction set design provides several advantages over

implementing a comparable CISC design:

Speed. Since a simplified instruction set allows for a pipelined, superscalar design RISCprocessors often achieve 2 to 4 times the performance of CISC processors using comparable

semiconductor technology and the same clock rates.

Simpler hardware. Because the instruction set of a RISC processor is so simple, it uses upmuch less chip space; extra functions, such as memory management units or floating point

arithmetic units, can also be placed on the same chip. Smaller chips allow a semconductor

manufacturer to place more parts on a single silicon wafer, which can lower the per-chip

cost dramatically.

Shorter design cycle. Since RISC processors are simpler than corresponding CISC processors,they can be designed more quickly, and can take advantage of other technological

developments sooner than corresponding CISC designs, leading to greater leaps in

performance between generations.

The hazards of RISC

The transition from a CISC design strategy to a RISC design strategy isn't without its problems.

Software engineers should be aware of the key issues which arise when moving code from a CISCprocessor to a RISC processor.

Figure1:


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Code Quality

The performance of a RISC processor depends greatly on the code that it is executing. If the

programmer (or compiler) does a poor job of instruction scheduling, the processor can spend quite a

bit of time stalling: waiting for the result of one instruction before it can proceed with a subsequent

instruction.

Since the scheduling rules can be complicated, most programmers use a high level language (such asC or C++) and leave the instruction scheduling to the compiler.

This makes the performance of a RISC application depend critically on the quality of the code

generated by the compiler. Therefore, developers (and development tool suppliers such as Apple)

have to choose their compiler carefully based on the quality of the generated code.

Debugging

Unfortunately, instruction scheduling can make debugging difficult. If scheduling (and other

optimizations) are turned off, the machine-language instructions show a clear connection with their

corresponding lines of source. However, once instruction scheduling is turned on, the machine

language instructions for one line of source may appear in the middle of the instructions for another

line of source code.

Such an intermingling of machine language instructions not only makes the code hard to read, it canalso defeat the purpose of using a source-level compiler, since single lines of code can no longer be

executed by themselves.

Therefore, many RISC programmers debug their code in an un-optimized, un-scheduled form and

then turn on the scheduler (and other optimizations) and hope that the program continues to work

in the same way.

Code expansion

Since CISC machines perform complexactions with a single instruction,

where RISC machines may require

multiple instructions for the same

action, code expansion can be a

problem.

Code expansion refers to the increase

in size that you get when you take a

program that had been compiled for a

CISC machine and re-compile it for a

RISC machine. The exact expansion

depends primarily on the quality of

the compiler and the nature of the

machine's instruction set.

Fortunately for us, the code expansion

between a 68K processor used in the non-PowerPC Macintoshes and the PowerPC seems to be only

30-50% on the average, although size-optimized PowerPC code can be the same size (or smaller)

than corresponding 68K code.

System Design

Another problem that faces RISC machines is that they require very fast memory systems to feed

them instructions. RISC-based systems typically contain large memory caches, usually on the chip

itself. This is known as a first-level cache.

C).CISC


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CISC, which stands for Complex Instruction Set Computer, is a philosophy for designing chips that

are easy to program and which make efficient use of memory. Each instruction in a CISC instruction

set might perform a series of operations inside the processor. This reduces the number of

instructions required to implement a given program, and allows the programmer to learn a small but

flexible set of instructions.

Characteristics of a CISC design

Introduction

While the chips that emerged from the 1970s and 1980s followed their own unique design paths,

most were bound by what we are calling the "CISC Design Decisions". These chips all have similar

instruction sets, and similar hardware architectures.

In general terms, the instruction sets are designed for the convenience of the assembly-language

programmer and the hardware designs are fairly complex.

Instruction sets

The design constraints that led to the development of CISC (small amounts of slow memory, and the

fact that most early machines were programmed in assembly language) give CISC instruction sets

some common characteristics: A 2-operand format, where instructions have a source and a destination. For example, the

add instruction "add #5, D0" would add the number 5 to the contents of register D0 and

place the result in register D0.

Register to register, register to memory, and memory to register commands. Multiple addressing modes for memory, including specialized modes for indexing through

arrays

Avalchanda length instructions where the length often varies according to the addressingmode

Instructions which require multiple clock cycles to execute. If an instruction requires

additional information before it can run (for example, if the processor needs to read in two memory

locations before operating on them), collecting the extra information will require extra clock cycles.As a result, some CISC instructions will take longer than others to execute.

CISC Pros and Cons

The advantages of CISC

At the time of their initial development, CISC machines used available technologies to optimize

computer performance.

Microprogramming is as easy as assembly language to implement, and much less expensivethan hardwiring a control unit.

The ease of microcoding new instructions allowed designers to make CISC machinesupwardly compatible: a new computer could run the same programs as earlier computers

because the new computer would contain a superset of the instructions of the earlier

computers.

As each instruction became more capable, fewer instructions could be used to implement agiven task. This made more efficient use of the relatively slow main memory.

Because microprogram instruction sets can be written to match the constructs of high-levellanguages, the compiler does not have to be as complicated.

The disadvantages of CISC

Still, designers soon realized that the CISC philosophy had its own problems, including:

Earlier generations of a processor family generally were contained as a subset in every newversion --- so instruction set & chip hardware become more complex with each generation

of computers.

So that as many instructions as possible could be stored in memory with the least possiblewasted space, individual instructions could be of almost any length---this means that


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different instructions will take different amounts of clock time to execute, slowing down the

overall performance of the machine.

Many specialized instructions aren't used frequently enough to justify their existence ---approximately 20% of the available instructions are used in a typical program.

CISC instructions typically set the condition codes as a side effect of the instruction. Not onlydoes setting the condition codes take time, but programmers have to remember to examinethe condition code bits before a subsequent instruction changes them.

NAME : RAJMAL JAIN


LEARNING CENTER

NAME: ITS

LEARNING CENTER CODE : 01964

COURSE : PGDCA

SUBJECT : MC0063 Discrete Mathematics

SEMESTER : 1

MODULE NO :DATE OF SUBMISSION :

MARKS AWARDED :

DIRECTORATE OF DISTANCE EDUCATION

SIKKIM MANIPAL UNIVERSITY

IT

NARKAGAR

OPP. RAVAN NI OFFICE , ABOVE RAM BHAROSE RESTAURANT

BHAGU BHAI NO VANDO FAKIRCHAND 5252552

SIGN OF COORDINATOR SIGN OF CENTER SIGN OF EVALUATOR

IT

NAME OF STUDENT : RAJMAL JAIN


COURSE : PGDCA

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SUBJECT : MC0063Discrete Mathematics

ASSIGNMENT NO : 1

DATE OF SUBMISSION : _______________________________

SIGNATURE OF STUDENT : SIGNATURE OF COUNCELLER WITH SEAL

MAY 2011Master of Computer Application (MCA) Semester 1

MC0063 Discrete Mathematics 4 Credits (Book ID: B0676 and B0677)Assignment Set 1 (60 Marks)

Assignment Set 1

1. Find theth

n term of the following series

(a) 222

531 .

(b) 1.4 + 4.7 + 7.10 +

(c) 11.8

1

8.5

1

5.2

1..

Ans:

The given series are neither in ., . nor in . These are special types of series.

In (a) . , the bases in each term namely 1, 3, 5, form an . whose nth term

by Ex. 1(a) above. Hence, th term of the given series is i.e.,

.

In (b) 1.4 + 4.7 + 7.10 + .., the first figure in each term viz., 1, 4 , 7, forms an whose nth

term and the second figure in each term viz., 4, 7, 10, forms an .

whose th term . Hence th term of the given series is


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In (c) , in each term numerator is 1 and in denominator the corresponding

figures are 2.5, 5.8, 8.11, As before the first figure in each term viz 2, 5, 8, forms an

whoseth

term

and the second figure in each term viz., 5, 8, 11, forms an . whose th term

. Hence the th term of the given series is

2. Obtain the Euler - function, (n), the number of integers x such that1 x < n and relatively prime to n.Ans:


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3. Write short notes on

(a) Public key Cryptography

(b) The R.S.A Cryptosystem

Ans:(a) Public key Cryptography

Public-key cryptography refers to a widely used set of methods for transforming a

written message into a form that can be read only by the intended recipient. Thiscryptographic

approach involves the use of asymmetric key algorithms that is, the non-messageinformation (the public key) needed to transform the message to a secure form is different fromthe information needed to reverse the process (the private key). The person who anticipates

receiving messages first creates both a public key and an associated private key, and publishes

the public key. When someone wants to send a secure message to the creator of these keys, thesender encrypts it (transforms it to secure form) using the intended recipient's public key; todecrypt the message, the recipient uses the private key.

Public key cryptography is a fundamental and widely used technology around the world.

It is the approach which is employed by many cryptographic algorithms andcryptosystems. It

underpins such Internet standards as Transport Layer Security (TLS)(successor to SSL), PGP,andGPG.

(b) The R.S.A CryptosystemIncryptography,RSA (which stands forRivest,ShamirandAdlemanwho first publicly

described it) is analgorithmforpublic-key cryptography.[1]It is the first algorithm known to besuitable forsigningas well as encryption, and was one of the first great advances in public key

cryptography. RSA is widely used in electronic commerce protocols, and is believed to besufficiently secure given sufficiently long keys and the use of up-to-date implementations.
http://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Cryptosystemhttp://en.wikipedia.org/wiki/Cryptosystemhttp://en.wikipedia.org/wiki/Cryptosystemhttp://en.wikipedia.org/wiki/Transport_Layer_Securityhttp://en.wikipedia.org/wiki/Transport_Layer_Securityhttp://en.wikipedia.org/wiki/Transport_Layer_Securityhttp://en.wikipedia.org/wiki/Pretty_Good_Privacyhttp://en.wikipedia.org/wiki/Pretty_Good_Privacyhttp://en.wikipedia.org/wiki/Pretty_Good_Privacyhttp://en.wikipedia.org/wiki/GNU_Privacy_Guardhttp://en.wikipedia.org/wiki/GNU_Privacy_Guardhttp://en.wikipedia.org/wiki/GNU_Privacy_Guardhttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/Adi_Shamirhttp://en.wikipedia.org/wiki/Adi_Shamirhttp://en.wikipedia.org/wiki/Adi_Shamirhttp://en.wikipedia.org/wiki/Leonard_Adlemanhttp://en.wikipedia.org/wiki/Leonard_Adlemanhttp://en.wikipedia.org/wiki/Leonard_Adlemanhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Public-key_cryptographyhttp://en.wikipedia.org/wiki/Public-key_cryptographyhttp://en.wikipedia.org/wiki/RSA#cite_note-rsa-0http://en.wikipedia.org/wiki/RSA#cite_note-rsa-0http://en.wikipedia.org/wiki/RSA#cite_note-rsa-0http://en.wikipedia.org/wiki/Digital_signaturehttp://en.wikipedia.org/wiki/Digital_signaturehttp://en.wikipedia.org/wiki/Digital_signaturehttp://en.wikipedia.org/wiki/Electronic_commercehttp://en.wikipedia.org/wiki/Electronic_commercehttp://en.wikipedia.org/wiki/Electronic_commercehttp://en.wikipedia.org/wiki/Digital_signaturehttp://en.wikipedia.org/wiki/RSA#cite_note-rsa-0http://en.wikipedia.org/wiki/Public-key_cryptographyhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Leonard_Adlemanhttp://en.wikipedia.org/wiki/Adi_Shamirhttp://en.wikipedia.org/wiki/Ron_Rivesthttp://en.wikipedia.org/wiki/Cryptographyhttp://en.wikipedia.org/wiki/GNU_Privacy_Guardhttp://en.wikipedia.org/wiki/Pretty_Good_Privacyhttp://en.wikipedia.org/wiki/Transport_Layer_Securityhttp://en.wikipedia.org/wiki/Cryptosystemhttp://en.wikipedia.org/wiki/Algorithmhttp://en.wikipedia.org/wiki/Cryptography


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(a) a = 0.5

(b) a b(c) a b(d) a b

Ans:

(a) a = 0.5

a = 1 a= 1 0.5

= 0.5

(b) a b

a b = min {0.5,0.7}= 0.5

(c) a b

a b = max{0.5,0.7}

= 0.7

(d) a ba b = min{1,1-0.5+0.7}

= 1

6. Verify whether or not, the following graphs are planar?

Ans:(I ) Observe the Kuratowskis 2nd graph K3,3.

It is clear that the graph contains six vertices vi

i

, , , , , . Now we have a Jordan curve.

So plane of the paper is divided into two regions, one inside and the other outside. Since v1 is

connected to v4, we can add the edge in either inside or outside (without intersecting the

(i)o

o

o

o

o

o

f

d

c

e

ba(ii)

o

o

o

o

o

o

Fig1.AFig 1.B


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edges already drawn). Let us draw inside. (If we choose outside, then we end up with the

same argument Now we have the Fig. 1 (A) Next we have to draw an edge and also

another edge . First we draw . If we draw it inside, we get a cross over the edge

. So we draw it outside. Then we get the Fig. 1 (B). Still we have to draw an edge from v3 to v6. If

drawn inside, it cross the edge (see the Fig. 1 (C) ).

So we can not draw it inside. So we select the case of drawing cross the edge (see the

Fig. 1(D)). Thus can not be drawn either inside or outside with out a cross over. Hence the

given graph is not a planar graph.

(II)

i) From the construction of the dual G*

of G, it is clear that there is a one-to-one

correspondence between the set of all edges ofG and the set of all edges ofG*. Also one edge

ofG*

intersects one edge ofG.

ii) An edge forming a self-loop in G yields a pendent edge in G*

and a pendent edge in G yields a

self-loop in G*.

iii) Edges that are in series in G produce parallel edges in G*.

[Ife1, e2 are in series in G, then , are parallel in G*].

iv) Parallel edges in G produce edges in series in G*.

v)It is a general observation that the number of edges constituting the boundary of a region Fi

in G is equal to the degree of the corresponding vertex pi in G*, and vice versa.

vi) The graph G*

is embedded in the plane, and so G*

is also a planar graph.

vii) Consider the process of drawing a dual G*

from G. It can be observed that G is a dual G*.

Therefore instead of calling G*, a dual ofG, we can usually say that G and G

*are dual graphs.

So, Given Graph is Planar Graph

Fig 1 C

Fig 1 D


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Assignment Set 2

1. Check whether the following set of vectors is LD or LI

(a){(1, 0, 0), (2 , 0, 0), (0, 0, 1)}, (b) {(1, 0, 1) , (1, 1, 0), (1, 1, -1)}

Ans:


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2. (a) Identity e = 3, a-1

= a

9

.

(b) Identit

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Sem 1 Assignment 2011