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Hindawi Publishing Corporation VLSI Design Volume 2010, Article ID 538454, 2 pages doi:10.1155/2010/538454 Editorial Selected Papers from the Midwest Symposium on Circuits and Systems Gregory D. Peterson, 1 Ethan Farquhar, 2 and Benjamin Blalock 1 1 Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN 37996-2100, USA 2 Oak Ridge National Laboratory, Oak Ridge, TN 37831-6006, USA Correspondence should be addressed to Gregory D. Peterson, [email protected] Received 7 April 2010; Accepted 7 April 2010 Copyright © 2010 Gregory D. Peterson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This special issue of the VLSI Design journal is dedicated to the 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), held in August 2008 at Knoxville, Tennessee. The papers at MWSCAS spanned a broad spectrum of topics including theory, CAD, digital systems, and emerging technologies. A number of quality papers in theory and CAD were submitted to this special issue. For example, nonlinear signal processing enables improved performance and power usage, but requires analog circuitry for practical systems. Odame and Hasler explore techniques for representing nonlinear circuit behavior in their paper Nonlinear circuit analysis via perturbation methods and hardware prototyping. Zhu et al. explore a novel capacitor array structure with theoretic and simulation studies to develop a Successive Approximation Register for use with converters in Linearity analysis on a series-split capacitor array for high-speed SAR ADCs. The paper from Reza Hashemanian presents a new approach for biasing analog circuits. The technique begins with localized optimization of nonlinear components at their operating points before turning to global optimization including the use of fixators and norators. The paper Error immune logic for low power probabilistic computing from Marr et al. presents theorems related to constructing datapath circuits that yield an increased immunity to noise and can be applied to develop ultra-low power datapath circuits. The paper by Yelamarthi and Chen presents an algorithm for timing optimization of CMOS dynamic logic along with a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic. Achieving timing closure looms as a major challenge in taping out a design. In Post-CTS delay insertion, Lu and Taskin explore techniques for improving clock performance by developing an optimization approach for implementing clock skew scheduling on circuits after clock tree synthesis is complete. A number of digital circuits and systems were presented at MWSCAS. In A low power digitally controlled oscillator for all digital phase locked loops, Zhao and Kim present a low power and low jitter 12-bit CMOS digitally controlled oscillator. This DCO is a key component of their all-digital PLL that helps achieve faster acquisition times with low power and jitter. Sumathi and Janakiraman present FPGA implementation of an amplitude modulated continuous wave ultrasonic ranger using restructured phase locking scheme that discusses a design for an accurate ultrasonic range finder with a restructured phase-locked loop employing a Sliding Discrete Fourier Transform. Industrial applications of Reconfigurable computing to power systems exploit the FPGA’s flexibility and perfor- mance. Selvajyothi and Janakiraman discuss their design for using an FPGA to control a single phase inverter. In Evolvable block-based neural network design for appli- cations in dynamic environments, Merchant and Peterson explore the use of reconfigurable computing to implement embedded neural network structures that are optimized during execution through the use of genetic algorithms. Pseudorandom number generation represents one of the more expensive computational tasks commonly required for scientific computing, cryptography, simulation, and even gaming algorithms. Lee et al. present a hardware-accelerated

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Page 1: SelectedPapersfromtheMidwestSymposium onCircuitsandSystemsdownloads.hindawi.com/journals/vlsi/2010/538454.pdf · 1Department of Electrical Engineering and Computer Science, University

Hindawi Publishing CorporationVLSI DesignVolume 2010, Article ID 538454, 2 pagesdoi:10.1155/2010/538454

Editorial

Selected Papers from the Midwest Symposiumon Circuits and Systems

Gregory D. Peterson,1 Ethan Farquhar,2 and Benjamin Blalock1

1 Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN 37996-2100, USA2 Oak Ridge National Laboratory, Oak Ridge, TN 37831-6006, USA

Correspondence should be addressed to Gregory D. Peterson, [email protected]

Received 7 April 2010; Accepted 7 April 2010

Copyright © 2010 Gregory D. Peterson et al. This is an open access article distributed under the Creative Commons AttributionLicense, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properlycited.

This special issue of the VLSI Design journal is dedicatedto the 51st IEEE International Midwest Symposium onCircuits and Systems (MWSCAS), held in August 2008 atKnoxville, Tennessee. The papers at MWSCAS spanned abroad spectrum of topics including theory, CAD, digitalsystems, and emerging technologies.

A number of quality papers in theory and CAD weresubmitted to this special issue. For example, nonlinear signalprocessing enables improved performance and power usage,but requires analog circuitry for practical systems. Odameand Hasler explore techniques for representing nonlinearcircuit behavior in their paper Nonlinear circuit analysis viaperturbation methods and hardware prototyping.

Zhu et al. explore a novel capacitor array structure withtheoretic and simulation studies to develop a SuccessiveApproximation Register for use with converters in Linearityanalysis on a series-split capacitor array for high-speed SARADCs.

The paper from Reza Hashemanian presents a newapproach for biasing analog circuits. The technique beginswith localized optimization of nonlinear components attheir operating points before turning to global optimizationincluding the use of fixators and norators.

The paper Error immune logic for low power probabilisticcomputing from Marr et al. presents theorems relatedto constructing datapath circuits that yield an increasedimmunity to noise and can be applied to develop ultra-lowpower datapath circuits.

The paper by Yelamarthi and Chen presents an algorithmfor timing optimization of CMOS dynamic logic along witha Path Oriented IN Time (POINT) optimization flow formixed-static-dynamic CMOS logic.

Achieving timing closure looms as a major challenge intaping out a design. In Post-CTS delay insertion, Lu andTaskin explore techniques for improving clock performanceby developing an optimization approach for implementingclock skew scheduling on circuits after clock tree synthesis iscomplete.

A number of digital circuits and systems were presentedat MWSCAS. In A low power digitally controlled oscillatorfor all digital phase locked loops, Zhao and Kim present alow power and low jitter 12-bit CMOS digitally controlledoscillator. This DCO is a key component of their all-digitalPLL that helps achieve faster acquisition times with lowpower and jitter.

Sumathi and Janakiraman present FPGA implementationof an amplitude modulated continuous wave ultrasonic rangerusing restructured phase locking scheme that discusses a designfor an accurate ultrasonic range finder with a restructuredphase-locked loop employing a Sliding Discrete FourierTransform.

Industrial applications of Reconfigurable computing topower systems exploit the FPGA’s flexibility and perfor-mance. Selvajyothi and Janakiraman discuss their design forusing an FPGA to control a single phase inverter.

In Evolvable block-based neural network design for appli-cations in dynamic environments, Merchant and Petersonexplore the use of reconfigurable computing to implementembedded neural network structures that are optimizedduring execution through the use of genetic algorithms.

Pseudorandom number generation represents one of themore expensive computational tasks commonly required forscientific computing, cryptography, simulation, and evengaming algorithms. Lee et al. present a hardware-accelerated

Page 2: SelectedPapersfromtheMidwestSymposium onCircuitsandSystemsdownloads.hindawi.com/journals/vlsi/2010/538454.pdf · 1Department of Electrical Engineering and Computer Science, University

2 VLSI Design

implementation of a scalable parallel library of pseudo-random number generators.

In A pipelined and parallel architecture for quantum montecarlo simulations on FPGAs, Gothandaraman et al. presenta parameterized framework for supporting computationalchemistry research on high performance reconfigurablecomputing platforms.

The MWSCAS papers also include emerging technologiesand novel applications. Ulaganathan et al. discuss theimplementation of an extreme environment circuit for dataacquisition in A SiGe BiCMOS instrumentation channel forextreme environment applications.

The emerging technology of carbon nanotubes promiseuseful characteristics for devices or wires. Xu et al. explorethese topics in Emerging carbon nanotube electronic circuits,modeling and performance.

Acknowledgments

The authors would like to conclude this Editorial by thankingour Editor in Chief, Dr. Saeid Nooshabadi for his supportin the publication of this Special Issue. They would also liketo express our gratitude for the excellent help and advice ofthe reviewers. They diligently read the submissions, providedinvaluable feedback to the paper authors, and helped us toselect the highest quality papers.

Gregory D. PetersonEthan Farquhar

Benjamin Blalock

Page 3: SelectedPapersfromtheMidwestSymposium onCircuitsandSystemsdownloads.hindawi.com/journals/vlsi/2010/538454.pdf · 1Department of Electrical Engineering and Computer Science, University

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