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Design of a Space Image Processing System

Robert A. Hillmanrah@ebs330.eb.uah.edu

Department of Electrical and ComputerEngineering

University of Alabama in HuntsvilleHuntsville, AL 35899

Mark W. Maiermaier@ebs330.eb.uah.edu

Department of Electrical and ComputerEngineering

University of Alabama In HuntsvilleHuntsville, AL 35899

Abstract

As part of the SEDSAT-1 project we have designed SEASIS (SEDS EarthAtmospheric and Space Imaging System), an image processing computer system for

small satellites . Our design is based on the Transputer chip and features 128 Megabytesof EDAC (Error Detection and Correction) DRAM, redundant video digitizers, and anoption for an advanced signal processor. These features are contained on a 13 inch by 12inch board designed for the thermal and radiation environment of a small satellite. Thispaper reviews the history and features of the design, including choice of processors,design of an error-correcting mass memory system, signal processor options, powercontrol features, CCD Camera Control Circuitry, and physical structuring for thermal andradiation characteristics. The design has been manufactured in a flight printed circuitboard configuration and is undergoing environmental qualification before launch onSEDSAT-1 in July of 1998.

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1. SEDSAT Introduction

SEDSAT-1, signifying Students for the Exploration and Development of SpaceSatellite number one, is being developed at the University of Alabama in Huntsville. TheSEDSAT-1 project has grown from two students and their mentors to an international

project funded by NASA, DARPA, and major corporations. SEDSAT-1 will havesignificant impact on space education, amateur radio communications, and spaceutilization. SEDSAT-1 is scheduled for launch on a Delta II in mid-1998, as a secondarypayload on the JPL DS-1 mission. On-orbit, SEDSAT-1 will be a unique resource foreducation and research.

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Figure 1. External view of SEDSAT-1 Drawing by John Bollich, UAH

The structural frame of the satellite is approximately 13.5 inch cube, with solarcells on 5 of the six sides, and a marman clamp on the 6 th side for interfacing to the delta-II (see figure 1). Also shown are the transponder antennas and the PAL (PanoramicAnnular Lens) - one of the two lens systems used on SEDSAT. In its orbital

configuration, the main objectives of the satellite are:

1. To provide multi-spectral remote sensing to the broadest possible community byuse of SEASIS (SEDS Earth Atmospheric Imaging System) - the optics system ofSEDSAT-1. The two cameras will collect in narrow wave bands (using selectedfilters) to coordinate with ground based observations across the U.S. Unlike otherremote sensing systems, the data will be broadly accessible because will be

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entirely public domain, and because its communication system will be integratedinto the World-Wide-Web.

2. Serve as a development platform for advanced microsatellite positiondetermination and control algorithms. The satellite will demonstrate a uniqueattitude determination system and new technology in active microsatellite control.

3. Provide the amateur radio community with digital packet store-and-forward andanalog repeater systems by use of the Mode-L Transponder, which has an uplinkof 9600 baud, and downlink of 9600 or 57,600.

4. Generate new data on the space performance of NiMh batteries, solar cells, andadvanced electronic components.

2. SEASIS Specifications

Many design constraints were considered before finalizing on the SEASIS design.Table 1 Shows general information on processor performance and features. The mainobjective of SEASIS is to digitize from two CCD cameras, one which is fully calibrated.Also, select one of 12 filters from each, and control camera configurations to maximizedynamic range. Real-time video data compression is possible with the addition of thethree Analog Devices SHARC ADSP-21062 chips later discussed. Mass RAM isincluded to store large amounts of images - since the downlink on the SEDSAT is only at9600 and 57,600 bps. Processor computing capabilities are shown in Table 1.

Processors Clock MFLOPS MIPS SRAM DRAM Total SystemPower (Watts)

T805-20 20 Mhz 3.3 Peak 20 2 Mbyte SMI 128 Mbyte 0.7 to 5 Watts

3 AnalogDevicesSHARC DSP

40 Mhz 120Peak/each360 Total

512Kbyte on-chip SRAM(1.5MbyteTotal)

N/A 3 Watts Each

Table 1. SEASIS Processor Specifications

3. Processor Selection

Originally, DARPA donated an MCM (the SCC-100) with 3 ZORAN DSPs, aT805 Transputer, and 2 Mbytes of internal SRAM. Unfortunately, the bus design for the

ZORANs would be a great bandwidth constraint (lowering the MFLOP rating of theMCM to a fraction of its 100Mflops peak), and the system was not designed for ourpurpose. Also, the SCC-100 consumed over 5 watts of power, and was the only MCM ofits kind - making it almost impossible to have a ground system functionally identical.For this reason, we chose to re-design a lower power, more effective solution.

The heart of the SEASIS board is the 32 bit T805 processor by INMOS runningat 20 Mhz. The processor operates under watt under normal operations, hasmultitasking capabilities built-in, and has a long history of use in space applications. For

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memory, code and data both reside inside the 128MByte EDAC protected DRAMslinearly addressed memory space without the need for bank switching.

Internal to the T805 are 4 high speed serial links - one running to the CDS board(Command Data System board on the SEDSAT-1 which communicates to the groundstation) and the other three to the DSPs (see Figure 2). These links make thecommunications hardware easier to implement in the system since different sections canbe powered off. The three SHARC chips can be powered on separately under the T805software control, on an external expansion board. Each SHARC has access to one of theT805s 20MBit links for communications and bootup code. Once a SHARC chip ispowered on, it immediately accepts code over the link from the T805, and runs the codeonce the end is reached.

The SEASIS board can be reset from the CDS board under software control.Upon power-up of the SEASIS board, a power-on reset circuit gives maximum resettimings for all circuitry. After reset, the T805 polls the transputer links for bootup code.One of the links is connected to the CDS - allowing the CDS board to send bootup code

to SEASIS over the link, placing it in EDAC protected memory and then run oncecomplete.

Buffers

Shared Memory InterfaceShared Memory Interface

Digitizer and I/O PowerDigitizer and I/O Power

I/O Devices and

Camera Control Logic

T805

32 MB EDAC SIMM

32 MB EDAC SIMM

32 MB EDAC SIMM

32 MB EDAC SIMM

SEASIS PowerSEASIS Power

DRAM Logic

20Mbit

Data LinksTo DSPs

and to CDS

NTSCDigitizer 2

NTSCDigitizer 1

Video InVideo In

BuffersBuffers

512kx8

512kx8

512kx8

512kx8

Figure 2. SEASIS Processor Board Block Diagram

4. EDAC Mass Memory Design

Mass memory consists of 128 Mbytes of EDAC (Error Detection and Correction)DRAM (Dynamic RAM) comprising of 4 32 Mbyte SIMMs. DRAM requires

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refreshing (accesses to every row at intervals no greater than 32 ms) - and this isincorporated into the design external to the Transputer for robustness, even though theT805 does have some limited refreshing capabilities. The refresh design has no memorymapped registers, when the power is applied, the DRAMs are guaranteed refreshed untilpowered down. Also, by using a CBR refresh (CAS before RAS) cycle, powerconsumption is minimized and the address bus can remain tri-stated. When refreshing128 Mbytes, interleaving was chosen to minimize effects on the power bus. Instead ofrefreshing all 4 SIMMs (both sides) at once, they are refreshed separately anddistributed evenly (8 CBR cycles during each refresh interval) throughout the 32 ms.

Each SIMM is 36 Bits wide (4 for parity) and 32 for data bits - along with 4check bits for each byte. Each byte has a separate EDAC chip - correcting single biterrors in EACH byte (and some double bit errors) - while detecting single and double biterrors. A memory mapped register can be read by the Transputer to determine whensingle and double bit errors occur - to map error locations and generate SEU statistics.

Using a flow-thru EDAC chip such as the IDT 39C465, the SMI SRAM can be

EDAC protected during digitizing, as well as running code. Also, instead of using theIBM EDAC DRAMs for the mass RAM, the 32 Bit IDT EDAC chip has been designedto do read-modify-write cycle on SRAMs and could be modified for standard COTSJEDEC 72 Pin DRAMs. The T805 can vary its bus cycle write size, making it moredifficult to design a 32 bit EDAC memory system that generates code words for the full32 bits. Because of this, wait states would need to be added, or faster memory wouldneed to be selected. For this reason, SEDSAT chose to use the IBM EDAC byte-wideDRAMs which generate check bits for each byte, rather than for each word - eliminatingthe need for a read-modify-write cycle during a partial CPU write.

5. Video Digitizer Design

Incorporated in the SEASIS board are two NTSC video digitizers which cansample at speeds up to 20 Mhz. In our case, at 768x484 resolution, we need to sample atthe pixel clock rate of the CCDs (14.31818 Mhz) which is far within the specifications.Reference digitizing voltages can be set from software control, as well as the analogmultiplexer choosing between one of the four input video channels, allowing for a totalof 8 video inputs together, or redundant digitizers.

To digitize, the transputer flips a bit in a memory mapped register, causing theDigitizer to find the beginning of the image. Then, the digitizer starts digitizing into theSMI (Shared Memory Interface) SRAM. Once complete, the digitizer generates an

exception (interrupt) for the T805, signaling that the digitizing is complete. Up to fourclocks can be software selected (CCD clock, fixed oscillator, software clock, No clock).Selecting no clock will lower power consumption when the digitizers are powered on butnot digitizing.

6. Digital Signal Processing Capabilities

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Three SHARC DSPs were chosen for the ability of having redundantcomputations on each, storing their result in the internal SRAM on-chip (512kbyteseach). High speed links connect each DSP together, with speeds up to 240MByte/secondusing the internal DMA capabilities. Once each DSP has computed the result, each onewill transfer their result to the T805, and the T805 will compare their results to see if anySEU (Single Event Upsets) occurred, and in which DSP. Another option is to have allthree DSPs operating on different sections of the image, and to have it computed twicefor comparison on the T805. If the results are not the same, the T805 will compute whatisnt consistent again on the 3 DSPs until it finds a match. Since all software isuploaded to the SHARC chip upon power-on, any scenario can be programmed to ensuredata integrity.

7. Power Control Features

SEASIS can be powered on in a base configuration with all mass memoryrefreshed in under 1 watt. The CDS board on SEDSAT can power off SEASIS, or senda command to power different sections of SEASIS down when it detects a low power

state of the batteries on the satellite. Configuration possibilities and power consumptionare shown in Table 2.

Configuration Systems Active Power (W)

Minimum Mass RAM, CPU Idle 0.7

Running Mass RAM, CPU active 100% 3.5

Digitizing Mass RAM, CPU, all I/O andDigitizers

5.0

Cameras Stand-alone, each 3.0

Stepper Motor Single Stepper, single Phase energized 5.6

Table 2. Power Control Configurations

SEASIS always starts up in the base configuration with only the critical memoryand logic system enabled. All camera control logic, stepper motor control, and thedigitizers can be powered up and down under software control. The cameras, auto-irislenses, and stepper motors power can also be controlled independently to minimize totalpower consumption.

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8. Image Control Logic

SEASIS has two cameras mounted perpendicular on the experimental mountingplate (see Figure 3). One lens is a PAL (Panoramic Annular Lens), and the other is atelephoto with a field of view of approximately 10 degrees. The unique capability of the

PAL allows us to see 360 degrees around the lens, which will overlap the image from thetelephoto.

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Figure 3. SEDSAT Experimental Mounting Plate Drawing by John Bollich, UAH

The PAL CCD camera is flown in fully automatic mode - allowing the camera toselect shutter speed, iris setting, and gain automatically. Only the telephoto camera isrequired to be calibratable. For this reason, and because we arent able to read thesettings made in automatic mode from the lens and iris, we generate a calibratable systemby setting the options on the iris and lens under software control. A list of options andsettings is in Table 3.

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System Options Possible Settings

Lens Iris Control 14 Bit D/Afor 16,384 settings

Camera Shutter Speed 200 PWM Electronic SpeedsGain Control AGC/Fixed/Manual

Stepper Motor Phase A,B,C,D Pulsed to select one of 12 filters

Filter Wheel 12 Filters Optical encoders on wheel which can be read todetermine filter number

Table 3. Image Control Settings on SEASIS

Iris control can be controlled by means of outputting an analog voltage into theauto-iris lens from the D/A converter. This will allow variation in intensity undersoftware control, however, makes the system unable to be calibrated. Because of this,the iris will be flown on SEDSAT fixed completely open on the lens which requires

calibration, and only the gain and shutter speed will be configurable (as well as aselection of neutral density filters), which will give us enough dynamic range. Oursecond CCD camera will be flown completely automatically - CCD camera and auto-irislens since we have no need to calibrate.

9. Thermal Design

SEASIS is powered by Interpoint DC/DC converters, with maximum outputpower of 15 to 30 Watts, and efficiencies of around 75%. The DC/DC converters aremounted on the SEDSAT experiment mounting plate, located near the center of thesatellite. Our simulations and tests have shown this to be the coldest location in the

satellite, and an ideal location for our DC/DC converters. Three DC/DC converters areused, one for cameras (12VDC), one for SEASIS main power (5VDC), and one forstepper motor power (28VDC). All derive their power directly from the main satellitepower bus.

PCBs have ground planes located on the top and bottom of all boards in thesatellite, secured to the frame with wedge-locks. Our simulations and tests havedemonstrated that this is very effective at distributing heat evenly especially whenmaking good thermal contact to the body of the components (using a thermallyconductive, electrically non-conductive strip). Soldering was very tedious whensoldering pins to ground, so better heat relief was added on the solder side.

10. Radiation Considerations

Almost all of the hardware on SEASIS are commercial parts with radiationinformation available (see Table 4). One of the main exceptions are the A/D video chipschosen, which have no radiation information (Brooktree BT252). Because of the internal4 channel mux, and programmable voltage references, we chose to keep the BT252 in theSEASIS design since our orbit will give us a minimal radiation exposure level.

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However, we have redundant electronics for the video digitizers, and can havecomponents RAD-COATed ( Space Electronics, Inc.) to increase their life expectencyto over 100krad. Also, the HS9008-RH could be used in a future design where long-duration exposure at high doses exist in place of the BT252.

Part Number Description Latch up Threshold MeV/(mg/cm2)**

T805-20 Inmos 20Mhz Transputer 36

HM628512 512Kx8 SMI SRAM > 90

74 and 54 Series Discrete Logic >100

MTR2805S Interpoint 28-5V DC/DC >50

MTR2812S Interpoint 28-12V DC/DC >50

10.00Mhz Q-Tech Rad-Hard Oscillator >100

BT252HS9008-RH*

Brooktree A/DHarris Rad-Hard A/D

No Information Available>300

Table 4. Radiation Specifications

*Feasible replacement part for BT252 on new design.**Radiation information from http://www.dasiac.com, and Interpoint for DC/DCconverters.

11. Conclusion

The SEASIS design incorporates low cost, low power, and high performance. Inour planned low earth orbit, the life expectancy is 3 years. Alternative chips andpackaging methods can increase total dose survival rate on SEASIS to well over100krad, but was not feasible (due to funding), nor required for our mission.

Future designs will include a more modern microprocessor - the T805 is beingphased out. Possible replacements include the 486 or Pentium microprocessors with lowpower modes, and a VME bus interface. Also, new digital camera technologies couldallow for direct digital output instead of NTSC, simplifying the image capture hardware.These options will be more feasible once the technology is more mature, and a longerflight history is developed.

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