SDC vs. FDC

7/17/2019 SDC vs. FDC

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FDC and SDC Timing ConstraintsSynopsys Application Note, November 2012

Beginning with the G-2012.09 release, the Synopsys® Synplify® family of FPGA synthesis tools

uses a new consolidated scheme for handling constraints. This document reviews the different

formats used in the past, as well as the new approach to defining constraints with a single

consolidated file.

•Old Constraint Formats, on page 2

• New FDC Constraint File, on page 3

• Migrating Existing Constraints to FDC, on page 5

• Details of Constraint Conversion, on page 7

• Specifying Constraints in the SCOPE Editor, on page 10

• FDC SCOPE Tabs, on page 11

• Mixed Timing Constraints and Precedence, on page 16

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2 FDC and SDC Timing Constraints

Copyright © 2012 Synopsys, Inc. All rights reserved.

Old Constraint Formats

In releases before G-2012.09, there were two parallel, mutually exclusive formats for specifying

timing constraints, both of which used the sdc abbreviation and file extension:

• Synopsys standard timing constraints (sdc)Public domain Design Compiler® constraints, as defined in the Synopsys SDC Standard .

Typical constraints: create_clock, set_input_delay, set_false_path

• Synplify legacy timing constraints (sdc)Constraint format native to the Synplify tools. Typical constraints: define_clock,define_input_delay, define_false_path.

In addition, the FPGA synthesis tools honor design constraints. Design constraints are non-

timing constraints for FPGA synthesis; they include attributes (design_attribute constraints) and

physical constraints. These non-timing design constraints are always specified with the same

syntax, regardless of the selected timing constraint format.

In releases prior to G-2012.09, this meant that there were two mutually exclusive schemes for

specifying constraints, based on the timing constraint format used. You had a choice between

using the legacy Synplify-style format for both timing and design constraints, or using a combi-

nation of Synopsys standard timing constraints along with Synplify-style design constraints.

The following figure shows the two constraint scheme choices in previous releases, and the

formats of the resulting constraints:

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FDC and SDC Timing Constraints


New FDC Constraint File

The G-2012.09 release eliminates the confusion of multiple timing constraint formats. It intro-

duces a single file that consolidates both timing and non-timing constraints, called the FPGA

Design Constraints (fdc) file. Use this file in place of both the Synopsys standard and theSynplify-style legacy sdc constraint files.

The FDC file offers the following advantages:

• Sharing of the same ASIC-style timing constraints across FPGA and ASIC tools.

• Easier prototyping of ASIC designs as FPGAs.

• Vendor support, starting with Altera TimeQuest in Quartus and Xilinx Vivado for Virtex-7

devices.

Generating an FDC File

To generate the new fdc file, you can translate existing constraints or enter new constraints in

the SCOPE editor. The following figure summarizes the methods.

After running the sdc2fdc command to generate an fdc file, use the SCOPE editor or a text file

editor to check the translated constraints and edit as needed. See Migrating ExistingConstraints to FDC , on page 5 for details.

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FDC File Description

FDC constraints include timing and non-timing design constraints. The timing constraints area subset of the Synopsys standard timing constraints, along with some FPGA-specific exten-

sions. The FDC non-timing design constraints are the same as the legacy Synplify-style design

constraints. This table summarizes the syntax formats used in the fdc file:

The fdc file has a Tcl section and other sections that match the tabs in the SCOPE editor (see

FDC SCOPE Tabs , on page 11). The SCOPE sections are enclosed in Begin and End statements

that you can see if you open the file in a text editor. Translated constraints in the SCOPE

sections can be viewed and worked with in the corresponding tabs of the SCOPE editor. You

can also work with them in a text editor.

Anything that is not enclosed in Begin and End statements is part of the Tcl section and can be

viewed and worked with in the Tcl View tab of the SCOPE editor. This section includes

constraints that could not be translated or ones that need advanced constraining. This section

also includes -disabled constraints from the original sdc files.

Timing Constraints Non-Timing Design Constraints

Synopsys standard format: create_clock, set_input_delay,set_false_path...

Synplify-style format: define_attribute...

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Migrating Existing Constraints to FDC

For existing designs, you must do a one-time conversion of your existing constraint files to use

the new FDC format. If you are targeting a Xilinx 7 series device, migration is mandatory.

Synopsys provides the sdc2fdc translator utility to automate the conversion process as much aspossible.

Use this procedure:

1. Open an existing design and run the sdc2fdc translator from the tool Tcl window or in batch

mode.

– Type sdc2fdc in the Tcl window.

– Use the following command in batch mode. The batch command disables error

checking for qualifiers like p: and i:.

synplify -batch <prj_file> -tclcmd “sdc2fdc -batch”

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The command translates all valid enabled sdc files for the specified project and puts the

results into an fdc file called <design> _translated.fdc, located in the newly-created

<project_dir>/ FDC_constraints/<impl_name> directory.

If your design has compile points, the command creates a separate fdc file for each compile

point. All constraints might not be translated. It is up to you to review and set newconstraints as needed, using the methods described in the next few steps.

2. Review the untranslated constraints by double-clicking the *_translated.fdc file and going to

the Tcl View tab of the SCOPE editor when it opens. Manually edit the constraints as

needed.

This tab contains the untranslated constraints and other constraints that need manual

intervention. Alternatively, open the translated fdc file in a text editor, review the Tcl section

of the file and edit the constraints there. The other sections of the file match the SCOPE

tabs, and are enclosed in Begin and End statements.

3. Check the Tcl window or the _translate.log file in the FDC_constraints/<impl_name> directory

for conversion errors. Fix any errors.

This is an example from the _translate.log file:

ERROR: BAD -from list for define_false_path (my_inst)

Missing qualifier(s) (i: p: n: ...)

“define_false_path -from (my_inst) -to i:abc.def.g_reg -through (n:bar)”

Synplicity SDC source file: D:/timing_88/clk_prior/top.sdc. Line number: 79

If you run the design as is with the translated fdc file, the srr log file includes a similar error

message, but the file it points to is the pre-translation sdc file, not the converted fdc file.

4. Check the validity of the constraints with Run->Constraint Check or the Check Constraints button in the SCOPE editor.

This command generates a report that checks the syntax and applicability of the timing

constraints. It lists constraints that are not applied, valid constraints that cannot be

applied, constraints on objects that do not exist, and wildcard expansions of constraint

specifications.

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Details of Constraint Conversion

This section describes some aspects of constraint conversion in more detail:

• Legacy Synplify Timing Constraints, on page 7

• Synopsys Standard Timing Constraints, on page 7

• Clocks and Clock Groups, on page 8

• Groups and Collections, on page 9

• Non-Timing Design Constraints, on page 9

Legacy Synplify Timing Constraints

The fdc file uses the Synopsys standard syntax for its timing constraints. The sdc2fdc utility

translates legacy Synplify-style timing constraints into the Synopsys standard syntax. You can

view any constraints that were not translated in the Tcl View tab of the SCOPE editor.

The following table shows some of the common legacy constraints and their equivalents in the

new timing constraint scheme:

Synopsys Standard Timing Constraints

Constraints specified in the Synopsys standard format are preserved and written to the fdc fileas is, because the fdc constraint syntax is the same as the Synopsys standard constraint

syntax.

Legacy Synplify Constraint FDC Constraint/Synopsys Standard Constraint

define_clock set_clock, create_generated_clock, set_clock_groups, set_clock_route_delay

define_clock_delay set_false_path, set_max_delay

define_false_path set_false_path

define_multicycle_path set_multicycle_path

define_path_delay set_max_delay

define_input_delay set_input_delay

define_output_delay set_output_delay

define_reg_input_delay set_reg_input_delay (FDC constraint only)

define_reg_output_delay set_reg_output_delay (FDC constraint only)

set_datapathonly_delay set_datapathonly_delay (FDC constraint only)

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Clocks and Clock Groups

Clock constraints are more complicated to translate because of fundamental differences

between the clock scheme assumptions. Some of these problems and their resolution by the

conversion process are described below.

Clock Groups

FDC clock groups are the same as Synopsys standard clock groups, but the FDC treatment of

clock groups is different from the legacy Synplify timing scheme. This means that while clock

groups specified with the Synopsys standard syntax are not affected, automatically translated

legacy Synplify constraints must be reviewed to ensure the constraints you want are correctly

defined.

With the FDC syntax you can represent more clock relationships than you could with the

Synplify legacy clock group definitions, as shown by the preceding table.

The following example shows legacy clock group definitions and their translated FDC equiva-

lents:

Clock Constraint Application

With Synopsys standard and FDC timing formats, clock constraints are applied to the output

port of the clock object. By contrast, the Synplify legacy timing constraints let you attach clock

constraints to instances. For backwards compatibility, you can still place constraints on BUFG

instances in the Xilinx Vivado flow for example, but going forward, it is recommended that you

apply clock constraints to top-level design ports or output ports of clock objects.

Legacy Clock Group FDC/Synopsys Standard Clock Group

Default (no clockgroup specified)

Asynchronous clocks Synchronous clocks

User-specified clockgroups

Based on lineage.

If clkb and clkc are synchronous toclka, they are synchronous to eachother.

Associative.

If clkb and clkc are synchronous to clka,they need not be synchronous to eachother; they can be asynchronous.

Legacy

Definition

define_clock -name {clka} {p:clka} -period 10 -clockgroup default_clkgroup_0

define_clock -name {clkb} {p:clkb} -freq 150 -clockgroup default_clkgroup_1define_clock -name {clkc} {p:clkc} -freq 200 -clockgroup default_clkgroup_1

FDCDefinition

###==== BEGIN Clocks - (Populated from SCOPE tab, do not edit)create_clock -name {clka} {p:clka} -period 10 -waveform {0 5.0}create_clock -name {clkb} {p:clkb} -period 6.667 -waveform {0 3.3335}create_clock -name {clkc} {p:clkc} -period 5.0 -waveform {0 2.5}set_clock_groups -derive -name default_clkgroup_0 -asynchronous -group {c:clka}set_clock_groups -derive -name default_clkgroup_1 -asynchronous -group {c:clkb c:clkc}###==== END Clocks

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Generated Clocks

Most legacy Synplify-style clock constraints are translated to FDC constraints: define_clock constraints become FDC create_clock constraints. However, generated clocks defined withcreate_generated_clock constraints are preserved as is in the fdc file.

Groups and Collections

The Tcl find. expand, and define_scope_collection commands are unchanged, and you can use them

to create groups or collections of objects, as before. During the conversion process, the

synthesis tools automatically create some SCOPE collections: for -default options, and for find or

expand commands that are embedded in constraints.

Embedded get query commands, like get_cells, get_clocks, and so on, appear as constraints with

equivalent object qualifiers (i:, p:, n:, t:, c:).

Non-Timing Design Constraints

Legacy non-timing design constraints are preserved in the fdc file. For more detail about how

different constraints are handled, see Attributes, I/O Standards, and Compile Point Tabs , onpage 14. The define_scope_collection, find, and expand commands are preserved, but query

commands like the get* commands are not. See Collections Tab , on page 12 for details.

Constraint Conversion for Vivado Designs

If you are going to use the Xilinx Vivado place-and-route tool, you cannot use legacy-style

timing constraints, and must convert them to the FDC format. You can also enter constraints in

the correct format in the SCOPE editor.

Use the following guidelines when creating constraints for Vivado designs:

• Specify clock groups correctly, making sure to properly define the clocks that are synchro-

nous to each other. Unlike the previous ISE scheme, the default assumes that a clock is

synchronous with all other clocks.

• Apply clock constraints to the output port of the clock object or to the top-level design

ports. Prior practice allowed clock constraints to be applied to nets and to BUFG instances

directly. If you do place a clock constraint on a BUFG instance, as was the previous

practice with the ISE flow, the FPGA synthesis tools convert the constraint so that it is

applied to the output port of the BUFG, and it is forward-annotated as such to Vivado

place-and-route.

The FPGA synthesis tools write out the requisite xdc constraints file for Vivado. Like the fdc file,

this file includes timing constraints in the Synopsys standard format, as well as physical,

location, and IP constraints.

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Specifying Constraints in the SCOPE Editor

You can use the SCOPE editor to specify new constraints or edit existing constraints. If you

define new constraints directly in the SCOPE editor, the tool automatically saves them in an fdc

file.

1. To specify new constraints directly in the SCOPE editor, first compile the design and then

do one of the following:

– Select File->New-> FPGA Design Constraints, and then select FPGA Constraint File (SCOPE).Define timing and non-timing constraints as needed.

– Click the SCOPE icon in the toolbar, and select FPGA Constraint File (SCOPE). Define

timing and non-timing constraints as needed.

When you enter constraints in the tabs, the tool saves them into an fdc file. It is recom-

mended that you use the new SCOPE editor and the fdc file for all new designs. For

descriptions of the SCOPE tabs, see FDC SCOPE Tabs , on page 11.

2. For newly-translated fdc files, do the following:

– Double-click the fdc constraints file in the Project view, or use File->Open, specifying the

file type as FPGA Design Constraints File (*.fdc).

– Check the translated constraints and edit them as needed. Check the Tcl View tab in

particular, which contains the untranslated constraints. You can also use this tab to

manually add constraints that do not fit on the other tabs.

– Enter any other constraints you might need.

3. To open the SCOPE editor for existing constraints, double-click the fdc constraints file in

the Project view, or use File->Open, specifying the file type as FPGA Design Constraints File

(*.fdc).

For legacy designs with Synplify-style sdc constraint files, it is recommended that you

convert your design as soon as possible to the fdc format, as described in MigratingExisting Constraints to FDC , on page 5. You can then use the new SCOPE editor. If you

must open an old sdc file, double-click on it in the Project view.

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4. Check the validity of the constraints with Run->Constraint Check or the Check Constraints button in the SCOPE editor.

You get a report on the syntax and applicability of the timing constraints. The report lists

unapplied constraints, valid constraints that cannot be applied, constraints on objects

that do not exist, and wildcard expansions of constraint specifications.

FDC SCOPE Tabs

The following sections briefly describe the new FDC SCOPE tabs and point out any differences

from the legacy SCOPE editor.

• Clocks Tab, on page 11

• Generated Clocks Tab, on page 12

•

Collections Tab, on page 12• Inputs/Outputs Tab, on page 13

• Delay Paths Tab, on page 14

• Attributes, I/O Standards, and Compile Point Tabs, on page 14

• Tcl View Tab, on page 15

Clocks Tab

This tab defines the clocks, clock groups, uncertainty and latency. The options you specify here

are written out as constraints in the fdc file. If your translated design contained uncertainty andlatency constraints, they are included on Tcl View tab.

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Generated Clocks Tab

The options defined on this tab are written out as create_generated_clock constraints in the fdc file.

You must check valid parameter combinations on this tab yourself, as the tool does not

currently do this automatically.

Collections Tab

The Collections tab lists commands that designate groups or collections of objects. This function-

ality has been enhanced so that the tool now generates some default collections automatically.

The table summarizes the translated constraints on this tab and the fdc constraints that arewritten out.

Translated constraints onthis tab

Synplify-style legacy constraints: define_clock

Synopsys standard constraints: create_clock, set_clock_groups,set_clock_uncertainty, set_clock_latency

FDC file constraints

written out from this tab

create_clock, set_clock_groups, set_clock_uncertainty, set_clock_latency

Translated constraints onthis tab

Synplify-style legacy constraints: define_clock

Synopsys standard constraints: create_clock

FDC file constraintswritten out from this tab

create_generated_clock

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The following excerpt shows the relevant portion of an fdc file, with define_scope_collection commands:

###==== BEGIN Collections - (Populated from SCOPE tab, do not edit)

define_scope_collection {all_inputs_fdc} {find -port *-filter @direction==input}

define_scope_collection {all_outputs_fdc} {find -port *-filter @direction==output}

define_scope_collection {all_clocks_fdc} {find -hier -clock *}

define_scope_collection {all_registers_fdc} {find -hier -seq *}

define_scope_collection {fdc_cmd0} {find -seq -hier {q?[*]} }

define_scope_collection {fdc_cmd1} {find -seq {*y*.q?[*]} }

###==== END Collections

Inputs/Outputs Tab

This tab lists the input and output delays, but includes some new I/O options. For example, the Add Delay (-add_delay) option indicates that you do not want to overwrite existing delays on the

ports but add to them.

This is an example of how legacy definitions are translated to the fdc format on this tab:

Translated Synplify legacyconstraints on this tab

define_scope_collection

Embedded find and expand definitions

Automatically generatedcollections from legacyconstraints

define_scope_collection for all -default options like clocks, registers,inputs, outputs, etc.

Embedded find and expand definitions

Untranslated Synplifylegacy constraints

-disabled constraints


define_scope_collection


set_input_delayset_output_delay


define_input_delaydefine_output_delay

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Delay Paths Tab

This tab lists the timing exceptions. You can now specify timing exceptions for reset paths and

datapaths.

Attributes, I/O Standards, and Compile Point Tabs

These SCOPE tabs are unchanged from previous releases, and the non-timing design

constraints specified on them are preserved as is. When the constraints are written out to the

fdc file, their syntax is unchanged:

###==== BEGIN Attributes - (Populated from SCOPE tab, do not edit)

define_global_attribute {syn_global_buffers} {0}

define_attribute {i:modulex_inst.q[7:0]} {syn_pipeline} {1}

define_attribute {b:x[1]} {syn_loc} {AR20}

###==== END Attributes

###==== BEGIN ”I/O Standards” - (Populated from SCOPE tab, do not edit)

LegacyDefinition

define_input_delay -default 0.000 -improve 0.00 -route 0.00 -ref c:clka:f

define_output_delay -default 0.000 -improve 0.00 -route 0.00 -ref c:clka:r define_input_delay {a[7:0]} 2.00 -ref {clka:r}

FDC

Definition

###==== BEGIN inputs/Outputs - (Populated from SCOPE tab, do not edit)

set_input_delay {$all_inputs_fdc} -clock {c:clka} -clock_fall -add_delay {0.000) set_output_delay {$all_outputs_fdc} -clock {c:clka} -add_delay {0.000)

set_input_delay {p:a [7:0]} -clock {c:clka} -add_delay {2.00)

set_input_delay {p:rst} -clock {c:clka} -add_delay {0)###==== END Inputs/Outputs


define_multicycle_pathdefine_false_pathdefine_path_delay

FDC file constraints

written out from this tab

set_multicycle_path

set_false_pathset_max_delayreset_pathset_datapathonly_delay

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define_io_standard -default_input syn_pad_type {LVCMOS18} -delay_type {input}

###==== END ”I/O Standards”

###==== BEGIN ”Compile Points” - (Populated from SCOPE tab, do not edit)

define_compile_point {-v:work.cp3} -type {locked, partition} -cpfile {} define_compile_point {-v:work.cp1} -type {locked} -cpfile {}

###==== END ”Compile Points”

Tcl View Tab

This tab opens an editor window where you can manually edit the Tcl constraints that were not

translated or which need other manual intervention. Some constraints that often need manual

editing are set_clock_latency, set_clock_uncertainty, set_datapathonly_delay, define_reg_input_delay (legacy)

or set_reg_input_delay (fdc), and define_reg_output_delay (legacy) or set_reg_output_delay (fdc).

Check and edit the translated constraints on this tab as needed. If necessary, enter or edit

other constraints manually on this tab. When you are done, save the constraints and rerun

your design using the saved fdc file.

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Copyright © 2012 Synopsys, Inc. All rights reserved. Specifications subject to change without notice. Synopsys, DesignWare, SCOPE, SolvNet, Synplicity, the Synplicity logo, Synplify,Synplify Pro, and VCS are registered trademarks of Synopsys, Inc.,All other names mentioned herein are trademarks or registered trademarks of their respective companies.

Synopsys, Inc.700 East Middlefield RoadMountain View, CA 94043 USA solvnet.synopsys.com


Mixed Timing Constraints and Precedence

Your design can contain Synopsys standard sdc constraints as well as an fdc file with timing

constraints. With timing constraints in different files, this order of precedence applies:

• The tool ignores the file order listed in the project file, and first reads in all Synopsysstandard sdc files and applies those constraints. If you have multiple standard sdc files,

the files are read in the order listed in the project file.

• After all the standard sdc files are read, the tool reads in all fdc files. If you have multiple fdc files, the tool honors project file order.

The implication is that a conflicting constraint in an fdc file overwrites a preceding sdc constraint. If a period of 10 ns was defined for a clock port in the sdc file, and the fdc defines a

clock on the same port with a period of 12 ns (without using the -add argument), then the

second constraint from the fdc file applies.

Precedence does not affect legacy timing constraints, because they cannot be used in the same

design as fdc or Synopsys standard timing constraints without conversion. It is strongly recom-

mended that you convert legacy constraints to the fdc format, but even if you retain the old

format for an existing design, there is no conflict because they are not used with the other

constraints.

Documents

SDC vs. FDC