Scaling: history, Moore’s law, > Moore • Cores •ITRS •Roadmapspioneer.netserv.chula.ac.th/~ksongpho/584/1.pdf · • Scaling: history, Moore’s law, > Moore • Cores •ITRS

Faculty of Engineering, Chulalongkorn University

1 Introduction to Nano-electronics1. Introduction to Nano-electronics

• Scaling: history, Moore’s law, > Moore• CoresCores• ITRS• Roadmaps

R.H. Dennard’s scaling proposal

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History of product scaling

li ll dd d f t / f ti lit

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scaling allows added features / functionality


Scaling: size comparison

(yrs ago)60

30

1 m

10

now

1 nm1 nm

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Scaling: What for?Source: ITRS 2011, Fi

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ig. 9


Scaling requires expensive fabrication plants (fab)..so expensive that investment is very risky..competition / collaboration for the benefit of the entire

l h ivalue chain

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Cost per function: 25–29% reduction per year


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This will require innovations in cross-disciplinary fields, such as nano-electronics, nano-thermomechanics, nano-biology, extremely parallel software, etc.

• Moore’s Law—An historical observation by Gordon Moore, that the market demand (and semiconductor industry response) for functionality per chip (bits, transistors) doubles every 1.5 to 2 years. He also observed that device affordability must be taken into account and also performance. Although viewed by some as a “self-fulfilling” prophecy, “Moore’s Law” has been recently acknowledged and celebrated as a consistent macro trend and key indicator of

Moore s Law has been recently acknowledged and celebrated as a consistent macro trend and key indicator of successful leading-edge semiconductor products and companies for the past 40 years.

• Scaling (“More Moore”)—Geometrical (constant field) Scaling refers to the continued shrinking of horizontal and vertical physical

Geometrical (constant field) Scaling refers to the continued shrinking of horizontal and vertical physical

feature sizes of the on-chip logic and memory storage functions in order to improve density (cost per function reduction) and performance (speed, power) and reliability values to the applications and end customers.

Equivalent Scaling (occurs in conjunction with, and also enables, continued geometrical scaling) refers to 3-dimensional device structure (“Design Factor”) improvements plus other non-geometrical process techniques and new

i l h ff h l i l f f h himaterials that affect the electrical performance of the chip.Design Equivalent Scaling (occurs in conjunction with equivalent scaling and continued geometric scaling)

refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity. Examples: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-Vdd, etc ); and homogeneous and heterogeneous multicore SOC architectures ”etc.); and homogeneous and heterogeneous multicore SOC architectures.

• Functional Diversification (“More than Moore”)—The incorporation into devices of functionalities that do not necessarily scale according to “Moore's Law,” but provides additional value to the end customer in different ways. The “More-than-Moore” approach typically allows for the non-digital functionalities (e.g., RF communication, power

control, passive components, sensors, actuators) to migrate from the system board-level into a particular package-level (SiP) or chip-level (SoC) potential solution. Examples: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”

• Beyond CMOS—emerging research devices (ERD) and Materials (ERM), focused on a “new switch” used to process information, typically exploiting a new state variable to provide functional scaling substantially beyond that attainable by ultimately scaled CMOS. Substantial scaling beyond CMOS is defined in terms of functional density, increased performance, dramatically reduced power, etc. The “new switch” refers to an “information processing element or

7

y gtechnology,” which is associated with compatible storage or memory and interconnect functions.

Examples of Beyond CMOS include: carbon-based nano-electronics, spin-based devices, ferromagnetic logic, atomic switches, and nano-electro-mechanical-system (NEMS) switches.




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(GHz)

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(GHz)


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http://www itrs net/home html

The overall objective of the ITRS is to present industry-wide consensus on the “best current estimate” of the industry’s research and development needs out to a 15-year horizon As such it provides a guide to the efforts of companies universities

http://www.itrs.net/home.html

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horizon. As such, it provides a guide to the efforts of companies, universities, governments, and other research providers or funders.


The progress of the semiconductor industry requires a neutral body to set technological q y gmilestones (roadmap).

Hence, the birth of ITRS

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Review: yearlyPublication: every 2 years (2011, 13, 15, ...)


ITRS: how it works

ITRS: the players (2005 data)

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“Time of Introduction”Time of Introduction

15-year planning:- Near-term: 7 years- Long-term: 8 years

material

possibility of III/V Ge technology acceleration to 2015

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possibility of III/V Ge technology acceleration to 2015


A roadmap has a time axis. The ITRS refers to time by:- Year of Production (starting ITRS 2007)Year of Production (starting ITRS 2007)- technology node: half-pitch (HP) (upto ITRS 2005)

Half-Pitch = Pitch/2

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Faculty of Engineering, Chulalongkorn Universityble

BTR

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11, T

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: IT

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ITRS 2011ITRS 2011Nanotechnology: size in one or moreNanotechnology: size in one or more dimension within 1-100nmNanoelectronics: began in 1999

Source: IT

(ก) (ข)(ก) (ข)

TRS 2011, Figg. ORTC 3-4

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MPUFLASH

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2010: Intel® Itanium® processors (Tukwila) 2-billion transistor microprocessor

Source: ITRS 2011, Tables ORCT7-8


Technology Cycle TimingFab distributionFab distributionNew fab: CPU, DRAM, FlashOld fab: logics, other commodity chips

S Kanjanachuchai 19Source: ITRS 2011, Figure 4



• Scaling: history, Moore’s law, > Moore• CoresCores• ITRS

System Drivers and DesignTest and Test EquipmentProcess Integration, Devices and Structures (PIDS)Radio Frequency and Analog/Mixed-Signal Technologies (RF/AMS)

• Roadmaps Microelectromechanical Systems (MEMS)Emerging Research Devices (ERDs)Emerging Research Materials (ERMs)Front End Processes (FEP)LithographyInterconnectFactory IntegrationAssembly and Packaging (AP)Environment, Safety, and Health Yield EnhancementMetrologyModeling and Simulation

S Kanjanachuchai 20design RF/AMS FEP PIDS Lith Intercnx A&P MEMS test metrology ERD ERM


Why does design cost tend to increase and what can be done?tiDesign

design RF/AMS FEP PIDS Lith Intercnx A&P MEMS test metrology ERD ERM

- time = money- design time depends on complexity- design time can be reduced by block re-use (copy & paste) IP very important

Design

SSource: ITRS 2011, Figure DESN3-4

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- Design productivity cannot catch up with HW improvement.- In-house chip designs are replaced by system-on-chip (SOC) and system-in-package (SIP) designs that incorporate building blocks from multiple sources.

Faculty of Engineering, Chulalongkorn UniversitySSource: ITRS 2011, Figure DESN13

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Stationary

SOC die size constant at 220mm2

DPE: Data Processing EngineDPE: Data Processing Engine

Portable

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GDSII : (Graphic Data System) a database file format; de facto industry standard for data exchange of IC layout artworkRTL: register transfer level


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RF / AMS


RF / AMS

RF/AMS (RADIO FREQUENCY AND ANALOG/MIXED SIGNAL)RF/AMS (RADIO FREQUENCY AND ANALOG/MIXED-SIGNAL):

1. Low-noise amplifier (LNA) amplifies the input signal (LTE, W-CDMA, WLAN, GPS, Bluetooth...) to a level that makes further signal processing insensitive to noise.

2. Voltage-controlled oscillator (VCO), key to phase-locked loop (PLL), which synchronizes communication between an integrated circuit and the outside world in high-bandwidth and/or high-frequency applications. Key design objectives: minimize phase noise and power consumption.

3. Power amplifier (PA), key components in the transmission path of wired or wireless communication systems. Key design objectives: high linearity to minimize adjacent channel power. Important devices: CMOS PAs, SiGe HBTs, III-V.

4. Analog-to-digital converter (ADC), digital meets analog @ A/V interfaces, interfaces to magnetic and optical storage media, and interfaces to wired or wireless transmission media.

5 S i li d i li (S D ) k t i i li d fib ti i ti t i l d5. Serializer-deserializer (SerDes) key component in wire line and fiber optic communication systems; includes multiplexer, demultiplexer, a (clock and data recovery circuit) CDR and a (clock multiplication unit) CMU. Goals: maximize data rate, while reducing power consumption for a given Mux-DeMux ratio.

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Front-End Process


Front End Process

FEP roadmap focuses on future process requirements and potential solutions related to scaled field effect transistors (MOSFETs), DRAM storage capacitors, and non-volatile memory (Flash, Phase-change, and ferroelectric).

Source: ITTRS 2011, Fig. FEP

Each structure (A-J) has its own roadmap.

P1

Memory status 2011- DRAM: MIM structure HKDRAM: MIM structure, HK- Flash: HK will be required for the floating gate Flash memory interpoly dielectric by 2012 and for tunnel dielectric by 2013- PCM: commercial production, although not in wide usage- FeRAM: will make a commercial appearance where ferroelectric and f ti t t i l ld b d

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ferromagnetic storage materials would be used


MOSFET

NMOS

MOSFETrealitytextbook

PMOSamorphous

SiO2

degenerately dopedpoly-Si2 p y

45nm65nm 45nm2007 201065nm

crystalline-Si

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http://www.solid-state.com/display_article/310335/5/none/none/CHIPF/SST-November-2007:-Intel's-evolution:-Strained-silicon-to-high-k-and-metal-gat


450mm roadmap

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A

[C3]

S Kanjanachuchai 32Source: ITRS 2009, Fig. FEP15 = ITRS2011, Fig. FEP17


JFlashFlash

DRAMDRAM

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E

F

E

B

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Process Integration Devices & Structures


Process Integration, Devices & StructuresProvide physical and electrical requirements and solutions for sustaining IC scaling in digital logic technologies and memory technologies

PIDS1: Scaling of Transistor Intrinsic Speed of High-Performance Logic

non-Si:

of High Performance Logic

Source: ITRS 2011, Fig. ORTC5

n(InAs) = 22,600 cm2/Vsn(Si) = 1,350 cm2/Vs

Table PIDS1aMultiple major changes are projected over the next seven years, such as.:

Material: high-κ gate dielectric, metal gate electrodes, lead-free solder

P : l t d S/D ( l ti i) d d d li d d i t h i

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Process: elevated S/D (selective epi) and advanced annealing and doping techniques

Structure: ultra-thin body (UTB) fully depleted (FD) SOI, multiple-gate MOSFETs, multi-chip package modules


[A]

[B]what cause the leak?- [C2]GHz

* slowdown of GHz* beginning of “multi-cores”

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(Vertical) scaling results in increased leakage power (in absolute term [A] and relative to total power [B]). Several techniques can be used to slow down this increase, see PIDS roadmap next page...


22

22 TGSN

TGSo

satD VVkVVLWCI

[C2-C4]

mobility (cm2/V-s)

HKMG

electrons holes

Si 1,350 480

Ge 3,900 1,900

CNT

InAs 22,600 200

GaSb 5,000 1,000

GaAs 8,500 400 Sourc

[C7]

nanologic[C4a]

ce: ITRS2011, Fig.

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PIDS3


(SiO2) = 3.9C = A/d

Sourc

nanomemory[C4b]

ce: ITRS2011, Fig.

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[C4b] PIDS4

Faculty of Engineering, Chulalongkorn UniversitySoource: ITRS2011, Fiig. FEP12

Flash families

Source: Micron Source: I

nanomemory[C4b]

Flash families- NAND: data storage- NOR: code storage (embedded systems)

TRS2011, Fig. PID

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DS10


Lithography


Lithography Current status: ArF, 193 nm

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AcronymsAcronymsImm: immersionDP: double patterningEUV: extreme ultravioletML2: maskless lithographyML2: maskless lithographyImprint: imprint lithographyDSA: directed self-assembly

Source: ITRRS2011, Fig. LITH3

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3A/3B


Interconnect I t t i i t th t di t ib t l k / th i l t th i f ti l bl k


Interconnect Interconnect: wiring system that distributes clock /other signals to the various functional blocks of a CMOS integrated circuit, along with providing necessary power and ground connections.

Goal: propagating terabits/second at femtojoules/bit

(PMD)

S Kanjanachuchai 42ทรานซิสเตอรทรานซิสเตอร

Source: ITRS 2009, Fig. INTC5


TSV: Through silicon via = connection between the two sides of a Si wafer that is electrically isolated from theTSV: Through silicon via connection between the two sides of a Si wafer that is electrically isolated from the substrate and from other TSV connections. The isolation layer surrounding the TSV conductor is called the TSV liner.

TSV is used for 3D-WLP (Wafer-level Package), 3D-SOC (System-on-Chip), and 3D-SIC (Stacked Integrated Circuit) interconnect technologies.te co ect tec o og es.

S Kanjanachuchai 43Source: ITRS 2009, Fig. INTC1


Scaling results in increased delay time due to increased resistivity of i t t ( t i i f t ) d itinterconnect (extrinsic factor) despite reduction in gate delay time (intrinsicfactor). This limits max bandwidth and bit rates.a es.

dA

ALRC

dA

!

m1065.2 8Al

93)SiO(cmμ 1.7m1070.1

m1065.2

2

8Cu

Al

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0.3)low(9.3)SiO( 2

kr

r

Faculty of Engineering, Chulalongkorn UniversityRC

RRAcronymsECD: electrochemical depositionCVD: chemical vapour depositionPVD: physical vapour deposition

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Source: ITRS 2009, Fig. INTC13


C

RC

max k (SiO2) = 3.9( )C min k (vacuum) = 1

S Kanjanachuchai 46Source: ITRS 2009, Fig. INTC7


"With the theoretical minimum of k i i h l i l k

Ultimate low k

Ak=1, air is the ultimate low-k material, which makes air gaps the dream of any interconnect researcher.

dAC

This microprocessor cross-section shows empty space in between the chip’s wiring. These “air gaps” —actually filled with a vacuum rather than air —

reduce capacitance, thereby increasing signal speed by 35% and reducing power consumption by 15%.

(Source: IBM)

Semiconductor International 7/1/2007Semiconductor International, 7/1/2007

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Assembly & Packaging = final manufacturing process transforming semiconductor devices into


Assembly & Packaging g p gfunctional products for end users. Packaging provides electrical connections for signal transmission, power input, and voltage control. It also provides for thermal dissipation and the physical protection required for reliability.

Scaling results in smaller chips with increased number of I/O pins. The A&P industry has to adapt to the smaller footprints11

, Fig.

TST

6So

urce

: ITRS

201

Lowest cost: SoC, but usually limited by material issues (different substrates) hence next best alternative is SiP

... these new devices will not have all the properties of CMOS devices Heterogeneous integration

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(different substrates), hence, next best alternative is SiP.of CMOS devices. Heterogeneous integration around a CMOS core at the chip/package level.


Wire Bondings:

Wire bond and flip chip are the two standard processes to connect die to a substrate.

Flip chip:Wire Bondings:Au - requirements for finer pad pitch spacing led to development for finer diameter gold wire. 16 m Au wire in qualification; 12 m in development.Cu - 18 m in use; Pd-coated

Flip chip:

Cu 18 m in use; Pd coated

S Kanjanachuchai 49Source: ITRS 2009


System in Package (SiP): systems level integrationSystem in Package (SiP) is a combination of multiple active electronic components of different functionality, assembled in a single unit, which provides multiple functions associated with a system or sub-system. A SiP may optionally contain passives, MEMS, optical components, and other packages and devices.

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SiP: categories

Source: ITRS 2009

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SiP: PIP/POP

CF, SD, USB

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ITRS 2008 Update: Optical interconnect on chip and chip to chip within a SiP has been added as a volume technology in 2011.

Communication between chips will migrate to "optical" mode in free space

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256 1Gbps


MEMS Micro Electro Mechanical Systems (MEMS) are devices that are fabricated using techniques similar to


MEMS Micro-Electro-Mechanical Systems (MEMS) are devices that are fabricated using techniques similar to those used for integrated circuits (ICs). They are composed of micrometer-sized mechanical structures (suspended bridges, cantilevers, membranes, fluid channels, etc.) and often integrated with analog and digital circuitry. MEMS can act as sensors, receiving information from their environment, or as actuators responding to a decision from the control system to change the environmentactuators, responding to a decision from the control system to change the environment.

Accelerometer

i b h i

Gyroscopes

l t i t bilit

Si Microphones

ll b tt

RF MEMS

t l

Emerging

O ti l Filt• airbag crash sensing• rollover detection• electronic stability

controls• motion and tilt

• electronic stability control

• rollover prevention• GPS navigation• early 2000s

• smaller, better acoustic than Electret Condenser Microphone (ECM)

• thin, surface-

• resonators: replace quartz oscillator in clock and timing applications

• contact switches:

• Optical Filters• Picoprojector• Electronic Nose• Microspeakers• Ultrasound Devicesmotion and tilt

sensing• 3-axis MEMS

accelerometer (Wii, iPhone)

• late 1990s

early 2000smountable

• analog (2003-2005)• digital (2006)

front-end wireless• varactors/capacitive

switches: front-end wireless systems

Ultrasound Devices

• late 1990s

10 degree-of-freedom (DOF) MEMS inertial measurement units (IMUs)

ADIS16407 Ten Degrees of Freedom Inertial Sensor

(2011)

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(2011)


Test & Test Equipment


Test & Test Equipmentmission: screening defects, speed binning or speed classification, reliability and yield learning--in order to decrease device Time-to-Market.

Key Drivers:

Source: ITRS 2

Key Drivers:• Increasing device interface bandwidth (# of signals and data rates)• Increasing device integration (SoC, SiP, MCP, 3D packaging)• Integration of emerging and non-digital CMOS technologies• package form factor, electro-mechanical & thermal characteristics

2011, Fig. TST13

• non-deterministic device behaviors (self-repair and correction)• multiple I/O types and power supplies on same device• fault tolerant device

Scaling results in more transistors in smaller space debug very difficultSmaller pins required to fit within tighter mechanical constraints will greatly increase contact resistance and signal

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Scaling results in more transistors in smaller space debug very difficult.IC testing has to be done by non-human and a fraction of chip area has to be dedicated to test structures (DFT)

constraints will greatly increase contact resistance and signal integrity issues. Contact force per pin 20 ~ 30 grams insure low contact resistance.


Source: ITRS 2011, Fig. TST9

Gbps interface standards: PCIe, hyper-transport, QPI, GDDR, DisplayPort, DDR, USB, Infiniband, SATA, SAS,

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Fiber channel, Gigabit Ethernet, XAUI, SONET, OTU, and OIF/CEI50 Gbps: chip-to-chip, chip-to-module interfaces will use optical signaling and optical fiber as the media (vs Cu,

loss 5dB/in at 25 GHz, max reach distance 10", shorter than backplane.


management talk:yield (=profit)

Improve productivity by wafer level burn-in test (WLBI)time-to-market

Souurce: ITRS 2011, Fiig. TST11

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Metrology Metrology is defined as the science of measurement.


Metrology Metrology is defined as the science of measurement. Metrology methods must routinely measure near and at atomic scale dimensions.

Critical Dimension (CD) Metrology Lithography Metrology

2011

, Fig.

MET

1

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ce: IT

RS 2


Microscopes typically employ light, electron beam, or scanned probe methods.

Electron Microscopy:FEP Metrology: Material Metrology

[C6]

Electron Microscopy:- SEM: scanning electron microscopy- TEM: transmission electron microscopy- STEM: scanning transmission electron microscopy

electron holography- electron holography- LEEM: low-energy electron microscopy

FEP Metrology: Stess Metrology

ET2

ITRS

2011

, Fig.

ME

Sour

ce:

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Source: ITRS 2011, Fig. MET4


E i R h D i & M t i l


Emerging Research Devices & MaterialsEmerging Research Devices (ERDs): devices for information processing and memory, new technologies for heterogeneous integration of multiple functions, and new paradigms for systems architecture.Emerging Research Materials (ERMs): materials with controlled properties that will enable operation of ERDs in highEmerging Research Materials (ERMs): materials with controlled properties that will enable operation of ERDs in high density at the nanometer scale.

QCA[C10]

[C4]

[C7] CNT

QDs

spintronics

S Kanjanachuchai 60Source: ITRS 2011, Fig. ERD2


ERDs: MemoriesERDs: Memories

Devices• Ferroelectric

Select Devices• 3-terminal (vertical

– Ferroelectric FET – Ferroelectric polarization

R RAM

transistors)• 2-terminal (resistance-

ReRAM• Nanoelectromechanical

memory (NEMM)

based memories)– Diode-type

R i ti t : M t lmemory (NEMM)• Redox Memory• Mott Memory

– Resistive-type: Metal-insulator (Mott) transition, threshold switch, threshold • Mott Memory

• Macromolecular/molecular Memory

switch, mixed ionic and electronic conduction (MIEC) switch.

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Memory

61


ERDs: Logic Beyond CMOSERDs: LogicExtending CMOS Charge Non-chargeg

•Carbon nanotube (CNT) FETs

g

•Spin FET and spin MOSFET T i t

g

•Spin wave devices (SWD)

•Graphene nanoribbon (GNR) FETsN i (NW)

Transistors•Impact ionization

MOS (IMOS)N i

•Nanomagnet logic (NML)

•Excitonic field-effect i (E FET)•Nanowire (NW)

FETs•n-channel III-V

•Negative gate capacitance FET

•Micro/Nano-Electro-M h i l

transistor (ExFET)•Bilayer pseudo-spin

field effect transistor (BiSFET)•p-channel Ge

•Tunnel FETsMechanical (M/NEM) Switches

•Atomic switchMOTT FET

(BiSFET)•Spin torque majority

logic gateAll i l i (ASL)1 •MOTT FET •All spin logic (ASL)

RS 20

11, F

ig. E

RD

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Sour

ce: IT

R


to replace MOSFET

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2 RM14

S 20

11, T

ab. E

RM2

TRS

2011

, Tab

. ER

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Sour

ce: IT

R

Sour

ce: I


Summaryy• Scaling

– macro-trend: Moore’s law for over 4 decades– macro-trend: Moore s law for over 4 decades– geometrical scaling:

• Moore’s law: #FET(M+18 ) = 2*#FET(M)HP(N+1) 0 7*HP(N)• HP(N+1) = 0.7*HP(N)

• Y(N+1) = Y(N) + 3– equivalent scaling (strained Si…)– design equivalent scaling (cores…)

• Functional Diversificationmulti physics– multi-physics

• ITRS– roadmaps for development / commercialisation of semiconductor devicesp p– adopted by all in the electronic industry– 16 roadmaps ranging from materials to devices, manufacturing, test...

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Documents

Scaling: history, Moore’s law, > Moore • Cores •ITRS •Roadmapspioneer.netserv.chula.ac.th/~ksongpho/584/1.pdf · • Scaling: history, Moore’s law, > Moore • Cores •ITRS