SC4612 Wide Input Range High Performance Synchronous Buck …u.dianyuan.com/bbs/u/32/1123661858.pdf · 2020. 5. 12. · Psarameter Tnest Condition Mpi Txy Msa Unit Power Supply VDD

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SC4612Wide Input Range High Performance

Synchronous Buck Switching ControllerPOWER MANAGEMENTDescription Features

Applications

Typical Application Circuit

Wide input power voltage range, 4.5V to 40VInternally regulated DRVOutput voltage as low as 0.5V1.7A output drive capabilityAsynchronous start up modeLow side RDS-ON sensing with hiccup mode currentlimitProgrammable current limitHigh side overcurrent protection at Asynchronousstart-upProgrammable frequency up to 1.2 MHzSmall power package MLP-12

SC4612 is a high performance synchronous buck controllerthat can be configured for a wide range of applications.The SC4612 utilizes synchronous rectified buck topologywhere high efficiency is the primary consideration. SC4612is optimized for applications requiring wide input supplyrange and low output voltages down to 500mV.

SC4612 implements an asynchronous soft start mode,which keeps the lower side MOSFET off during soft start, adesired feature when a converter turns on into a presetexternal voltage or pre-biased voltage. With the lowerMOSFET off, the external bus is not discharged, preventingany disturbances in the start up slope and any latch-up ofmodern day ASIC circuits.

SC4612 comes with a rich set of features such as regulatedDRV supply, programmable soft start, high current gatedrivers, internal bootstrapping for driving high sideN-channel MOSFET, shoot through protection, RDS-ON sensingwith hiccup over current protection, and asynchronous startup with over current protection.

Distributed power architecturesTelecommunication equipmentServers/work stationsMixed signal applicationsBase station power managementPoint of use low voltage high current applications

Revision: July 25, 2005

Q1

Q2

L1

C8

C10

+

_

+

_

Vin

Vout

R4

R5

C5

R2

C1

C9

C2

R6

C3

D1

C7C4

R3R1

R7C6

ILIM1 PHASE 12

OSC2

SS/EN3

FB5

VDD6 GND 7

DL 8

DRV 9

BST 10

DH 11

EAO4

U1SC4612MLP

2 2005 Semtech Corp. www.semtech.com

SC4612

POWER MANAGEMENTAbsolute Maximum Ratings

retemaraP lobmyS mumixaM stinU

DNGotegatloVylppuS DDV 03ot3.0- V

DNGotVRD 01ot3.0- V

)kaep(tnerruCecruoSVRD 57± Am

DNGot,MILI 01ot3.0- V

DNGotCSO,BF,NE/SS,OAE 5+ot3.0- V

DNGotLD 01+ot3.0- V

ESAHPotTSB 01+ot3.0- V

DNGotESAHP NIV 04+ot2- V

ESAHPotHD 01+ot3.0- V

tneibmAotnoitcnuJecnatsiseRlamrehT )1( θ AJ3.54 W/C°

egnaRerutarepmeTnoitcnuJgnitarepO TJ 521+ot04- C°

egnaRerutarepmeTegarotS T GTS 051+ot56- C°

).ceS01(erutarepmeTwolfeRRI T wolfeRRI 062+ C°

)ledoMydoBnamuH(gnitaRDSE DSE 2 Vk

All voltages with respect to GND. Positive currents are into, and negative currents are out of the specified terminal. Pulsedis defined as a less than 10% duty cycle with a maximum duration of 500ns. Consult Packaging Section of Data sheet forthermal limitations and considerations of packages.

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified inthe Electrical Characteristics section is not implied.

Note:(1). 1 sq. inch of FR-4, double-sided, 1 oz copper weight.


SC4612

POWER MANAGEMENT

VIN = VDD = 12V, FOSC = 600kHz, Phase to GND < 100mV (No low side current limit condition present) , TA = TJ = -40°C to 125°C.Unless otherwise specified:

retemaraP snoitidnoCtseT niM pyT xaM stinU

ylppuSrewoP

DDV 82 V

tnerruCtnecseiuQ V DD 0=NE/SS,daoloN,V21=5 Am

V DD 0=NE/SS,daoloN,V82=

tuokcoLegatlovrednUDDV

dlohserhTtratS 02.4 05.4 08.4 V

siseretsyHOLVU 004 Vm

VRD V01 ≤ V DD ≤ I,V82 TUO ≤ Am1 3.7 8.7 3.8 V

rotallicsO

egnarycneuqerFnoitarepO 001 0021 zHk

ycaruccAlaitinI )1( C CSO Fp081= 045 006 066 zHk

elcyCytuDmumixaM 09 %

yellaVotkaePpmaR )1( 058 Vm

tnerrucegrahCrotallicsO 09 011 Aµ

Electrical Characteristics

Note:(1). Guaranteed by design.


SC4612

POWER MANAGEMENT


)nosdRediSwoL(timiLtnerruC

egatloVdlohserhTtimiLtnerruC V TUO V5,V3.3,Vm005= 001 Vm

reifilpmArorrE

egatloVkcabdeeF TA C°52= 594.0 005.0 505.0 V

TJ C°521+ot04-= 884.0 005.0 215.0 V

tnerruCsaiBtupnI V5.0=BF 002 An

niaGpooLnepO )1( 06 Bd

htdiwdnaBniaGytinU )1( 7 01 zHM

tnerruCkniStuptuO V0=BF,pooLnepO 009 Au

tnerruCecruoStuptuO V6.0=BF,pooLnepO 0011 Au

etaRwelS )1( 1 su/V

NE/SS

egatloVdlohserhTelbasiD 005 Vm

tnerruCegrahCtratStfoS 52 Aµ

tnerruCegrahcsiDtratStfoS )1( 1 Aµ

nwoDtuhSotwoLelbasiD )1( 05 Sn

pucciH

elcycytudpucciH C SS ,1.0=noitidnoctimiltnerruc 1 %

Electrical Characteristics (Cont.)Unless otherwise specified:


VIN = VDD = 12V, FOSC = 600kHz, Phase to GND < 100mV (No low side current limit condition present) , TA = TJ = -40°C to 125°C.


SC4612

POWER MANAGEMENT


evirDetaG

)H(ecnatsiseR-nOevirDetaG I ECRUOS Am001= 4 Ω

)L(ecnatsiseR-nOevirDetaG I KNIS Am001= 4 Ω

tnerruCkniS/ecruoSLD Fp0002=TUOC 4.1± 7.1 A

tnerruCkniS/ecruoSHD Fp0002=TUOC 4.1± 7.1 A

emiTesiRtuptuO Fp0002=TUOC 02 sn

emiTllaFtuptuO Fp0002=TUOC 02 sn

palrevO-noNmuminiM )1( 03 sn

emiTnOmuminiM 001 sn

Unless otherwise specified:


Electrical Characteristics (Cont.)

VIN = VDD = 12V, FOSC = 600kHz, Phase to GND < 100mV (No low side current limit condition present) , TA = TJ = -40°C to 125°C.


SC4612

POWER MANAGEMENTTiming Diagrams

SS/EN2.75V

EAO

DH

DLSoft Start Duration

Asynchronous Operation

0.5V0.8V

1.3V

VCCVcc

UVLO4.58V

No fault start up sequence

SS/EN2.75V

EAO

DH

DL

0.5V0.8V

1.3V

VCCVcc

UVLO4.58V

Over current fault at Asynchronous start up sequence

Faultoccur

EOA<FB+0.7V

Soft Start Duration

Asynchronous Operation

Fault removed,normal operation resumed

Faultpresent for10 cycles


SC4612

POWER MANAGEMENT

rebmuNtraP egakcaP )1( T(egnaR.pmeT J)

TRTLM2164CS )2( 21-DPLM C°521+otC°04-

Pin Configuration Ordering Information

Notes:(1) Only available in tape and reel packaging. A reelcontains 2500 devices.(2) Lead free product. This product is fully WEEE andRoHS compliant.

1

2

3

4

5

6 7

PHASEI_LIMIT

TOP VIEW

(12 Pin MLPD)

12

8

DHOSC

BSTSS/EN

DRVEAO

DLFB

GNDVDD

10

9

11

Top Mark

Marking Information

Marking for the 4x3 MLPD 12 Lead package:nnnn = Part Number (Example: 1531)yyww = Date Code (Example: 0012)xxxxx = Semtech Lot No. (Example:E9010)

4612yywwxxxxx


SC4612

POWER MANAGEMENT

ILIM (Pin 1) :

The current limit programing resistors (R2 & R3) in con-junction with an internal current source, program the cur-rent limit threshold for the low side MOSFET RDS-ON

sensing. Once the voltage drop across the Low sideMOSFET is larger than the drop across the programmedvalue, current limit condition occurs, and the hiccup cur-rent limit protection is activated.

OSC (Pin 2) :

Oscillator Frequency set pin. An external capacitor to GNDwill program the oscillator frequency. The formula belowcan be used to approximate the Oscillator Frequency:

OSCOSC CF

610111 −×≅

SS/ENA (Pin 3) :

Soft start pin. Internal current source connected to a singleexternal capacitor will determine the softstart duration forthe output. Inhibits the chip if pulled down.

SS

SSSS I

2.1XCT ≅

EAO (Pin 4) :

Error Amplifier output. A compensation network is con-nected from this pin to FB.

FB (Pin 5) :

The inverting input of the error amplifier. Feedback pin isused to sense the output voltage via a resistive divider.

VDD (Pin 6) :

Input supply ranging from 4.5V to 28V, VDD pin is initiallyused to provide the base drive to the internal pass transis-tor to regulate the DRV.

GND (Pin 7) :

The sensitive internal circuitry as well as the return of theMOSFET gate drive currents are referenced to this pin.Proper layout guidelines (detailed explanation in the lay-out guide line section) should be followed to improve noiseimmunity.

DL (Pin 8) :

DL signal (Drive Low). Gate drive for bottom MOSFET.

DRV (Pin 9) :

DRV supplies the output MOSFETs gate drive, and the chipanalog circuitry. This pin should be bypassed with a 2.2µFceramic capacitor to GND. DRV is internally regulated fromthe external supply connected to VDD. If VDD is below 10V ,the supply could be directly connected to the DRV pin.

BST (Pin 10) :

BST signal. Supply for high side driver; can be directly con-nected to an external supply or to a bootstrap circuit.

DH (Pin 11) :

DH signal (Drive High). Gate drive for top MOSFET.

PHASE (Pin 12) :

The return path for the high side gate drive, also used tosense the voltage at the phase node for adaptive gate driveprotection, and the low-side RDS-ON voltage sensing.

THERMAL PAD: Pad for heatsinking purposes. Connect toground plane using multiple vias.

Pin Descriptions


SC4612

POWER MANAGEMENTBlock Diagram

OCP @ Asynchronous Start up

EAO > FB + 0.7

True

False

for more than 10cycles

AllowSynchronous

mode

Soft StartCycle

PWMEnable

Vcc UVLO

SS

+-

800mV

PWMDisable

Vcc UVLO

+-

Over Voltage Protection

S QR

FB

600mV20% OVP

Low Side 100% on

Top Side offPWM

Enable

+-

FB

Vref

SynchronousMode

S QR

PWMEnableLow Side

Rdson OCP S QR

PWMEnable

PWMDisable

+-

SS

Vref+0.5

REF

INTERNAL REGULATOR&

BANDGAP GENERATOR

VDD

DRV

GND

Oscillator

900mV

OSC

CurrentLimit

ILIM

SOFT START&

EnableSS/EN

TOP SideGate Driver

BST

DH

PHASE

PWM Control

Low Side Gate Driver

VCC

DL

GND

BST

DH

PHASE

DL

+-

ErrorAmp.

FB

SS

FB

+-

EN SYNC

OCP

SynchronousMode

PWM

PWM

EAO

OTP OVP

OCPOVPOTP

QS R

SS

+-

2.75V

PHASEpin

OCP

Low Side Rdson OCP Current Limit

260k130k

2k

10k 10k

2pF 5pF

I_Limitpin

Vccor

ExternalSupply

Current LimitProgramming

Resistor

Current LimitProgramming

Resistor


SC4612

POWER MANAGEMENTApplications InformationINTRODUCTION

The SC4612 is a versatile voltage mode synchronousrectified buck PWM convertors, with an input supply (VIN)ranging 4.5V to 40V designed to control and driveN-channel MOSFETs.The power dissipation is controlled using a novel low volt-age supply technique, allowing high speed and integra-tion with the high drive currents to ensure low MOSFETswitching loss. The synchronous buck configuration alsoallows converter sinking current from load without losingoutput regulation.

The internal reference is trimmed to 500mV with ± 1%accuracy, and the output voltage can be adjusted by twoexternal resistors.

A fixed oscillator frequency (up to 1.2MHz) can beprogrammed by an external capacitor for an optimizeddesign.During the Asynchronous start up, the SC4612 provides atop MOSFET shut down over current protection, while undernormal operating conditions a low side MOSFET RDS-ON

current sensing with hiccup mode over current protection,minimizes power dissipation and provides furtherprotection.Other features of the SC4612 include:

Wide input power voltage range (4.5V to 40V), low outputvoltages down to 500mV, externally programmable softstart, hiccup over current protection, wide duty cycle range,thermal shutdown, asynchronous start-up protection, anda -40 to 125°C junction operating temperature range.

THEORY OF OPERATION

SUPPLIES

Two pins (VDD and DRV) are used to power up the SC4612.If an input supply greater than 10V will be used, supplyconnected to the VDD pin is initially used to provide thegate drive to the internal pass transistor to regulate theDRV. This supply should be bypassed with a low ESRceramic capacitor right at the IC.

The DRV supply provides the bias for the InternalReference, Oscillator, and control circuitry. This supplyshould be bypassed with a low ESR 2.2uF (or greater)ceramic capacitor directly at the DRV to GND pins of theSC4612.

The DRV supply also provides the bias for the low and thehigh side MOSFET gate drive.

The maximum rating for DRV supplies is 8.6V and forapplications where input supply is below 10V, it may beconnected directly to VCC.

START UP SEQUENCE

Start up is inhibited until VDD input reaches its UVLOthreshold. The UVLO limit is 4.58V typical.Meanwhile, the high side and low side gate drivers DH,and DL, are kept low. Once VDD exceeds the UVLOthreshold, the external soft start capacitor starts to becharged by a 25µA current source. If an over currentcondition occurs, the SS/EN pin will discharge to 500mVby an internal switch. During this time, both DH and DLwill be turned off.

When the SS pin reaches 0.8V, the converter will startswitching. The reference input of the error amplifier isramped up with the soft-start signal. Initially only the highside driver is enabled. Keeping the low side MOSFET offduring start up is useful where multiple convertors areoperating in parallel. It prevents forward conduction in thefreewheeling MOSFET which might otherwise cause a dipin the common output bus.

In case of over current condition longer than 10 cyclesduring the asynchronous start up, SC4612 will turn offthe high side MOSFET gate drive, and the soft startsequence will repeat.When the SS pin reaches 1.3V, the low side MOSFET willbegin to switch and the convertor is fully operational inthe synchronous mode. The soft start duration iscontrolled by the value of the SS cap. If the SS pin is pulledbelow 0.5V, the SC4612 is disabled and draws very lowcurrent.

Bias Generation

A 4.5 to 9.2V supply voltage is required to power up theSC4612. This voltage could be provided by an externalpower supply or derived from VDD (VDD >10V) through aninternal pass transistor.

The internal pass transistor will regulate the DRV from anexternal supply >10V to produce 7.8V typ. at the DRV pin.


SC4612

POWER MANAGEMENTApplications Information (Cont.)Soft start / Shut down

An external capacitor at the SS/EN pin is used to set upthe soft start duration. The capacitor value in conjunctionwith the internal current source, controls the duration ofsoft start time. If the SS/EN pin is pulled down to GND, theSC4612 is disabled. The soft start pin is charged by a 25µAcurrent source and discharged by an internal switch. WhenSS/EN is released it charges up to 0.5V as the controlcircuit starts up.

The reference input of the error amplifier is effectivelyramped up with the soft-start signal. The error amp outputwill vary between 100mV and 1.2V, depending on the dutycycle selected. The error amp will be off until SS/ENreaches 0.7V and will move the output up to its desiredvoltage by the time SS/EN reaches 1.3V. The gate driverswill be in asynchronous mode until the FB pin reaches500mV.

The intention for the asynchronous start up is to keep thelow side MOSFET from being switched on which forces thelow side MOSFETs body diode or the parallel Schottky di-ode to conduct. The conduction by the diode prevents anydips in an existing output voltage that might be present,allowing for a glitch free start up in applications that aresensitive to any bus disturbances.During the asynchronous start up SC4612 monitors theoutput and if within 10 cycles the FB has not reached regu-lation, the device switches to synchronous mode. This pro-vides an added protection in case of short circuit at theoutput during the asynchronous start when the bottomMOSFET is not being switched to provide the RDS-ON sens-ing current limit protection.In case of a current limit, the gate drives will be held offuntil the soft start is initiated. The soft start cycle definedby the SS cap being charged from 800mV to 1.3V andslowly discharged to achieve an approximate hiccup dutycycle of 1% to minimize excessive power dissipation.

The part will try to restart on the next softstart cycle. If thefault has cleared, the outputs will start . If the fault stillremains, the part will repeat the soft start cycle above in-definitely until the fault has been removed.

The soft start time is determined by the value of thesoftstart capacitor (see formula below).

SS

SSSS I

2.1XCT ≅

Oscillator Frequency Selection

The internal oscillator sawtooth signal is generated bycharging an external capacitor with a current source of100µA charge current.

Following is the equation to calculate the oscillator fre-quency and some typical Cosc values:

OSC

6

OSC C10111F

−×≅

OVERCURRENT PROTECTION

SC4612 features low side MOSFET on-state Rds currentsensing and hiccup mode over current protection. ILIM pinwould be connected to DRV or PHASE via programmingresistors to adjust the over current trip point to meetdifferent customer requirements.The sampling of the current thru the bottom FET is set at~150ns after the bottom FET drive comes ON. It is done toprevent a false tripping of the current limit circuit due tothe ringing at the phase node when the top FET is turnedOFF.Internally overcurrent threshold is set to 100mV_typ. Ifvoltage magnitude at the phase node during sampling issuch that the current comparator meets this condition thenthe OCP occurs.Connecting a resistor from external voltage source suchas VDD, DRV, etc. to ILIM increases the current limit.Connecting a resistor from ILIM to PHASE lowers the currentlimit (see the block diagram in page 9).Internal current source at ILIM node is ~20µA. Externalprogramming resistors add to or subtract from that sourceand hence vary the threshold.The tolerance of the collective current sink at ILIM node isfairly loose when combined with variations of the FET’sRds(on). Therefore when setting current limit some iterationmight be required to get to the wanted trip point.Nonetheless, this circuit does serve the purpose of a hardfault protection of the power switches. When choosing thecurrent limit one should consider the cumulative effect ofthe load and inductor ripple current. As a rule of thumb,the limit should be set at least x10 greater then the pk-pkripple current. Whenever a high current peak is detected,SC4612 would first block the driving of the high side andlow side MOSFET, and then discharge the soft-tartcapacitor. Discharge rate of the SS capacitor is 1/25 ofthe charge rate.


SC4612

POWER MANAGEMENT

ERROR AMPLIFIER DESIGN

The SC4612 is a voltage mode buck controller that utilizesan externally compensated high bandwidth error amplifierto regulate output voltage. The power stage of thesynchronous rectified buck converter control-to-outputtransfer function is as shown below:

++

+×=

LC2sLR

Ls1

CCsESR1

SVINV

)s(VDG

where,

VIN – Input voltage RL – Load resistance

L – Output inductance C – Output capacitance

ESRC – Output capacitor ESR

VS – Peak to peak ramp voltage

The classical Type III compensation network can be builtaround the error amplifier as shown below:

R3

C3

R2

R1

C1

Vref

C2

-

+

Figure 1. Voltage mode buck converter compensationnetwork

The transfer function of the compensation network is asfollows:

)s1)(s1(

)s1)(s1(

s)s(G

2P1P

2Z1ZICOMP

ω+

ω+

ω+

ω+

⋅ω=

Applications Information (Cont.)Under Voltage Lock Out

Under Voltage Lock Out (UVLO) circuitry senses the VDDthrough a voltage divider. If this signal falls below 4.5V(typical) with a 400mV hysteresis (typical), the output driv-ers are disabled . During the thermal shutdown, the out-put drivers are disabled.

Gate Drive/Control

The SC4612 also provides integrated high current gatedrives for fast switching of large MOSFETs. The high sideand low side MOSFET gates could be switched with a peakgate current of 1.7A. The higher gate current will reduceswitching losses of the larger MOSFETs.

The low side gate drives are supplied directly from the DRV.The high side gate drives could be provided with the clas-sical bootstrapping technique from DRV.

Cross conduction prevention circuitry ensures a non over-lapping (30ns typical) gate drive between the top and bot-tom MOSFETs. This prevents shoot through losses whichprovides higher efficiency. Typical total minimum off timefor the SC4612 is about 30ns which will cause the maxi-mum duty cycle at higher frequencies to be limited to lowerthan 100%.

OVERVOLTAGE PROTECTION

If the FB pin ever exceeds 600mV, the top side driver islatched OFF, and the low side driver is latched ON. Thismode can only be reset by power supply cycling.


SC4612

POWER MANAGEMENT

where,

CoutLout1,

C)RR(1,

CR1

o231

2Z12

1Z×

=ω+

=ω=ω

31

312

2P23

1P311

I

CCCCR

1,CR1,

)CC(R1

+

=ω=ω+

=ω

The design guidelines are as following:

1. Set the loop gain crossover frequency wC for givenswitching frequency.

2. Place an integrator in the origin to increase DC and lowfrequency gains.

3. Select wZ1 and wZ2 such that they are placed near wO todampen peaking; the loop gain has –20 dB rate to goacross the 0 dB line for obtaining a wide bandwidth.

4. Cancel wESR with compensation pole wP1 (wP1 = wESR ).

5. Place a high frequency compensation pole wP2 at halfthe switching frequency to get the maximum attenuationof the switching ripple and the high frequency noise withthe adequate phase lag at wC.

0dB

Gd

T

ωZ1

ωZ2

p1

p2

c

ESR

ωo

ω

ω

ω

ω

Loop gain T(s)

Figure 2. Simplified asymptotic diagram of buck powerstage and its compensated loop gain.

Application Information (Cont.)


SC4612

POWER MANAGEMENT

PCB LAYOUT GUIDELINES

Careful attention to layout is necessary for successfulimplementation of the SC4612 PWM controller. Highswitching currents are present in the application and theireffect on ground plane voltage differentials must beunderstood and minimized.

1). The high power section of the circuit should be laid outfirst. A ground plane should be used. The number andposition of ground plane interruptions should notunnecessarily compromise ground plane integrity. Isolatedor semi-isolated areas of the ground plane may bedeliberately introduced to constrain ground currents toparticular areas; for example, the input capacitor andbottom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the TopFET (M1), and the Bottom FET (M2) must be kept as smallas possible. This loop contains all the high current, fasttransition switching. Connections should be as wide andas short as possible to minimize loop inductance.Minimizing this loop area will a) reduce EMI, b) lower groundinjection currents, resulting in electrically “cleaner” groundsfor the rest of the system and c) minimize source ringing,resulting in more reliable gate switching signals.

3). The connection between the junction of M1, M2 andthe output inductor should be a wide trace or copper region.It should be as short as practical. Since this connectionhas fast voltage transitions, keeping this connection shortwill minimize EMI. Also keep the Phase connection to theIC short. Top FET gate charge currents flow in this trace.

4) The Output Capacitor(s) (Cout) should be located as closeto the load as possible. Fast transient load currents aresupplied by Cout only, and therefore, connections betweenCout and the load must be short, wide copper areas tominimize inductance and resistance.

5) The SC4612 is best placed over a quiet ground planearea. Avoid pulse currents in the Cin, M1, M2 loop flowingin this area. GND should be returned to the ground planeclose to the package and close to the ground side of (oneof) the output capacitor(s). If this is not possible, the GNDpin may be connected to the ground path between theOutput Capacitor(s) and the Cin, M1, M2 loop. Under nocircumstances should GND be returned to a ground insidethe Cin, M1, M2 loop.

6)If the BST for the SC4612 is supplied from the 12V supply,the BST pin should be decoupled directly to GND by a 0.1uFceramic capacitor. Trace lengths should be as short aspossible. If a 12V supply is not available, a classical boot

strap method could be implemented to achieve the upperMOSFETs gate drive.

7) For current share mode of operation, the two convertersshould be laid out as symmetrical as possible for the bestcurrent sharing accuracy.

8) Allow adequate heat sinking area for the powercomponents. If multiple layers will be used, providesufficent vias for heat ransfer


Voltage and current waveforms of buck power stage .

Vout

VIN

+

+

Ids (Top Fet)

Ids (Bottom Fet)

I (Input Capacitor)

Vphase

I (Inductor) Vout

I (Output Capacitor)


SC4612

POWER MANAGEMENT

COMPONENT SELECTION:

SWITCHING SECTIONOUTPUT CAPACITORS - Selection begins with the mostcritical component. Because of fast transient load currentrequirements in modern microprocessor core supplies, theoutput capacitors must supply all transient load currentrequirements until the current in the output inductor rampsup to the new level. Output capacitor ESR is therefore oneof the most important criteria. The maximum ESR can besimply calculated from:

step current Transient excursion voltage transient Maximum

Where

==

≤

t

t

t

tESR

IV

IVR

For example, to meet a 100mV transient limit with a 10Aload step, the output capacitor ESR must be less than10mΩ. To meet this kind of ESR level, there are threeavailable capacitor technologies.

ygolonhceT

hcaEroticapaC ytQ

.dqR

latoT

C)Fu(

RSEm( Ω)

C)Fu(

RSEm( Ω)

mulatnaTRSEwoL 033 06 6 0002 01

NOC-SO 033 52 3 099 3.8

munimulARSEwoL 0051 44 5 0057 8.8

The choice of which to use is simply a cost/performanceissue, with low ESR Aluminum being the cheapest, buttaking up the most space.

INDUCTOR - Having decided on a suitable type and valueof output capacitor, the maximum allowable value ofinductor can be calculated. Too large an inductor willproduce a slow current ramp rate and will cause the outputcapacitor to supply more of the transient load current forlonger - leading to an output voltage sag below the ESRexcursion calculated above.The maximum inductor value may be calculated from:

( )OINt

ESR VVI

CRL −≤

The calculated maximum inductor value assumes 100%duty cycle, so some allowance must be made. Choosingan inductor value of 50 to 75% of the calculated maximumwill guarantee that the inductor current will ramp fastenough to reduce the voltage dropped across the ESR at afaster rate than the capacitor sags, hence ensuring a goodrecovery from transient with no additional excursions. Wemust also be concerned with ripple current in the outputinductor and a general rule of thumb has been to allow10% of maximum output current as ripple current. Notethat most of the output voltage ripple is produced by theinductor ripple current flowing in the output capacitor ESR.Ripple current can be calculated from:

OSC

INL fL4

VIRIPPLE ⋅⋅

=

Ripple current allowance will define the minimum permittedinductor value.

POWER FETS - The FETs are chosen based on severalcriteria with probably the most important being powerdissipation and power handling capability.

TOP FET - The power dissipation in the top FET is acombination of conduction losses, switching losses andbottom FET body diode recovery losses.

a) Conduction losses are simply calculated as:

IN

O

)on(DS2OCOND

VV cycleduty = D

whereDRIP

≈

⋅⋅=

b) Switching losses can be estimated by assuming aswitching time, If we assume 100ns then:

3INOSW 10VIP −⋅⋅=

or more generally,

4f)tt(VIP OSCfrINO

SW⋅+⋅⋅=

c) Body diode recovery losses are more difficult to estimate,but to a first approximation, it is reasonable to assume



SC4612

POWER MANAGEMENT

that the stored charge on the bottom FET body diode willbe moved through the top FET as it starts to turn on. Theresulting power dissipation in the top FET will be:

OSCINRRRR fVQP ⋅⋅=

To a first order approximation, it is convenient to onlyconsider conduction losses to determine FET suitability.For a 5V in, 2.8V out at 14.2A requirement, typical FETlosses would be:

epyTTEF R )no(SD m( Ω) )W(DP egakcaP

S2043LRI 51 96.1 D2 KAP

3022LRI 5.01 91.1 D2 KAP

0144iS 02 62.2 8-OS

Using 1.5X Room temp RDS(ON) to allow for temperature rise.

BOTTOM FET - Bottom FET losses are almost entirely dueto conduction. The body diode is forced into conduction atthe beginning and end of the bottom switch conductionperiod, so when the FET turns on and off, there is very littlevoltage across it resulting in low switching losses.Conduction losses for the FET can be determined by:

)D1(RIP )on(DS2OCOND −⋅⋅=

For the example above:

epyTTEF R )no(SD m( Ω) PD )W( egakcaP

S2043LRI 51 33.1 D2 KAP

3022LRI 5.01 39.0 D2 KAP

0144iS 02 77.1 8-OS

Each of the package types has a characteristic thermalimpedance, for the TO-220 package, thermal impedanceis mostly determined by the heatsink used. For the surface

mount packages on double sided FR4, 2 oz printed circuitboard material, thermal impedances of 40oC/W for theD2PAK and 80oC/W for the SO-8 are readily achievable.The corresponding temperature rise is detailed below:

(esirerutarepmeT 0 )C

epyTTEF TEFpoT TEFmottoB

S2043LRI 6.76 2.35

3022LRI 6.74 2.73

0144iS 8.081 6.141

It is apparent that single SO-8 Si4410 are not adequate forthis application, By using parallel pairs in each position,power dissipation will be approximately halved andtemperature rise reduced by a factor of 4.

INPUT CAPACITORS - Since the RMS ripple current in theinput capacitors may be as high as 50% of the outputcurrent, suitable capacitors must be chosen accordingly.Also, during fast load transients, there may be restrictionson input di/dt. These restrictions require useable energystorage within the converter circuitry, either as extra outputcapacitance or, more usually, additional input capacitors.Choosing low ESR input capacitors will help maximize ripplerating for a given size.



SC4612

POWER MANAGEMENTApplication Information (Cont.)

Application Circuit 1: Vin = 36V; Vout = 5V @ 20A, Fsw = 250kHz.

SC4612: 36Vin, 5Vout @ 20A

60%

65%

70%

75%

80%

85%

90%

95%

100%

0 2 4 6 8 10 12 14 16 18 20 22Current, (A)

Effic

ienc

y

Efficiency:

Q1HAT2172H

Q2HAT2172H

L14.7uH@22A

C100.1

C12A330/6.3V_PosCap

+

_

+

_

Vin=36V

Vout=5@20A

R310k

R55.36k

C61/16V

R80

R90

R1*

C2470p

C910/50V_cer

C30.1

R648.7k

C49.1n

D1MBR0540

C82.2/10VC5

1.3n

C1N/A

ILIM1 PHASE 12

OSC2

SS/EN3

FB5

VDD6 GND 7

DL 8

DRV 9

BST 10

DH 11

EAO4

U1SC4612MLP

R4*1.5k_1210

R7910

C71.3n

Rx0

C13B10/6.3V_cer

R2*

C12B330/6.3V

Fsw=250kHz

C13A330/6.3V

C14B330/50V_AL

C14A330/50V_AL


SC4612


Application Circuit 2: Vin = 24V; Vout = 3.3V @ 20A, Fsw = 470kHz.

Q1HAT2168H

Q2HAT2165H

L11.5uH@22A

C100.1

C12A180/4V_PosCap

+

_

+

_

Vin=24V

Vout=3.3@20A

R310k

R56.98k

C61/16V

R80

R90

R1*

C2220p

C922/25V_cer

C30.1

R639.2k

C43.9n

D1MBR0540

C82.2/10VC5

300p

C1N/A

ILIM1 PHASE 12

OSC2

SS/EN3

FB5

VDD6 GND 7

DL 8

DRV 9

BST 10

DH 11

EAO4

U1SC4612MLP

R4*430_1206

R7887

C7750p

Rx0

C13B10/6.3V_cer

R2*

C12B180/4V

Fsw=470kHz

C13A180/4V

C14B470/35V_AL

C14A470/35V_AL

Efficiency:

SC4612: 24Vin, 3.3Vout @ 20A

60%

65%

70%

75%

80%

85%

90%

95%

100%

0 2 4 6 8 10 12 14 16 18 20 22Current, (A)

Effic

ienc

y


SC4612


Efficiency:

Application Circuit 3: Vin = 12V; Vout = 2.5V @ 12A, Fsw = 770kHz

Q1HAT2168H

Q2HAT2165H

L11.4uH@14A

C100.1

C12A220/4V_PosCap

+

_

+

_

Vin=12V

Vout=2.5@12A

R310k

R52.74k

C61/16V

R80

R90

R1*

C2120p

C922/16V_cer

C30.1

R611.0k

C43.3n

D1SD107WS

C82.2/10VC5

300p

C1N/A

ILIM1 PHASE 12

OSC2

SS/EN3

FB5

VDD6 GND 7

DL 8

DRV 9

BST 10

DH 11

EAO4

U1SC4612MLP

R4*20

R7178

C72.2n

Rx0

C13B10/6.3V_cer

R2*

C12B220/4V

Fsw=770kHz

C13AN/A

C14B47/16V_AL

C14A47/16V_AL

SC4612: 12Vin, 2.5Vout @ 12A

60%

65%

70%

75%

80%

85%

90%

95%

100%

0 2 4 6 8 10 12 14Current, (A)

Effic

ienc

y


SC4612


Efficiency:

Application Circuit 4: Vin = 5V; Vout = 1.35V @ 12A, Fsw = 960kHz.

Q1HAT2168H

Q2HAT2168H

L10.47uH@15A

C100.1

C11100/6.3_1210_cer

+

_

+

_

Vin=5V

Vout=1.35@12A

R310k

R58.87k

C61

R1*

C2100p

C9100/6.3_1210_cer

C30.1

R613.3k

C41n

D1SD107WS

C82.2C5

33p

ILIM1 PHASE 12

OSC2

SS/EN3

FB5

VDD6 GND 7

DL 8

DRV 9

BST 10

DH 11

EAO4

U1SC4612MLP

R45.1

R7649

C7510p

R2*

Fsw=960kHz

SC4612: 5Vin, 1.35Vout @ 12A

60%

65%

70%

75%

80%

85%

90%

95%

100%

0 2 4 6 8 10 12 14

Current, (A)

Effic

ienc

y


SC4612


Evaluation Board 1:

Top layer and components view

Bottom Layer:


SC4612


Evaluation Board 2 (actual size):

Top layer: Bottom layer:


SC4612

POWER MANAGEMENTOutline Drawing - MLPD - 12

bxNe

MILLIMETERS

0.50 BSC

.002.001 0.00.000A1

.114

.154

.061

.124

.012

.007

E1

aaabbb

N

eL

A2

D1D

E

b

.020 BSC.067

.016

.003

.004

12

.118

(.008)

.130

.157

.010-

1.55.071

.020 0.30

.161

.122

.134

-.012

3.90

2.903.15

-0.18

.031MINDIM

AMAX

DIMENSIONSINCHES

.035NOM

.040 0.80MIN

0.02 0.05

3.10

4.10

1.80

3.40

0.50

0.30

1.70

0.40

0.100.0812

3.00

(0.20)

3.304.000.25

-

1.00MAX

0.90NOM

A B

PIN1INDICATOR

(LASER MARK)

A1

Aaaa C

A2

C

SEATING PLANE

1 2

N

bbb C A B

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

NOTES:

2.1.

D

E

D1/2D1

E1/2E1

LxN


SC4612

POWER MANAGEMENTLand Pattern - MLPD - 12

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR

NOTES:1.

DIM

XY

HKP

CG

MILLIMETERSINCHES(2.90)

.012

.028

.087

.020

.138

.067

(.114)

0.300.70

1.70

0.503.50

2.20

DIMENSIONS

COMPANY'S MANUFACTURING GUIDELINES ARE MET.

3.60.142Z

hcnarBnawiaT 0833-8472-2-688:leTF xa 0933-8472-2-688:

HbmGdnalreztiwShcetmeShcnarBnapaJ

0590-8046-3-18:leT1590-8046-3-18:xaF

hcnarBaeroK T le 7734-725-2-28:F 6734-725-2-28:xa

).K.U(detimiLhcetmeS 006-725-4971-44:leT106-725-4971-44:xaF

eciffOiahgnahS T 0380-1936-12-68:le1380-1936-12-68:xaF

LRASecnarFhcetmeS 00-22-82-961)0(-33:leT89-21-82-961)0(-33:xaF

foyraidisbusdenwo-yllohwasiGAlanoitanretnIhcetmeS.A.S.Uehtnisretrauqdaehstisahhcihw,noitaroproChcetmeS

HbmGynamreGhcetmeS 321-041-1618)0(-94:leT421-041-1618)0(-94:xaF

Contact Information for Semtech International AG

Documents

SC4612 Wide Input Range High Performance Synchronous Buck …u.dianyuan.com/bbs/u/32/1123661858.pdf · 2020. 5. 12. · Psarameter Tnest Condition Mpi Txy Msa Unit Power Supply VDD