SBVS272A –NOVEMBER 2015–REVISED SEPTEMBER 2018 TPS3711 36 … · 2020. 2. 9. · SBVS272A –NOVEMBER 2015–REVISED SEPTEMBER 2018 TPS3711 36-V Voltage Detector 1 1 Features

0.01 �F

VDD

SENSE OUT

GND

R1

R2

VPULLUP0 V to 25 V

To a reset or enable input of the system

RP

VMON 1.8 V to 36 V

Temperature (qC)

Neg

ativ

e-G

oing

Inpu

t Thr

esho

ld (

mV

)

-40 -25 -10 5 20 35 50 65 80 95 110 125399

399.1

399.2

399.3

399.4

399.5

399.6

399.7

399.8

399.9

400

VDD = 1.8 VVDD = 12 VVDD = 36 V

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3711SBVS272A –NOVEMBER 2015–REVISED SEPTEMBER 2018

TPS3711 36-V Voltage Detector

1

1 Features1• Wide Supply Voltage Range: 1.8 V to 36 V• Adjustable Threshold: Down to 400 mV• Open-Drain Output for Undervoltage Detection• Low Quiescent Current: 7 µA (Typical)• High Threshold Accuracy:

– 0.75% Over Temperature– 0.25% (Typical)

• Internal Hysteresis: 5.5 mV (Typical)• Temperature Range: –40°C to +125°C• Package: SOT-6

2 Applications• Industrial Control Systems• Embedded Computing Modules• DSPs, Microcontrollers, and Microprocessors• Notebook and Desktop Computers• Portable- and Battery-Powered Products• FPGA and ASIC Systems

3 DescriptionThe TPS3711 wide-supply voltage comparatoroperates over a 1.8-V to 36-V range. The device hasa precision comparator with an internal 400-mVreference and an open-drain output rated to 25 V forundervoltage detection. Set the monitored voltagewith the use of external resistors.

OUT is driven low when the voltage at the SENSEpin drops below the negative threshold, and goeshigh when the voltage returns above the positivethreshold. The comparator in the TPS3711 includesbuilt-in hysteresis for noise rejection, therebyensuring stable output operation without falsetriggering.

The TPS3711 is available in a SOT-6 package, and isspecified over the junction temperature range of–40°C to +125°C.

Device Information (1)PART NUMBER PACKAGE BODY SIZE (NOM)

TPS3711 SOT (6) 2.90 mm × 1.60 mm

(1) For all available packages, see the package option addendumat the end of the datasheet.

Typical Application Typical Error vs Junction Temperature

http://www.ti.com/product/tps3711?qgpn=tps3711http://www.ti.com/product/TPS3711?dcmp=dsproject&hqs=pfhttp://www.ti.com/product/TPS3711?dcmp=dsproject&hqs=sandbuysamplebuyhttp://www.ti.com/product/TPS3711?dcmp=dsproject&hqs=tddoctype2http://www.ti.com/product/TPS3711?dcmp=dsproject&hqs=swdesKithttp://www.ti.com/product/TPS3711?dcmp=dsproject&hqs=supportcommunity

2

TPS3711SBVS272A –NOVEMBER 2015–REVISED SEPTEMBER 2018 www.ti.com

Product Folder Links: TPS3711

Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information .................................................. 46.5 Electrical Characteristics........................................... 56.6 Timing Requirements ................................................ 66.7 Typical Characteristics .............................................. 7

7 Detailed Description .............................................. 97.1 Overview ................................................................... 97.2 Functional Block Diagram ......................................... 9

7.3 Feature Description................................................. 107.4 Device Functional Modes........................................ 10

8 Application and Implementation ........................ 118.1 Application Information............................................ 118.2 Typical Application ................................................. 12

9 Power Supply Recommendations ...................... 1410 Layout................................................................... 15

10.1 Layout Guidelines ................................................. 1510.2 Layout Example .................................................... 15

11 Device and Documentation Support ................. 1611.1 Documentation Support ....................................... 1611.2 Community Resources.......................................... 1611.3 Trademarks ........................................................... 1611.4 Electrostatic Discharge Caution............................ 1611.5 Glossary ................................................................ 16

12 Mechanical, Packaging, and OrderableInformation ........................................................... 16

4 Revision History

Changes from Original (November 2015) to Revision A Page

• Changed input pin voltage maximum value from 1.7 V to 6.5 V ............................................................................................ 4• Added tablenote .................................................................................................................................................................... 4

http://www.ti.com/product/tps3711?qgpn=tps3711http://www.ti.comhttp://www.ti.com/product/tps3711?qgpn=tps3711http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBVS272A&partnum=TPS3711

GND

VDD

GND

OUT

GND

SENSE

1

2

3

6

5

4

3

TPS3711www.ti.com SBVS272A –NOVEMBER 2015–REVISED SEPTEMBER 2018


Submit Documentation FeedbackCopyright © 2015–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

DDC Package6-Pin SOTTop View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.GND 2, 4, 6 — Ground. Connect all three pins to ground.

OUT 1 O Comparator open-drain output. This pin is driven low when the voltage at this comparator isless than VIT–. The output goes high when the sense voltage rises above VIT+.

SENSE 3 IComparator input. This pin is connected to the voltage to be monitored with the use of anexternal resistor divider. When the voltage at this pin drops below the threshold voltage VIT–,OUT is driven low.

VDD 5 I Supply-voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is goodanalog design practice to place a 0.1-µF ceramic capacitor close to this pin.


4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratings (1)over operating junction temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage (2)VDD –0.3 40

VVOUT –0.3 28VSENSE –0.3 7

Current Output pin current 40 mA

TemperatureOperating junction, TJ –40 125 °CStorage, Tstg -40 125

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) Operating Vsense at 1.7 V or higher and at 125°C continuously for 10 years or more would cause a degradation of accuracy spec to 1.5%maximum.

6.3 Recommended Operating Conditionsover operating junction temperature range (unless otherwise noted)

MIN NOM MAX UNITVDD Supply pin voltage 1.8 36 VVSENSE Input pin voltage 0 6.5 (1) VVOUT Output pin voltage 0 25 VVPULLUP Pullup voltage 0 25 VIOUT Output pin current 0 10 mATJ Junction temperature –40 25 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport (SPRA953).

6.4 Thermal Information

THERMAL METRIC (1)TPS3711

UNITDDC (SOT)6 PINS

RθJA Junction-to-ambient thermal resistance 201.6 °C/WRθJC(top) Junction-to-case (top) thermal resistance 47.8 °C/WRθJB Junction-to-board thermal resistance 51.2 °C/WψJT Junction-to-top characterization parameter 0.7 °C/WψJB Junction-to-board characterization parameter 50.8 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

http://www.ti.com/product/tps3711?qgpn=tps3711http://www.ti.comhttp://www.ti.com/product/tps3711?qgpn=tps3711http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBVS272A&partnum=TPS3711http://www.ti.com/lit/pdf/spra953

5




(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.(2) When VDD falls below UVLO, OUT is driven low. The output cannot be determined if less than V(POR).

6.5 Electrical CharacteristicsOver the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistor RP = 100 kΩ (unlessotherwise noted). Typical values are at TJ = 25°C and VDD = 12 V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITV(POR) Power-on reset voltage (1) VOL ≤ 0.2 V 0.8 VVIT– SENSE pin negative input threshold voltage VDD = 1.8 V to 36 V 397 400 403 mVVIT+ SENSE pin positive input threshold voltage VDD = 1.8 V to 36 V 400 405.5 413 mV

VHYSSENSE pin hysteresis voltage(HYS = VIT+ – VIT–)

2 5.5 12 mV

VOL Low-level output voltageVDD = 1.8 V, IOUT = 3 mA 130 250 mVVDD = 5 V, IOUT = 5 mA 150 250

IIN Input current (at SENSE pin)VDD = 1.8 V and 36 V, VSENSE = 6.5 V –25 +1 +25 nAVDD = 1.8 V and 36 V, VSENSE = 0.1 V –15 +1 +15

ID(leak) Open-drain leakage current VDD = 1.8 V and 36 V, VOUT = 25 V 10 300 nAIDD Supply current VDD = 1.8 V – 36 V 8 11 µAUVLO Undervoltage lockout (2) VDD falling 1.3 1.5 1.7 V


VDD

SENSE

OUT

VIT+VHYS

tpd(LH) tpd(LH)tpd(HL)

VIT±

t d(start)

V(POR)

6




(1) High-to-low and low-to-high refers to the transition at the input pin (SENSE).(2) During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition.

6.6 Timing RequirementsPARAMETER TEST CONDITION MIN TYP MAX UNIT

tpd(HL) High-to-low propagation delay (1)VDD = 24 V, ±10-mV input overdrive,RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

9.9 µs

tpd(LH) Low-to-high propagation delay (1)VDD = 24 V, ±10-mV input overdrive,RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

28.1 µs

td(start) (2) Startup delay VDD = 5 V 155 µs

tr Output rise timeVDD = 12 V, 10-mV input overdrive,RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD

2.7 µs

tf Output fall timeVDD = 12 V, 10-mV input overdrive,RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD

0.12 µs

Figure 1. Timing Diagram


VIT+ Threshold (mV)

Cou

nt

0

500

1000

1500

2000

2500

3000

3500

404

405

406

407

408

VIT- Threshold (mV)

Cou

nt

0

500

1000

1500

2000

2500

3000

3500

4000

4500

398

399

400

401

402

Temperature (qC)

Pos

itive

-Goi

ng In

put T

hres

hold

(m

V)

-40 -25 -10 5 20 35 50 65 80 95 110 125404

404.5

405

405.5

406

406.5

407

407.5

408

408.5

409VDD = 1.8 VVDD = 12 VVDD = 36 V

Temperature (qC)

Neg

ativ

e-G

oing

Inpu

t Thr

esho

ld (

mV

)

-40 -25 -10 5 20 35 50 65 80 95 110 125399

399.1

399.2

399.3

399.4

399.5

399.6

399.7

399.8

399.9

400

VDD = 1.8 VVDD = 12 VVDD = 36 V

Supply Voltage (V)

Sup

ply

Cur

rent

(P

A)

0 4 8 12 16 20 24 28 32 360

1

2

3

4

5

6

7

8

9

10

TJ = -40°CTJ = 0°CTJ = 25°CTJ = 85°CTJ = 125°C

Overdrive (%)

Min

imum

Pul

se W

idth

(P

s)

0 5 10 15 20 25 30 35 40 45 500

1

2

3

4

5

6

7

8

9

10

7




6.7 Typical Characteristicsat TJ = 25°C and VDD = 12 V (unless otherwise noted)

Figure 2. Supply Current vs Supply Voltage

VDD = 24 V, minimum pulse duration required to trigger outputhigh-to-low transition, SENSE = negative spike below VIT–

Figure 3. Minimum Pulse Duration vsThreshold Overdrive Voltage

Figure 4. SENSE Positive Input Threshold Voltage (VIT+) vsTemperature

Figure 5. SENSE Negative Input Threshold Voltage (VIT–) vsTemperature

VDD = 1.8 V

Figure 6. SENSE Positive Input Threshold Voltage (VIT+)Distribution

VDD = 1.8 V

Figure 7. SENSE Negative Input Threshold Voltage (VIT–)Distribution


Temperature (qC)

Sta

rtup

Del

ay (P

s)

-40 -25 -10 5 20 35 50 65 80 95 110 125120

135

150

165

180

195

Output Sink Current (mA)

VO

L (V

)

0 1 2 3 4 5 6 7 8 9 100

0.1

0.2

0.3

0.4

0.5

0.6TJ = -40°CTJ = 0°CTJ = 25°CTJ = 85°CTJ = 125°C

Output Sink Current (mA)

VO

L (V

)

0 1 2 3 4 5 6 7 8 9 100

0.1

0.2

0.3

0.4

0.5

0.6TJ = -40°CTJ = 0°CTJ = 25°CTJ = 85°CTJ = 125°C

Temperature (qC)

Hig

h-to

-Low

Pro

paga

tion

Del

ay (

µs)

-40 -25 -10 5 20 35 50 65 80 95 110 1254

6

8

10

12VDD = 1.8 VVDD = 36 V

Temperature (qC)

Low

-to-

Hig

h P

ropa

gatio

n D

elay

(µ

s)

-40 -25 -10 5 20 35 50 65 80 95 110 1250

0.5

1

1.5

2

2.5

3

VDD = 1.8VVDD = 36 V

8




Typical Characteristics (continued)at TJ = 25°C and VDD = 12 V (unless otherwise noted)

Input step ±200 mV

Figure 8. Propagation Delay vs Temperature(High-to-Low Transition at SENSE)

Input step ±200 mV

Figure 9. Propagation Delay vs Temperature(Low-to-High Transition at SENSE)

VDD = 1.8 V

Figure 10. Output Voltage Low vs Output Sink Current

VDD = 12 V

Figure 11. Output Voltage Low vs Output Sink Current

VDD = 5 V

Figure 12. Startup Delay vs Temperature


SENSE

GND

VDD

OUT

VIT-

9




7 Detailed Description

7.1 OverviewThe TPS3711 combines a comparator and a precision reference for undervoltage detection. The TPS3711features a wide supply voltage range (1.8 V to 36 V) and a high-accuracy threshold voltage of 400 mV (0.75%over temperature) with built-in hysteresis. The output is rated to 25 V and can sink up to 10 mA.

Set the input pin (SENSE) to monitor any voltage above 0.4 V by using an external resistor divider network.SENSE has very low input leakage current, allowing the use of a large resistor divider without sacrificing systemaccuracy. The relationship between the input and the output is shown in Table 1. Broad voltage thresholds aresupported that enable the device to be used in a wide array of applications.

Table 1. Truth TableCONDITION OUTPUT STATUS

SENSE > VIT+ OUT high Output high impedanceSENSE < VIT– OUT low Output asserted

7.2 Functional Block Diagram


10




7.3 Feature Description

7.3.1 Input Pin (SENSE)The TPS3711 combines a comparator with a precision reference voltage. The comparator has one external inputand one internal input connected to the internal reference. The falling threshold on SENSE is designed andtrimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy. Thecomparator also has built-in hysteresis that proves immunity to noise and ensures stable operation.

The comparator input swings from ground to 6.5 V (7.0 V absolute maximum), regardless of the device supplyvoltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nFbypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltagechanges on the monitored signal.

For the comparator, the output (OUT) is driven to logic low when the input SENSE voltage drops below VIT–.When the voltage exceeds VIT+, OUT goes to a high-impedance state; see Figure 1.

7.3.2 Output Pin (OUT)In a typical TPS3711 application, the output is connected to a reset or enable input of the processor [such as adigital signal processor (DSP), application-specific integrated circuit (ASIC), or other processor type] or the outputis connected to the enable input of a voltage regulator [such as a dc-dc converter or low-dropout regulator(LDO)].

The TPS3711 provides an open-drain output (OUT); use a pullup resistor to hold the line high when the outputgoes to a high-impedance state. Connect this pullup resistor to a voltage rail that meets the logic requirements ofthe downstream device. The TPS3711 output can be pulled up to 25 V, independent of the device supplyvoltage. To ensure the proper voltage level, give some consideration when choosing the pullup resistor value.The pullup resistor value is determined by VOL, output capacitive loading, and the open-drain leakage current(ID(leak)). These values are specified in the Electrical Characteristics table.

Table 1 and the Input Pin (SENSE) section describe how the output is asserted or high impedance. See Figure 1for a timing diagram that describes the relationship between threshold voltage and the respective output.

7.4 Device Functional Modes

7.4.1 Normal Operation (VDD > UVLO)When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUT signal corresponds to the voltage onSENSE, as listed in Table 1.

7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,V(POR), the OUT signal is asserted regardless of the voltage on SENSE.

7.4.3 Power On Reset (VDD < V(POR))When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND(V(POR)), OUT is in a high-impedance state.


0.01 �F

VDD

SENSE OUT

GND

R1

R2

VPULLUP0 V to 25 V


RP

VMON 1.8 V to 36 V

0.01 �F

VDD

SENSE OUT

GND

R1

R2


RP

1.8 V to 25 V

11




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TPS3711 is used as a precision voltage supervisor in several different configurations. The monitored voltage(VMON), VDD voltage, and output pullup voltage can be independent voltages or connected in any configuration.The following sections show the connection configurations and the voltage limitations for each configuration.

8.1.1 Input and Output ConfigurationsFigure 13 to Figure 14 show examples of the various input and output configurations.

Figure 13. Monitoring the Same Voltage as VDD

NOTE: The input can monitor a voltage higher than VDD (max) with the use of an external resistor divider network.

Figure 14. Monitoring a Voltage Other than VDD


MON(UV) ITR1

V = 1 + × VR2 �

§ ·¨ ¸© ¹

0.01 �F+

±

VDD

SENSE OUT

GND

2 M

37.4 k

VPULLUP3.3 V


100 k

VMON 24 V

12




Application Information (continued)8.1.2 Immunity to Input Pin Voltage TransientsThe TPS3711 is immune to short voltage transient spikes on the input pin. Sensitivity to transients depends onboth transient duration and amplitude; see Figure 3, Minimum Pulse Duration vs Threshold Overdrive Voltage.

8.2 Typical Application

Figure 15. 24-V, 10% Comparator

8.2.1 Design Requirements

Table 2. Design ParametersPARAMETER DESIGN REQUIREMENT DESIGN RESULT

Monitored voltage24-V nominal, falling (VMON(UV))

threshold10% nominal (21.6 V)

VMON(UV) = 21.8 V ±2.7%

Output logic voltage 3.3-V CMOS 3.3-V CMOSMaximum current consumption 30 µA 24 µA

8.2.2 Detailed Design Procedure

8.2.2.1 Resistor Divider SelectionThe resistor divider values and target threshold voltage can be calculated by using Equation 1 to determineVMON(UV).

where• R1 and R2 are the resistor values for the resistor divider on the SENSE pin• VMON(UV) is the target voltage at which an undervoltage condition is detected (1)

Choose an RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than theinput current at the SENSE pin. Use resistors with high values to minimize current consumption (as a result oflow input bias current) without adding significant error to the resistive divider. For details on sizing input resistors,refer to application report SLVA450, Optimizing Resistor Dividers at a Comparator Input, available for downloadfrom www.ti.com.

http://www.ti.com/product/tps3711?qgpn=tps3711http://www.ti.comhttp://www.ti.com/product/tps3711?qgpn=tps3711http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBVS272A&partnum=TPS3711http://www.ti.com/lit/pdf/SLVA450

Overdrive (%)

Min

imum

Pul

se W

idth

(P

s)

0 5 10 15 20 25 30 35 40 45 500

1

2

3

4

5

6

7

8

9

10

HI pullup

D(leak

pullu

UT)

p

O

V VRP

I

V

I

�d d

13




8.2.2.2 Pullup Resistor SelectionTo ensure the proper logic-high voltage level (VHI), select a pullup resistor value where the pullup voltage dividedby the pullup resistor value does not exceed the sink-current capability of the device. Confirm this voltage levelby verifying that the pullup voltage minus the open-drain leakage current (ID(leak) ) multiplied by the resistor isgreater than the desired VHI. These values are specified in the Electrical Characteristics .

Use Equation 2 to calculate the value of the pullup resistor.

(2)

8.2.2.3 Input Supply CapacitorAlthough an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF lowequivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may benecessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the powersource.

8.2.3 Application Curves

Figure 16. 24-V Window Monitor Output Response


100

0.01 �F+

±

VDD

SENSE OUT

GND

R1

R2

VPULLUP


14




9 Power Supply RecommendationsThe TPS3711 has a 40-V absolute maximum rating on the VDD pin, with a recommended maximum operatingcondition of 36 V. If the voltage supply that provides power to VDD is susceptible to any large voltage transientthat may exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, then place an RCfilter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. In these cases, a100-Ω resistor and 0.01-µF capacitor are required, as shown in Figure 17.

Figure 17. Using an RC Filter to Remove High-Frequency Disturbances on VDD


InputSupply

1

2

3 4

6

5

R2R1Monitored

Voltage

RP1

OutputFlag

PullupVoltage

CVDD

15




10 Layout

10.1 Layout Guidelines• Place R1 and R2 close to the device to minimize noise coupling into the SENSE node.• Place the VDD decoupling capacitor close to the device.• Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance

from the supply to the capacitor, might form an LC tank and create ringing with peak voltages above themaximum VDD voltage. If long traces are unavoidable, see Figure 17 for an example of filtering VDD.

10.2 Layout Example

Figure 18. Recommended Layout


16




11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related DocumentationFor related documentation, see the following application report, available through the TI website at www.ti.com:• Optimizing Resistor Dividers at a Comparator Input, SLVA450

11.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

http://www.ti.com/product/tps3711?qgpn=tps3711http://www.ti.comhttp://www.ti.com/product/tps3711?qgpn=tps3711http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SBVS272A&partnum=TPS3711http://www.ti.com/lit/pdf/SLVA450http://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://www.ti.com/corp/docs/legal/termsofuse.shtmlhttp://e2e.ti.comhttp://support.ti.com/http://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS3711DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 11BO

TPS3711DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 11BO

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS3711DDCR SOT-23-THIN

DDC 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

TPS3711DDCT SOT-23-THIN

DDC 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2021

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS3711DDCR SOT-23-THIN DDC 6 3000 213.0 191.0 35.0

TPS3711DDCT SOT-23-THIN DDC 6 250 213.0 191.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 7-Jan-2021

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

0.200.12 TYP

0.25

3.052.55

4X 0.95

1.1000.847

0.10.0 TYP

6X 0.50.3

0.60.3 TYP

1.9

0 -8 TYP

A

3.052.75

B1.751.45

SOT - 1.1 max heightDDC0006ASOT

4214841/B 11/2020

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Reference JEDEC MO-193.

34

0.2 C A B

1 6

INDEX AREAPIN 1

GAGE PLANESEATING PLANE

0.1 C

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAXARROUND

0.07 MINARROUND

6X (1.1)

6X (0.6)

(2.7)

4X (0.95)

(R0.05) TYP

4214841/B 11/2020


NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

SYMM

LAND PATTERN EXAMPLEEXPLOSED METAL SHOWN

SCALE:15X

SYMM

1

3 4

6

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

EXPOSED METAL

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDERMASK DETAILS

EXPOSED METAL

www.ti.com

EXAMPLE STENCIL DESIGN

(2.7)

4X(0.95)

6X (1.1)

6X (0.6)

(R0.05) TYP


4214841/B 11/2020

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 THICK STENCIL

SCALE:15X

SYMM

SYMM

1

3 4

6

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

https://www.ti.com/legal/termsofsale.htmlhttps://www.ti.com

1 Features2 Applications3 DescriptionTable of Contents4 Revision History5 Pin Configuration and Functions6 Specifications6.1 Absolute Maximum Ratings6.2 ESD Ratings6.3 Recommended Operating Conditions6.4 Thermal Information6.5 Electrical Characteristics6.6 Timing Requirements6.7 Typical Characteristics

7 Detailed Description7.1 Overview7.2 Functional Block Diagram7.3 Feature Description7.3.1 Input Pin (SENSE)7.3.2 Output Pin (OUT)

7.4 Device Functional Modes7.4.1 Normal Operation (VDD > UVLO)7.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)7.4.3 Power On Reset (VDD < V(POR))

8 Application and Implementation8.1 Application Information8.1.1 Input and Output Configurations8.1.2 Immunity to Input Pin Voltage Transients

8.2 Typical Application8.2.1 Design Requirements8.2.2 Detailed Design Procedure8.2.2.1 Resistor Divider Selection8.2.2.2 Pullup Resistor Selection8.2.2.3 Input Supply Capacitor

8.2.3 Application Curves

9 Power Supply Recommendations10 Layout10.1 Layout Guidelines10.2 Layout Example

11 Device and Documentation Support11.1 Documentation Support11.1.1 Related Documentation

11.2 Community Resources11.3 Trademarks11.4 Electrostatic Discharge Caution11.5 Glossary

12 Mechanical, Packaging, and Orderable Information