Running a Quantum CircuitRunning a Quantum Circuitat the Speed of Dataat the Speed of Data

Nemanja Isailovic, Mark Whitney, Nemanja Isailovic, Mark Whitney, Yatish Patel, John KubiatowiczYatish Patel, John Kubiatowicz

U.C. BerkeleyU.C. BerkeleyQEC 2007QEC 2007

The Impact of QEC

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X

QEC Step

QEC Step

QEC StepZero Ancilla Prep Zero Ancilla Prep

Zero Ancilla Prep

time

Serial Latency

Parallel Latency

Data Involvementin QEC Step

The Speed of Data

• Non-Transversal Logical Gate– Zhou et al., Phys. Rev. A, 62(5):52316

• Ideally, execution time determined solely by data

Non-Transversal Ancilla Prepare

Data Involvement

time

hardware

Limited BW Graph

• 32-bit Quantum Carry-Lookahead Adder in Ion Traps– Varying rate at which encoded zero ancillae are provided for QEC– Conclusion: design architecture with “ancilla factories”

Idealized Qalypso Architecture

• Dense data region– Data qubits only– Local communication

• Shared Ancilla Factories– Distributed to data as needed– Fully multiplexed to all data– Output ports ( ): close to data– Input ports ( ): may be far from

data, since recycled qubits have

irrelevant state

• Goals– Design ancilla factories– Answer Question: How much hardware is needed for ancilla

generation to run at the speed of data?

Our Quantum CAD Toolset

• Automated toolset to assist in architecture design– Ion trap technology– Local gates: two qubits in the same trap– Basic block abstraction: to avoid unknown electrode details

• Our basic layout blocks

straight 3-way 4-way turn gate locations

Dr. Hensinger, University of

Sussex3-way intersection

Level 1 [[7,1,3]] QEC Circuits

Encoded Zero Ancilla Prepare

Bit Correct

Phase Correct

EncodedData Qubit

Encoded Zero Ancilla Prepare

Corrected Encoded

Data Qubit

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Bit Correct

Phase Correct

0 Prep

Cat Prep

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?0 Prep

Cat Prep

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Cat Prep

IdenticalCircuits

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Steane, Multiple-ParticleInterference and QEC

Zero Ancilla Factory Design I

• “In-place” ancilla preparation

Verify

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Bit Correct

Phase Correct

0 Prep

Cat Prep

Verify

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?0 Prep

Cat Prep

Verify

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?0 Prep

Cat Prep

Encoded Ancilla Verification Qubits

• Ancilla factory consists of many of these– Encoded ancilla prepared

in many places– But we want input and

output ports

In-placePrep

In-placePrep

In-placePrep

In-placePrep

Zero Ancilla Factory Design II

• Pipelined ancilla preparation: break into stages– Match physical qubit bandwidth between stages for high utilization– Steady stream of encoded ancillae at output port

Physical0 Prep

CNOTs

Cat Prep

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ssba

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CNOTs

Cat Prep

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ssba

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Verif

VerifPhysical0 Prep

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Junk

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its

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ncill

ae

Recycle cat state qubits and failures

Recycle used correction qubits

Area Needs for Ancilla Preparation

33.6

6.813.2

48.8

68.461.3

17.624.8 25.5

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QuantumRipple-Carry

Adder

Quantum Carry-Lookahead

Adder

QuantumFourier

Transform

π/8 Ancilla Area

QEC Ancilla Area

Data Area

Practical Qalypso Architecture

• Multiple Data Regions– Each serviced by local ancilla factories– Communication network moves data between regions (not shown)– Data regions as large as possible to get benefits of minimizing

inter-region movement and multiplexing ancilla factory output

Summary

• Investigated removing ancilla generation from critical path – Operations on data qubits dictate performance– Tradeoff in ancilla bandwidth vs execution speed

• Architectural approach: ancilla factories– Match production bandwidth to needs of data– Pipelining places output ports close to data

• Qalypso architecture– Dense data regions with local communication– Ancilla factories segregated from data

• Multiplexing between factories and data• Input and output ports

– Layout investigation => ancilla generation dominates area