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RISC-V SoC FPGA Brings Real-Time to Linux

RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

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Page 1: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

RISC-V SoC FPGA Brings Real-Time to Linux

Page 2: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

2

Microchip’s FPGA StrategyTo be the leading provider of programmable RISC-V solutions

§ Highly differentiated, open ISA alternative to Arm®

technology§ AMP Mode: Simultaneous Linux + Real-Time Flexibility§ Enhances our low power position§ Enhances our security position§ Provenance enables full transparency for trusted design§ A lower cost ASIC migration path than Arm

§ Microchip Foundation Board Member: Ted Speers§ Microchip Working Committee Members: Stuart Hoad,

Richard Newell§ Strategic Partnership with

§ Soft 32-bit uCs, Hard Quad-core 64-bit uPs + uC§ Common MSS architecture, boards, ecosystem

A Comprehensive Ecosystem to Support RISC-V Development

Open. Lowest Power. Programmable RISC-V Solutions

Key RISC-V Foundation and Industry Partnerships

Page 3: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

3

CPUs: Mi-V Soft CPUs & Roadmap

Core LE’s CoreMark Cache Mul/Div Floating Point Availability

Mi_V_RV32IMA_L1_AHB 10K 2.01 8K I and D Yes N/A Now

Mi_V_RV32IMAF_L1_AHB 26K 2.01 8K I and D Yes Single Precision Now

Mi_V_RV32I_AHB 5K - N/A N/A N/A CQ4’19

Mi_V_RV32IMA_L1_AXI 10K 2.01 8K I and D Yes N/A Now

l Mi_V_RV32I_AHBl Small core, with/without debug, 5K LEs

l Mi_V_RV32IMA_L1_AHB with SECED available

Mi_V_RV32IMAFC_L1_AHB

Mi-V = Mi-V RISC-V Ecosystem RV32I = 32 bit integer machineM = Multiply and DivideA = Atomic InstructionsF = Single Precision Floating PointD = Double Precision Floating PointC = Compressed InstructionsL1 = Instruction and Data CacheAHB = AHB Bus InterfaceAXI = AXI Bus Interface

Page 4: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

4

SoftConsole Eclipse IDE

l A single tool chain for RISC-V and Arm MCUsl Easy migration from Arm to RISC-V

l Running on Linux or Windows Hostsl Bundled with example projects and Real-Time

Operating Systems (RTOSs)

Eclipse IDE Design Flow

Compiler

Debugger Demo/Eval Boards

Firmware Catalog

Sample Projects

Arduino ShieldPMOD

MikroBusUSB

Page 5: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

5

Why RISC-V for a SoC FPGA?

l The RISC-V ISA is Open. Open ISA’s allow for …l Low cost migration to ASICs, royaltyfree usagel Innovation for custom architectures – free “architectural

license” doesn’t restrict usage to fixed architectures

l The RISC-V ISA is simple. Simplicity …l Allows for a low-power implementationl Lowers cost of ownership - easier to learn, customize and

debugl Simple architectures are easier to secure against threats

Open, Lowest Power, Cost Optimized, Programmable SoC

Page 6: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

PolarFire® SoC Architecture

Open, Lowest Power, Cost-Optimized, Programmable SoC

Page 7: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

7

Data Route Zones Policy

Lowest Power Mid-Range FPGAs

Control Plane (PCIe, GigE, 10GE)

RF and Baseband Signal Processing

Video & Image Processing

Hardware Acceleration

Packet Processing & Traffic Management

10G Bridging & Aggregation

PortableCommunications

Low-PowerOptics

Page 8: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

8

Mid-Range FPGA Landscape

PolarFire FPGAs deliver 30 to 50% lower power than competing SRAM-based mid-range FPGAs

Transceiver Rate

Relative Power & Cost

5G

10G

28G+

PERFORMANCE OPTIMZEDCOST / POWER OPTIMIZED

Only cost and power optimized FPGA with 12.7G SERDES• Power/cost

decrease from mid-range FPGAs

• Performance upgrade from cost/power optimized FPGAs

High Density FPGAs

CompetingMid-rangeFPGAs

Competing Low Density FPGAs

Page 9: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

9

Lowest Power –Save Up to 50%

l Enabling Application Performance at Significantly Lower Power

l Static power 10x Reduction

l Transceiver 2x Reduction

§ Total power up to 50% lower than best case competitor number

§ PolarFire Customer: $1.5/W in BOM cost saving due to power savings

Page 10: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

10

Security is All About LayersTo protect your information you need

Secure Hardware, Design Security and Data Security

Microsemi FPGAs provide a strong foundation for your security needsThe DPA logo is a trademark of Cryptography Research, Inc. used under license

Trust: Licensed Patent Protected DPA Resistance, NIST Certified Crypto Accelerators, Secure Supply Chain

Anti-Tamper: Secure Bitstream, Tamper Detection, Active Mesh, No Copying. Cloning, or Reverse Engineering

Information Assurance: Key storage using Physically Unclonable Function (PUF)Advanced Crypto AcceleratorsLicensed Patent Protected DPA Resistance Pass through License

“The number of IoT sensors is expected to approach 30 billion in 5 years – and each unit is a potential entry point for cyber-criminals” –The Economist Intelligence Unit, 4/11/2016

“Some call cybercrime the greatest transfer of wealth in human history” – The Center of Strategic and International Studies, July 2013, The Economic Impact of Cybercrime

Page 11: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

11

Exceptional Reliability

l Error Free SEU immune Fabric Configurationl No need to detect configuration errors

l No scrubbing required l No triple mode redundancy neededl Lowers cost

l Memories are also protected l Built-in SECDED on 33-bit word

l System Controller Suspend Mode for Safety-Critical Applications

SEU a growing concern for equipment demanding 99.999% uptime

Flash FPGANo Error

SRAM FPGAFunctional Failure

Alpha / Neutronparticles strike routing matrix

SRAM Configuration Failures

Page 12: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

12

PolarFire Product Family

Extended Commercial (0⁰C-100⁰C) and Industrial (-40⁰C-100⁰C) Temperature Support for all Die Package Combinations - RoHS only

FeaturesPolarFire FPGA

MPF100 MPF200 MPF300 MPF500

FPGA Fabric

Logic Elements (4LUT + DFF) 109K 192K 300K 481KMath Blocks (18x18 MACC) 336 588 924 1480LSRAM Blocks (20 kbit) 352 616 952 1520uSRAM Blocks (64x12) 1008 1764 2772 4440Total RAM (Mbits) 7.6 Mbits 13.3 Mbits 20.6 Mbits 33 MbitsuPROM (kbits 297 Kbits 297 Kbits 459 Kbits 513 KbitsUser DLL's/PLL's 8 each 8 each 8 each 8 each

High Speed I/O

250 Mbps -12.7 Gbps Transceiver Lanes 8 16 16 24PCIe Gen2 Endpoints/Root Ports 2 2 2 2

Total I/O Total User I/O 284 364 512 584

Packaging

Type / Size / Pitch Total User I/O (HSIO / GPIO) GPIO CDRs / XCVRsFCSG325 (11x11, 11x14.5*, 0.5 mm) 170(84/86) 8/4 170(84/86) 8/4*FCSG536 (16x16, 0.5 mm) 300(120/180) 15/4 300(120/180) 15/4FCVG484 (19x19, 0.8 mm) 284(120/164) 14/4 284(120/164)14/4 284(120/164) 14/4FCG484 (23x23, 1.0 mm) 244(96/148) 13/8 244(96/148) 13/8 244(96/148) 13/8

FCG784 (29x29, 1.0 mm) 364(132/232)20/16

388(156/232) 20/16

388(156/232)20/16

FCG1152 (35x35, 1.0 mm) 512(276/236) 24/16

584(324/260) 24/24

Devices in the same package and family type are pin compatible

Additional Temp Grade: Military (-55⁰C-125⁰C) - Leaded packages only Note: FC484M package is a lidded package whereas the FCG484I package is not.

Page 13: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

PolarFire® SoC Architecture

Open, Lowest Power, Cost-Optimized, Programmable SoC

Page 14: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

14

Secure Communications and Portable Embedded Systems

Enabling Purpose-built, Real-time, Low Power systems

Smart Weapons, Drones and UAVsIndustrial IoT

Collaborative RobotsImaging and Machine LearningSafety Critical Systems

Page 15: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

15

Real-time Linux?

l Widespread Linux adoptionl Rich OS with thousands of applications to choose from

l Requirements still exist for real-time while running Linuxl Safety-critical

l The ability to deterministically monitor the execution environment

l Real-time system controll Completing tasks deterministically, on time every time

l Securing the IoTl Execute a trusted execution environment deterministically for consistent

results

l Working with our partnerl We have been able to architect a complex SoC FPGA that provides

determinism and a rich OS within the same multi-core CPU cluster

Page 16: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

16

Variable Execution Time in Typical Application Processors

SMP 1

L2

DDR4

CPU

SMP 2

CPU

SMP 3

CPU

SMP 4

CPU

5332800

5333000

5333200

5333400

5333600

5333800

5334000

5334200

ISR Execution Time Variability

Branch predictors, cache misses and lack of coherency affect determinism negatively

Page 17: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

17

l Turn off the CPU branch predictorsl Convert L1 to Tightly Integrated Memoryl Make sure all cores coherent to the memory subsysteml Make the memory system deterministicl Share coherent memory for message passing

Real-Time and Linux

SMP 1

L2

DDR4

RTBP Off

E51 U54

SMP 2

U54

SMP 3

U54

SMP 4

U54

Direct Access

Coherent Buffers

5722600

5723100

5723600

No Execution Time VariabilityRESULT

Page 18: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

18

PolarFire SoC - RISC-V Enabled Innovation Platform

Freedom to Innovate in• Linux and Real-Time

• Securely Connected IoT systems• High-Rel Safety Critical Systems

• Thermal and Power Constrained Systems

Page 19: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

19

Low Power MSSü Low power RISC-V micro-architectureü 2MB L2 cache: increases cache hit/miss ratioü 0.5-0.9W lower power

Low Power: RISC-V MSS vs. Alternatives

0.0

200.0

400.0

600.0

800.0

1000.0

1200.0

1400.0

1600.0

PolarFireSoC Zynq Zynq+

Processor Power4000 DMIPS load, DDR@32b x 1600Mb/s

DDR

ProcessorDynamic

ProcessorStatic

Comp A 22nm

Comp A 16nm

PolarFire SOC28nm

0

2

4

6

8

10

12

14

16

PolarFireSoC Zynq Zynq+

4x4x60MHz DFE Power

Static

XCVR

lProcessor

Dynamic

4x4x60MHz RRH

368MHz732DSP126k LE

10xCPRI7 1x12.5G JESD

4000 DMIPS

4GB/s DDR

Comp A 22nm

Comp A 16nm

PolarFire SOC28nm

LTE Digital Front End Applicationü 3-7W lower power for 60MHz 4x4 MIMO

implementation

Page 20: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

20

l PolarFire® SoC inherits best-in-class PolarFire FPGA Securityl DPA-resistant bitstream programmingl Anti-tamperl Cryptographical bound supply chain assurancel Physically unclonable functionl True random number generatorl Side channel resistant crypto coprocessor

l PolarFire SoC has:+ Secure Boot+ Spectre and Meltdown immunity+ Physical memory protection+ SECDED on all memories

Security Built for Defense, Ready for IoT

Page 21: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

Pre-silicon PolarFire® SoC Development Options

Page 22: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

22

Freedom to Start Software Development

Eclipse IDE Design Flow

Compiler

Debugger

Firmware Catalog

Sample Projects

GDB

l Free Rapid Software Development and Debug Capabilities Without Hardware

l Complete PolarFire SoC Processor Subsystem Model

l Available now

Page 23: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

23

HiFive Unleashed Development BoardHiFive Unleashed Expansion Board

PolarFire SoC Embedded Experts Development Kit

Freedom to Begin Hardware Development

+

MPFS-DEV-KIT

Page 24: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

24

PolarFire SoC Summary

l PolarFire® FPGA Award-Winning Featuresl 30-50% lower power over competitive devicesl Defense-grade securityl Exceptional reliabilityl Smallest, lowest power, secure form factors – 11x11, 16x16, 19x19

l PolarFire Microprocessor Subsysteml Linux and real time in a deterministic, coherent CPU clusterl 30-50% lower powerl Defense-grade secure bootl Spectre/Meltdown immunel SECDED on all memories

Click here to learn more

https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
Page 25: RISC-V SoC FPGA Brings Real-Time to Linux · 2 Microchip’s FPGA Strategy To be the leading provider of programmable RISC-V solutions § Highly differentiated, open ISA alternative

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