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RF Reconfiguration and Testing
Rashad Ramzan and Jerzy DabrowskiLinköping University
Dept. of Electrical EngineeringSE-581 83 Linköping, Sweden
2 Linkoping, OCT 4 , 2006
Outline
• Testable LNA • RF-DC Detector• Offset-Loopback• Summary, Future Planes
3 Linkoping, OCT 4 , 2006
Recent Chip: RF Sampling Frontend
• A 1.4V, 25mW Wideband Testable LNA in 0.13m CMOS
4 Linkoping, OCT 4 , 2006
5 Linkoping, OCT 4 , 2006
Recent Chip: RF Sampling Frontend
VBias5
OUT-
BWC
VDD
Bias2R
VBias2
R1IN-
VBias4
VBias3
M3
M1
M2
M4M5
C2C
C1C
DR
Bias5R
OUT+Bias2R
R1IN+
M3
M1
M2
M4M5
C1C
DR
VDD VDD VDD
Bias5R
VBias2
C2C
BWC
VBias3
VBias4
2 1 2 1
2 2
1 1
(1 ) 1m m
inm m D m v
g R g RZ
g G R g A
1 5 4
4 1 5
( ). ..
( )m m m D
v m Dm ds ds
g g g RA G R
g g g
2
1 5 3 3 2 2 12 2 2
1 5 2 1
11 1
1 4 4 4 4 1 4 1 4 1m s m s D
v m s m s m s v s v
g R g R R RF
A g R g R g R R A R A
6 Linkoping, OCT 4 , 2006
Resent Chip: RF Sampling Frontend Due to “PCB” we are not
able to measure NF at high frequencies?
Traces are not even. FR4 not good for >1GHz Connector Pad parasitics
& impedance discontinuities
Remedy: We are working on it …….. New PCB with Rogers not
FR4 or Thin Film Technology TRL calibration
1,0
1,5
2,0
2,5
3,0
3,5
4,0
1 2 3 4 5 6 7Frequency (GHz)
NF
(d
B)
SchematicLayoutMeasurment
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1 2 3 4 5 6 7 8 9 10Frequency (GHz)
S11 (d
B)
SchematicLayoutMeasurment
0
2
4
6
8
10
12
14
16
18
20
0 1 2 3 4 5 6 7 8 9 10Frequency (GHz)
Vo
lta
ge G
ain
(d
B)
SchematicLayoutMeasurment
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1 2 3 4 5 6 7 8 9 10Frequency (GHz)
S22 (d
B)
SchematicLayoutMeasurment
7 Linkoping, OCT 4 , 2006
RF Testing- RF to DC Detector
VG-LNA Buffer
Q
I
o90
FrequencySynthesizer
Bas
e B
and
Pro
cess
or
Low
pass
Filt
erV
GA
and
ADC
ADCinZ =50
RFSignal
Generator
RF-DCD
C/L
ow Freq B
us
Slow SpeedMU
X
MU
X
T-DAC
T-ADC
D
CBA
E
F
DC/Low Freq Bus
Detector
BPF
Idea! Only from DC measurements. All catastrophic faults
can be detected. Some of parametric
faults. Performance
parameter like Gain, 1dB CP
And may be NF & IP3 Calibration of Detectors
with DC/Low voltage signals only
8 Linkoping, OCT 4 , 2006
RF Testing- Offset Loopback
BaseBand
Processor
LPF
DACLPF
LNA
LO
Amp T r a n s m i t t
e r
R e c e i v e r (zero-IF)
TA
Test
xtest
ADC
I
Q
900
IQ
IQ
IQ offset
mixerIQ test signal
QPSK is the simplest implementation but others can
be used as well
• Test setup using IQ offset mixer for shared LO
f
f
Tx band Rx band
fTx fRx
)sin()(cos)( txtx Qtest
Itest
)sin()(cos)( txtx Itest
Qtest
t 0
9 Linkoping, OCT 4 , 2006
RF Testing- Offset Loopback• Test setup using IQ offset mixer for shared LO
QPSK:EVM vs Fault in LNA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0.0 2.0 4.0 6.0 8.0 10.0
Fault Strength (Gain and NF) in dB
EV
M
60dB:40deg 70dB:40deg60dB:15deg 70dB:15deg
QPSK: EVM vs Fault in Down Conversion Mixer
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0 2.0 4.0 6.0 8.0 10.0
Fault Strength (Gain and NF) in dB
EV
M
60dB 70dB
60dB(Gain Only) 70dB ()Gain Only
= 160
=160
=50
(skew)
Tx I
Tx Q
Rx Q
Rx I
10 Linkoping, OCT 4 , 2006
Future Planes
• New board for complete Chip measurements.• Test for Transceivers with polar modulator
(shared LO) multistandard Transceivers. (with Phillips)
On-Chip phase noise measurements
