RF Multiplexing RF Multiplexing Transmitting and Transmitting and

Receiving UnitReceiving Unit

EE413 Final ReportEE413 Final Report

ByBy

Adam Halstead and Michael Adam Halstead and Michael PfetschPfetsch

Problem and SolutionProblem and Solution

Problem: There are a limited number Problem: There are a limited number of frequency bands that can be of frequency bands that can be allocated for sending information allocated for sending information over long distancesover long distances

Solution: Devise a system that Solution: Devise a system that enables the transmission of multiple enables the transmission of multiple sources of information over a single sources of information over a single RF carrier frequencyRF carrier frequency

DescriptionDescription

Digitize analog information from several sourcesDigitize analog information from several sources Multiplex multiple sources to form one source Multiplex multiple sources to form one source

for transmissionfor transmission Transmit multiplexed source using frequency Transmit multiplexed source using frequency

modulationmodulation Receive frequency modulated signalReceive frequency modulated signal Separate single source into its original sourcesSeparate single source into its original sources Convert signal back to analog and output to userConvert signal back to analog and output to user

Finished ProjectFinished Project

FPGA

CPLD

D/A

PLL

Op-amps

A/D

DemonstrationDemonstration

ResultsResults Successful multiplexing and de-multiplexing of Successful multiplexing and de-multiplexing of

4 analog audio sources 4 analog audio sources Successful construction of phase locked loop Successful construction of phase locked loop

circuitcircuit Successful construction of an FM transmitterSuccessful construction of an FM transmitter Could not synchronize transmitter and receiver Could not synchronize transmitter and receiver

using phase lock loop using phase lock loop Used direct clock connection for final demonstrationUsed direct clock connection for final demonstration Tried several different line coding schemesTried several different line coding schemes

Bandwidth of transmitter/receiver limited to Bandwidth of transmitter/receiver limited to 75kHz75kHz inadequate for transmission rate of 330 kbpsinadequate for transmission rate of 330 kbps

ApplicationsApplications

Surround sound radio/television streams: Surround sound radio/television streams: eg.: Front-left, front-right, rear-left, rear-eg.: Front-left, front-right, rear-left, rear-rightright

Multilingual broadcastsMultilingual broadcastseg.: Cantonese, Hindi, Arabic, Englisheg.: Cantonese, Hindi, Arabic, English

Two stereo music streams of different Two stereo music streams of different genres:genres:eg.: Beethoven’s 9eg.: Beethoven’s 9thth Symphony and “I did it” Symphony and “I did it” by Dave Matthews Bandby Dave Matthews Band

Four simultaneous talk radio shows:Four simultaneous talk radio shows:eg.: health, auto mechanics, poetry, politicseg.: health, auto mechanics, poetry, politics

CostCost

Transmission ProtocolTransmission Protocol

Transmission ProtocolTransmission Protocol A single unit of data transmission is 33 A single unit of data transmission is 33

bits in length.bits in length.Reason: (4 signal sources) * (1 sample per Reason: (4 signal sources) * (1 sample per source) * (8 data bits per sample) + 1 source) * (8 data bits per sample) + 1 synchronizing bit = (32 + 1) bits = 33 bitssynchronizing bit = (32 + 1) bits = 33 bits

The data for all four sources are The data for all four sources are interleaved at the bit level.interleaved at the bit level.

Bytes are transmitted MSB first, with Bytes are transmitted MSB first, with signal source 1 transmitted firstsignal source 1 transmitted first

Baud rate: (33 bits/sample) * (10,000 Baud rate: (33 bits/sample) * (10,000 samples/s)= 330,000 bits/ssamples/s)= 330,000 bits/s

Line codingLine coding

Clock RecoveryClock Recovery

Phase locked loop circuit utilizing the NTE989, which is pin equivalent to the LM565

Phase Locked Loop Phase Locked Loop DemonstrationDemonstration

FM transmitter/receiver FM transmitter/receiver performanceperformance

Bandwidth: 10,000 HzBandwidth: 10,000 Hz Frequency response: 8 Hz – 10 kHzFrequency response: 8 Hz – 10 kHz

FM Transmitter Circuit FM Transmitter Circuit DiagramDiagram

Circuit design courtesy of Velleman-kit K1771Advantage: Greater bandwidth due to high carrier frequency (around

100MHz)Disadvantage: Difficult to replicate the transformer provided by

printed circuit board.

System as implementedSystem as implemented

PartsParts LF353 OpAmp – amplified incoming audio signals LF353 OpAmp – amplified incoming audio signals

and output signal of receiverand output signal of receiver TLC0838 – 8 bit A/D converter to digitize audio TLC0838 – 8 bit A/D converter to digitize audio

signals to be processed by FPGA signals to be processed by FPGA XC2S50 FPGA on Digilent Pegasus board with 50 XC2S50 FPGA on Digilent Pegasus board with 50

MHz crystal oscillator – controlling hardware (state MHz crystal oscillator – controlling hardware (state machine with 132 states) for the transmitting endmachine with 132 states) for the transmitting end

NTE989 Phase Lock Loop – used for clock recovery NTE989 Phase Lock Loop – used for clock recovery (pin equivalent to LM565)(pin equivalent to LM565)

XC2C64 CPLD in Digilent CMOD package – XC2C64 CPLD in Digilent CMOD package – controlling hardware (state machine with 33 states) controlling hardware (state machine with 33 states) for the receiving endfor the receiving end

TLC7524 – 8 bit parallel input D/A converter to TLC7524 – 8 bit parallel input D/A converter to convert digitized signal to audio signal convert digitized signal to audio signal

LD1086V33 Voltage Regualtor – Provided 3.3V for LD1086V33 Voltage Regualtor – Provided 3.3V for CPLDCPLD

K1771 FM Transmitter Kit – Used to transmit signalK1771 FM Transmitter Kit – Used to transmit signal

ChallengesChallenges A/D converters utilized complicated A/D converters utilized complicated

configuration scheme which required 5 configuration scheme which required 5 configuration bits to be sent before configuration bits to be sent before each conversion.each conversion.

Positive Positive andand negative negative clock edges clock edges used at used at various various points in each points in each conversion.conversion.

Designed a Designed a state machine state machine with 132 with 132 states, and states, and implemented implemented on the FPGAon the FPGA

ChallengesChallenges

Interfacing a 3.3V FPGA with 5V A/D Interfacing a 3.3V FPGA with 5V A/D convertersconverters FPGA is 5V CompliantFPGA is 5V Compliant Configured I/O pins for TTL signal Configured I/O pins for TTL signal

standardstandard Used high impedance state for logic 1Used high impedance state for logic 1 Output pins of FPGA connected to 5V Output pins of FPGA connected to 5V

through 10kΩ pull up resistorsthrough 10kΩ pull up resistors

Future WorkFuture Work Solve problem encountered in clock Solve problem encountered in clock

recovery with phase locked loop, recovery with phase locked loop, eliminating need for separate clock eliminating need for separate clock connection.connection.

Wireless transmission using TRF-24G Wireless transmission using TRF-24G transceiver to provide enough bandwidth transceiver to provide enough bandwidth for higher quality audio signal.for higher quality audio signal.

Increase the number of multiplexed Increase the number of multiplexed signals, by adding more A/D converters signals, by adding more A/D converters and changing the programmable logic and changing the programmable logic controller.controller.

Utilize digital audio Utilize digital audio compression/decompressioncompression/decompression

ReferencesReferences Clark, Jeremy and Mcneil, Kyle James. “Experiment Clark, Jeremy and Mcneil, Kyle James. “Experiment

to view T1 clock recovery”. Retrieved April 12, to view T1 clock recovery”. Retrieved April 12, 2005, from 2005, from “http://www.picotech.com/experiments/t1_clock_rec“http://www.picotech.com/experiments/t1_clock_recovery/”. overy/”.

Liu, Pao-Lo. “Signal Generation and Conditioning” Liu, Pao-Lo. “Signal Generation and Conditioning” lecture notes. Retrieved April 4, 2005, from lecture notes. Retrieved April 4, 2005, from “http://www.ee.buffalo.edu/faculty/paololiu/413/sige“http://www.ee.buffalo.edu/faculty/paololiu/413/sigen.ppt”.n.ppt”.

Tomasi, Wayne. Tomasi, Wayne. Electronic Communications Electronic Communications Systems: Fundamentals Through AdvancedSystems: Fundamentals Through Advanced, Fifth , Fifth Edition. Upper Saddle River, New Jersey: Pearson Edition. Upper Saddle River, New Jersey: Pearson Education, Inc., 2004.Education, Inc., 2004.

Questions?Questions?

End of show

Extra SlidesExtra Slides

TimelineTimeline

Example Verilog Code – Example Verilog Code – mod128 countermod128 counter

module counter( clock, counter );

input clock;

output [6:0] counter;

reg [6:0] counter;

always @ ( posedge clock )

begin

counter <= counter + 1;

end

endmodule

Programmable Logic Programmable Logic DevicesDevices

Complex Programmable Logic Devices Complex Programmable Logic Devices (CPLD’s): Typically have 32 to 512 macrocells, (CPLD’s): Typically have 32 to 512 macrocells, each containing combinational logic and a flip each containing combinational logic and a flip flop.flop.

Field Programmable Gate Arrays (FPGA’s): A Field Programmable Gate Arrays (FPGA’s): A more recent technology, capable of realizing more recent technology, capable of realizing more complicated designs than CPLD’s.more complicated designs than CPLD’s.

Verilog HDL: Hardware description language Verilog HDL: Hardware description language used to abstractly define a digital system. used to abstractly define a digital system. Useful for implementing a design on a CPLD Useful for implementing a design on a CPLD or an FPGA, although basic schematic design or an FPGA, although basic schematic design may still be used.may still be used.

Work PlanWork Plan

1.0 Project scope and approach1.0 Project scope and approach1.1 Define project goals1.1 Define project goals1.2 Develop specifications to achieve goal1.2 Develop specifications to achieve goal1.3 Create block diagram of system1.3 Create block diagram of system

2.0 Design system2.0 Design system2.1 Design multiplexing/de-multiplexing circuits2.1 Design multiplexing/de-multiplexing circuits2.2 Design A/D and D/A conversion circuits2.2 Design A/D and D/A conversion circuits2.3 Design transmitter/receiver circuits2.3 Design transmitter/receiver circuits

3.0 Construction3.0 Construction3.1 Construct multiplexing/de-multiplexing 3.1 Construct multiplexing/de-multiplexing circuitscircuits3.2 Construct A/D and D/A conversion circuits3.2 Construct A/D and D/A conversion circuits3.3 Implement transmitter/receiver circuits3.3 Implement transmitter/receiver circuits

Work Plan continuedWork Plan continued

4.0 Optimization4.0 Optimization

4.1 Optimize synchronization of system4.1 Optimize synchronization of system

4.2 Make adjustments for increased quality 4.2 Make adjustments for increased quality at output to systemat output to system

4.3 Fine tune system for maximum 4.3 Fine tune system for maximum efficiencyefficiency

5.0 Testing and Documentation5.0 Testing and Documentation

5.1 Test system for quality of output versus 5.1 Test system for quality of output versus quality of inputquality of input

5.2 Document results5.2 Document results