Reuse: Right Idea, Wrong representation?

REUSE: RIGHT IDEA, WRONG REPRESENTATION?

June, 2013(New Slides Added to Support Unaided

Reading)Ted J. Biggerstaff

Software Generators, LLC

Never Reprogram AgainTM

ImplementationNeutral

ComputationSpec

DSLGen

Von NeumannArchitecture

MulticoreThreaded

Parallelism

InstructionLevel

Parallelism(ILP)

MulticoreThreadedAnd ILP

GPUParallelism(e.g., C and

CUDA)

API orLayeredLibrary

(e.g, DirectX)Speciality

Platform orFramework(e.g, MDE

Docs)

FutureArchitectures

Digital SignalProcessing

ChipAPI

ExecutionPlatform

Spec

//Sobel Edge Detectionb=[(a Å s)2 +(a Å sp)2]1/2

((PL C) (partition t))

Von Neumann with

Partitioning



ComputationSpec

DSLGen


MulticoreThreaded

Parallelism

InstructionLevel

Parallelism(ILP)



CUDA)




Docs)

FutureArchitectures


ChipAPI

ExecutionPlatform

Spec


((PL C) (partition t) Mcore (Threads MS) (LoadLevel (SliceSize 5)))

MulticoreThreadedParallel



ComputationSpec

DSLGen


MulticoreThreaded

Parallelism

InstructionLevel

Parallelism(ILP)



CUDA)




Docs)

FutureArchitectures


ChipAPI

ExecutionPlatform

Spec


((PL C) (partition t) (ILP SSE))

Instruction Level

Parallelism with SSE

Alternative Output Opportunities


ComputationSpec

DSLGen


MulticoreThreaded

Parallelism

InstructionLevel

Parallelism(ILP)



CUDA)




Docs)

FutureArchitectures


ChipAPI

ExecutionPlatform

Spec


((PL MDE) (partition t) (ILP SSE)) MDE DOCs

for Parallelism with SSE

Beyond MDEPROBLEM DOMAIN (PD) PROGRAM LANGUAGE

DOMAIN (PLD) DSLGen™ Design in

PD MDE (Model Driven

Engineering) in PLD

PL PL

http://softwaregenerators.com/papers/BeyondMde.wav




Engineering) in PLD Abstractions

PLINITIALLY, NO: OO Classes OO Methods PL Scopes PL Routines Routine Signatures PL Loops Control Flow Data Flow Aliasing …

http://softwaregenerators.com/papers/NoPLAbstractions.wav




Engineering) in PLD

PLAssociativeProgrammingCONSTRAINTS

(APCs)Initial DSLGen™

Architecture Representation

http://softwaregenerators.com/papers/APCDescription.wav




Engineering) in PLD

PLInitial DSLGen™

Architectural Layers

Iterative APC (e.g.,PD Loop)

PD Partion APC (e.g., edge or center)PD Design Entity (e.g., Pixel neighborhood specialized to partition)PD Component Definition (Method- Transform specialized to partition)

Implementation Neutral Specification (INS)

a b//Sobel Edge Detectionb=[(a Å s)2 +(a Å sp)2]1/2

Essence of Computation

a bS

SP

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

+

121000121

101202101

aaaaaaaaa

jijiji

jijiji

jijiji

*1*2*1*0*0*0*1*2*1

1,1,11,1

1,1,1,

1,1,11,1

aaaaaaaaa

jijiji

jijiji

jijiji

*1*0*1*2*0*2*1*0*1

1,1,11,1

1,1,1,

1,1,11,1

where ai,j is NOT an edge pixel

Essence of Computation

a bS

SP

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

+

000000000

000000000

aaaaaaaaa

jijiji

jijiji

jijiji

*0*0*0*0*0*0*0*0*0

1,1,11,1

1,1,1,

1,1,11,1

where ai,j IS an edge pixel

aaaaaaaaa

jijiji

jijiji

jijiji

*0*0*0*0*0*0*0*0*0

1,1,11,1

1,1,1,

1,1,11,1

Design Features Of Differing Generated Implementations

a b


DSLGen™

Von NeumannMachine

Multicore withThreads

Vector Machine

Von Neumann ImplementationProcessEdges

Sequentially

ProcessCenter

a b

Von Neumann Design FeaturesEdge Processing

Loops

1 Dimensional Loops

Von Neumann Design FeaturesCenter

Processing Loops

Neighborhood of c[idx13,idx14]

Processing Loops

Essence of

Sobel

(c[idx13,idx14] Å s[p15,q16])(c[idx13,idx14] Å sp[p15,q16])

Thread Based Implementation

Thread MgrEdges Thread

Center Slice Threads

a b

Thread Manager Design Features

Start Edge Thread Routine

Start Center Slice Routine for each Slice

Slice Up Center

Synchronize Thread Routines

Edge Thread Design Features

Synchronize

Thread

Edge Processing Thread One

Dimensional Loops

Center Slice Design Features

Loops Over

Center Slice

Synchronize

Thread

Loops Over c[i,j] Pixel

Neighborhood

Essence of Sobel Edge Detection

Center Processing

Thread

(c[i,j] Å s[p,q])(c[i,j] Å sp[p,q])

SIMD Implementation

ProcessCenter(RGB)

a b

SIMD Design FeaturesAn RGB Edge Loop

Generated WeightVectors

(c[idx3,idx4] Å dsarray9)(c[idx3,idx4] Å dsarray10)

Neighbor-hood Loops As SSE InstructionMacros

RGB Center Loops

The Problem Changing Platforms in Programming

Language (PL) Domain Requires Difficult Reprogramming Von Neumann to Multicore to Vector Processor Inter-related structures change across the

program PL-Based Abstractions Too Restrictive Conclusion: Non-PL Abstractions Needed

New Abstractions for DSLGen

Associative Programming Constraints (APC) Isolated design feature of an implementation

form Partial and provisional specification Retains domain knowledge Can be composed Can be manipulated (algebra of APCs)

Design Frameworks (formal “Design Patterns”) Large scale architectural framework

Logical Architecture (LA) when combined

APC’s Used in DSLGen Iteration Constraints

Loop Constraints Recursion Constraints

Partitioning Constraints (Natural) Matrix edges, corners, non-corner edges,

centers Upper triangular, diagonal, and more

Partitioning Constraints (Synthetic) Add design features to solution

Sobel Edge Detection Computation

Programmer’s Specification of Computation

Programmer’s Specification ofThe Platform

a b

Sobel Edge Detection Computation



a b

Programmers Specification of Computation

(DSDeclare Neighborhood s :form (array (-1 1) (-1 1)) :of DSNumber)(DSDeclare Neighborhood sp :form (array (-1 1) (-1 1))

:of DSNumber)(DSDeclare DSNumber m :facts ((> m 1)))(DSDeclare DSNumber n :facts ((> n 1)))(DSDeclare BWImage a :form (array m n) :of BWPixel)(DSDeclare BWImage b :form (array m n) :of BWPixel)

(Defcomponent w (sp #. ArrayReference ?p ?q) (if (or (== ?i ?ilow) (== ?j ?jlow) (== ?i ?ihigh) (== ?j ?jhigh)

(tags (constraints partitionmatrixtest edge))) (then 0) (else (if (and (!= ?p 0) (!= ?q 0)) (then ?q) (else (if (and (== ?p 0) (!= ?q 0)) (then (* 2 ?q)) (else 0)))))))(Defcomponent w (s #. ArrayReference ?p ?q) ….)

b = [(a Å s)2 +(a Å sp)2]1/2

a b

Built-In Def:(ai.j Å s) = (Σp, q (w(s)p , q * a i+p

, j+q )

CenterSpecializations

Go To Platform Spec

Edge

(ai.j Å s) = (p, q (w(s)p , q * a i+p , j+q)

a bS

SP

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

+

121000121

101202101

aaaaaaaaa

jijiji

jijiji

jijiji

*1*2*1*0*0*0*1*2*1

1,1,11,1

1,1,1,

1,1,11,1

aaaaaaaaa

jijiji

jijiji

jijiji

*1*0*1*2*0*2*1*0*1

1,1,11,1

1,1,1,

1,1,11,1

where ai,j is NOT an edge pixel

(ai.j Å s) = (p, q (w(s)p , q * a i+p , j+q)

a bS

SP

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

aaaaaaaaa

jijiji

jijiji

jijiji

1,1,11,1

1,1,1,

1,1,11,1 Å =

+

000000000

000000000

aaaaaaaaa

jijiji

jijiji

jijiji

*0*0*0*0*0*0*0*0*0

1,1,11,1

1,1,1,

1,1,11,1

where ai,j IS an edge pixel

aaaaaaaaa

jijiji

jijiji

jijiji

*0*0*0*0*0*0*0*0*0

1,1,11,1

1,1,1,

1,1,11,1

Return

IL Specializations Specialize IL(Defcomponent w (sp #.

ArrayReference ?p ?q) (if (or (== ?i ?ilow) (== ?j ?jlow) (== ?i ?ihigh) (== ?j ?jhigh) (tags (constraints

partitionmatrixtest edge))) (then 0) (else (if (and (!= ?p 0) (!= ?q 0))

(then ?q) (else (if (and (== ?p 0)

(!= ?q 0)) (then (* 2 ?q)) (else 0)))))))

SP-Edge1 (== ?i ?ilow)(Defcomponent w (sp-Edge1

#. ArrayReference ?p ?q) 0)

SP-Center5 (ELSE)(Defcomponent w (sp-Center5

#. ArrayReference ?p ?q)(if (and (!= ?p 0) (!= ?q 0))

(then ?q) (else (if (and (== ?p 0)

(!= ?q 0)) (then (* 2 ?q)) (else 0)))))

Return

Programmers Specification of the Platform



a b

Programmers Specification of the Platform



a b

Generation: Logical Architecture

….b = [(a Å s)2 + (a Å sp)2]1/2


Logical Architecture

Edge2

Set of Partitions

Edg

e1

Edg

e3

Edge4

Center5

Partially Translated INS Expression:b [i,j]= [(a[i,j] Ås[p,q])2 + (a[i,j]Åsp[p,q])2]1/2

Loop Constraint:(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S)}

SpecializationsOf

NeighbothoodsS and SP:

S-Edge1Sp-Edge1S-Edge2Sp-Edge2S-Edge3Sp-Edge3S-Edge4Sp-Edge4S-Center5Sp-Center5

Convolution Neighborhoods

Transforms

WPartestxRowCol...

Logical Architecture (Internal Form)

W method-transform component definition specialized to neighborhood spart-0-edge11

Partition APC modifying loop APC

Loop APC

Neighborhoods spart & sppart specialized toEdge11 partition

Component definitions for selected neighborhood spart-0-edge11

NB: Concrete Example where Spart & sppart are analogous to s & sp in abstract example.

Logical Architecture (Internal Form)

W method-transform component definition specialized to neighborhood spart-0-center15

Component definitions for selected neighborhood spart-0-center15

W.Spart Specialized to Center

Recall body of definition of W of sp

Return


W.Spart Specialized to Edge

w.Spart body specialized to

edge

Return


Generation: Logical Architecture(Synthetic Partitioning)

….

b = [(a Å s)2 + (a Å sp)2]1/2


Generation: Logical Architecture(Synthetic Partitioning)

Edge2

Edg

e1

Edg

e3

Edge4

Slicer: (forall (h) { 0<= h<=(m-1), eq(mod(h, Rstep(S-Center5-KSegs)), 0),Partestx(S-Center5-KSegs))

SpecializationsOf Neighbothoods

S and SP:S-Edge1Sp-Edge1S-Edge2Sp-Edge2S-Edge3Sp-Edge3S-Edge4Sp-Edge4S-Center5

Sp-Center5S-Center5-ASegSp-Center5-ASegS-Center5-KSegs

SP-Center5-KSegs

Center5-K

…..…..…..…..…..…..…..…..…..

ASlice: (forall (i j) {h<= i<min((h +RStep(S-Center5-KSegs),m), 0<=j<=(n-1), Partestx(S-Center5-ASeg)}

Partially Translated INS Expression:b [i,j]= [(a[i,j] Ås[p,q])2 + (a[i,j]Åsp[p,q])2]1/2

Center5-0

Center5-ASeg

Center5-KSegs

Generation: Logical Architecture(Cloning and Specializing)

….

b = [(a Å s)2 + (a Å sp)2]1/2


Generation: Logical Architecture(Cloning and Specializing)

Generation: Physical Architecture(Finding Design Framework)

….

b = [(a Å s)2 + (a Å sp)2]1/2


Generation: Physical Architecture(Finding Design Framework)

Generation Phases

….

b = [(a Å s)2 + (a Å sp)2]1/2


Demo

Performance with Threads

Performance with SIMD

DSLGen Tools Demo

Transformation and Type Inference Rule

Definitions

TransformationEngine

PatternEngine

Partial Evaluation

Engine

Generator Execution Unit

v Read Computation Specificationv Read Target Machine Specificationv Read List of Phasesv For each Phase

o Enable Transforms of that Phaseo Traverse Specification Applying Rewriting

Transforms v Write Out Generated Program

ComputationSpecification

TargetMachine

Specification

GeneratedGPL Program

Phase ListDefinitions

AssociativeProgramming

ConstraintDefinitions

InferenceEngines

Data Abstractions

Demo

Patents 8,060,857 – Automated partitioning of a

computation for parallel or other high capability architecture

8,225,277 – Non-localized constraints for automated program generation

8,327,321 - Synthetic partitioning for imposing implementation design patterns onto logical architectures of computations

End of Presentation

DSLGEN™ TOOLS DEMOJune, 2013

Ted J. BiggerstaffSoftware Generators, LLC

Tools Building Logical Architecture History Debugger Partial Evaluation Engine Synchronizing Design Decisions Pattern Matching Engine Transformation Engine Type Inference Engine Inference Engine

How Did LA Get Built?

b = [(a Å s)2 +(a Å sp)2]1/2

=

+

b

Å

s a

square

Å

sp a

square

sqrtLoop2d1

Loop2d2

Loop2d3

Loop2d2 (e1-c5)Loop2d3 (e6-

c10)

Loop2d4 ((e11-c15) = (e1-c5, e6-c10))

Loop2d5 ((e11-c15) =(e1-c5, e6-c10))

bi,j

ak,l sp,q at,u

spv,w


Domain Engineer Debugging

Domain Engineer’s Job is DSLGen Extensions Problem: Analyzing Creation of Logical

Architecture How are loop constraints and index names

created? How are partitions created, combined &

specialized? How do design decisions (e.g., Idx1 -> Idx3 )

happen? Tools for Analyzing a Generation History? History Debugger

History Debugger

HistoryTree at TopLevel (total

tree typically

~3K nodes)

Bindings of selected history

node used to rewrite AST

AST beforerewriting

AST afterrewriting

History Debugger

Selected history node (e.g., transform,

routine or trace info)

Bindings created by

operation of selected

node

Dialog to search

history tree

Bookmarked locations (for debugging or presentation

s).

History Debugger Dialogs available from History Debugger

Architecture browser (as used earlier to display LA)

Examine transforms (as used earlier to show w.part)

Inspect any object (e.g., examine slots of idx3) Open source file of a DSLGen™ routine in an

editor (e.g., Gnuemacs)


Degenerate Loops for Edges?

void Sobel Edges9( ) { /* Edge1 partitioning condition is (i=0) */ {for (int j=0; j<=(n-1);++j) b [0,j]=0;}

_endthread( ); }

Architecture Specializations

Specializations of W.Spart

W.Spart specialized to center

W.Spart body specialized to

edge

Physical Architecture Inline the Intermediate Language (IL)

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S-Edge1)} b [i,j]=[(a[i,j] Ås-edge1[i,j])2 + (a[i,j]Åsp-edge1[i,j])2]1/2

Partestx Å


(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S-Edge1)} b [i,j]=[(a[i,j] Ås-Edge1[i,j])2 + (a[i,j]Åsp-edge1[i,j])2]1/2

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((sum(p q) {0<= p<=2, 0<=q<=2} (* (aref a (row s-Edge1 a[i,j] p q)

(col s-Edge1 a[i,j] p q) ) (w s-Edge1 a[i,j] p q))))2

+ (convolution using sp-Edge1)2]1/2

Partestx Å

row colw


(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S-Edge1)} b [i,j]=[(a[i,j] Ås-Edge1[i,j])2 + (a[i,j]Åsp-Edge1[i,j])2]1/2

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((sum (p q) {0<= p<=2, 0<=q<=2} (* (aref a (row s-Edge1 a[i,j] p q)



Partestx Å

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((sum (p q) {0<= p<=2, 0<=q<=2} (* (aref a (+ 0 (+ p -1))

(+ j (+ q -1))) 0)))2 + (“convolution using sp-Edge1” )2]1/2

row colw


(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S-Edge1)} b [i,j]=[(a[i,j] Ås-Edge1[i,j])2 + (a[i,j]Åsp-Edge1[i,j])2]1/2

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((sum (p q) {0<= p<=2, 0<=q<=2} (* (aref a (row s-Edge1 a[i,j] p q)



Partestx Å

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((sum(p q) {0<= p<=2, 0<=q<=2} (* (aref a (+ 0 (+ p -1))


(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) } b [0,j]=[ 0 + 0]1/2

row colw

(…* 0) (…* 0)

Physical Architecture(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), Partestx(S-Edge1)} b [i,j]=[(a[i,j] Ås-Edge1[i,j])2 + (a[i,j]Åsp-Edge1[i,j])2]1/2

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((forall (p q) {0<= p<=2, 0<=q<=2} (* (aref a (row s-Edge1 a[i,j] p q)



Partestx Å

(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) )} b [0,j]= [ ((forall (p q) {0<= p<=2, 0<=q<=2} (* (aref a (+ 0 (+ p -1))


(forall (i j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) } b [0,j]=[ 0 + 0]1/2

row colw

(…* 0) (…* 0)

(forall (j) { 0<= i<=(m-1), 0<=j<=(n-1), (i==0) } b [0,j]= 0

PE

Degenerate Loops for Edges?

void Sobel Edges9( ) { /* Edge1 partitioning condition is (i=0) */ {for (int j=0; j<=(n-1);++j) b [0,j]=0;}

_endthread( ); }

Analyzing Behavior with History Debugger


Synchronizing Design Decisions

How did index variables get synchronized? di,j and ck,l and ct,u

Answer: Loop constraint combining transforms generated fix up transforms to be executed later Loop2d4 combo transform generated

K -> I, T-> I, L-> J, U->J transforms NB: Loop constraints for neighborhoods s and

sp elided from example for simplicity


Pattern Language Left-Hand-Side (LHS) of transformations Reverse quoting language

Non-syntactically enhanced items are literals (e.g., “a”) Syntactically enhanced are operators E.G., ?x is variable, $(op …) is a pattern operator

Full backtracking on failure (via “continuations”) Extensible – User can define new operators Internal – Lambda tree + fail stack of

continuations De-compiler for internal to external Turing complete

Example Pattern Constructs

$(Por pat1 pat2….patn) $(Pand pat1 pat2 …patn) $(pnot pat) $(none pat1 pat2 … patn) $(remain ?x) $(spanto ?x <pattern>) $(bindvar ?x <pattern>) $(bindconst ?x

<constant>) $(pcut) $(pfail) $(pmatch <pattern>

<data>)

$(within <pattern>) $(ptest <lisp function of

one argument>) $(papply function ?arg1 ?

arg2 ... ?argn) $(pat <variable>) $(plisp <Lisp Code>) $(psuch slotname ?vbl

<pattern>) $(ptrace <lisp

expression> label) $(plet <let list>

<pattern>) …others …


Transformations Pattern Language used to specify LHS Transformations

Format Preroutines and postroutines (like before and

after methods) Inheritance

Example TransformationsTransform(=> PartitioningCompositeLeaf LocalizeAndPartition image `$(pand #.LeafOperator

$(psuch dimensions ?op ((,_Member ?iiter (,_Range ?ilow ?ihigh)) (,_Member ?jiter (,_Range ?jlow ?jhigh)))) $(por ($(spanto ?taglessremain (tags)) ?thetags) $(psucceed)))

`(,leaf ?newleaf (tags (commasplice ?newtaglist))) enablePartitioningCompositeLeaf nil all)

Method-Transform (Defines IL)(Defcomponent w (sp #. ArrayReference ?p ?q) (if (or (== ?i ?ilow) (== ?j ?jlow) (== ?i ?ihigh) (== ?j ?jhigh) (tags (constraints partitionmatrixtest edge))) (then 0) (else (if (and (!= ?p 0) (!= ?q 0)) (then ?q) (else (if (and (== ?p 0) (!= ?q 0)) (then (* 2 ?q)) (else 0)))))))

(defconstant LeafOperator `$(por (,leaf ?op) $(pand $(ptest atom) ?op)))

Use of Example Transformation

Transform Viewer

Preroutine handles

bookkeeping

operations after LHS

match

Type object where

transform lives

Phase where it is enabled to

execute

LHS patternRHS

Transformation Pattern Matching

Transformation Definition(=> PartitioningCompositeLeaf

LocalizeAndPartition image `$(pand #.LeafOperator

$(psuch dimensions ?op ((,_Member ?iiter (,_Range ?

ilow ?ihigh)) (,_Member ?jiter (,_Range ?

jlow ?jhigh)))) $(por ($(spanto ?taglessremain (tags)) ?thetags)

$(psucceed))) `(,leaf ?newleaf (tags (commasplice ?

newtaglist))) enablePartitioningCompositeLeaf nil all)

WHERE

(defconstant LeafOperator `$(por (,leaf ?op) $(pand $(ptest

atom) ?op)))

DSLGen Internal StateAST before rewrite = (leaf d (tags (itype

colorimage)))AST after rewrite = (leaf colorpixel1 (tags (itype

colorpixel) (constraints loop2d1)))

__________________________________________________(dimension d) = ((_Member iiter6 (_Range 0 99 1)) (_Member jiter6 (_Range 0 99

1)))__________________________________________________Bindings After Matching and Preroutine =((?newleaf colorpixel1) (?idx1 idx1) (?idx2 idx2) (?theapc loop2d1) (?inewtype colorpixel) (?newtaglist ((itype colorpixel) (constraints loop2d1))) (?thetags (tags (itype colorpixel) (constraints loop2d1))) (?taglessremain (leaf d)) (?jhigh 99) (?jlow 0) (?jiter jiter6) (?ihigh 99) (?ilow 0) (?iiter iiter6) (?op d) (?phase localizeandpartition) (?defclass image) (?transformname partitioningcompositeleaf))

Transformations Pattern Language used to specify LHS Transformations

Format Preroutines and postroutines (like before and

after methods) Inheritance – Up type hierarchy

If there is no “(row sp-0-center15 …)” specialization, “(row sp …)” will be used when in-lining definitions


Example Type Inference Rules

(DefOPInference ImageOperators (ImageOperators image iatemplate) 1)(DefOPInference ImageOperators (ImageOperators pixel iatemplate) 1)(DefOPInference ImageOperators (ImageOperators channel iatemplate) 1)(DefOPInference AOperators (AOperators DSNumber DSNumber) DSNumber)(DefOPInference RelationalOperators (RelationalOperators (oneormore t)) DSSymbol)(DefOPInference LogicalOperators (LogicalOperators (oneormore t)) DSSymbol)(DefOpInference AssignOp (AssignOp t t) last) ; resultant type is infered type of the last arg (DefOpInference ProgmOp (ProgmOp (oneormore t)) last)(DefOpInference IfOp (IfOp t t t) 2)(DefOpInference IfExprOp (IfExprOp t t t) 2)(DefOpInference IfOp (IfOp t t) 2)(DefOpInference ThenOp (ThenOp (oneormore t)) last)(DefOpInference ElseOp (ElseOp (oneormore t)) last)(DefOpInference ListOp (ListOp (oneormore t)) last)

(DefMethodInference IATemplate (Prange IATemplate image DSNumber DSNumber Iterator) Range)(DefMethodInference IATemplate (Qrange IATemplate image DSNumber DSNumber Iterator) Range)(DefMethodInference IATemplate (W IATemplate channel t t) DSNumber)


Inference Engine Given

(Idx1 == 0) from partitioning condition (0 <= Idx1 <= (m -1)) from loop range (m > 1) from :facts slot of m

Is partial evaluation of “(Idx1 == (m – 1))” true, false or unknown for all m?

False. “(m >1)” fact eliminates the only possible true case (i.e., for (m == 1)).

Inference engine based on Fourier-Motzkin elimination.

Code For Image Average/* Definitions from scope SCOPE1: */ int M = 100; int N = 100; BWPIXEL IMAGEAVG (DSNUMBER M, DSNUMBER N, BWIMAGE A[M][N], BWIMAGE B[M][N]) {{ /* DSLGen (Version 0 Revision 2) generated this program at 3:26:38 pm on 11/Jun/2009 */ int IDX3 ; int IDX4 ; int P5 ; int Q6 ; int ANS1 ; {/*Initial values from scope SCOPE3 are ((IDX4 0) (IDX3 0))*/ int IDX4 = 0; int IDX3 = 0; for (IDX3=0; IDX3<=(M - 1); ++IDX3) {{ for (IDX4=0; IDX4<=(N - 1); ++IDX4) {{{/*Initial values from scope SCOPE4 are ((ANS1 0) (Q6 0) (P5 0))*/ int ANS1 = 0; int Q6 = 0; int P5 = 0; for (P5=((IDX3 == 0) ? 1:0); P5<=((IDX3 == (M - 1)) ? 1:2); ++P5) {{for (Q6=((IDX4 == 0) ? 1:0); Q6<=((IDX4 == (N - 1)) ? 1:2); ++Q6) {{ANS1 += ((*((*(A + ((IDX3 + (P5 + -1))*N))) + (IDX4 + (Q6 + -1)))) * ((((IDX3 == 0) || (IDX3 == (M - 1))) && ((IDX4 == 0) || (IDX4 == (N - 1)))) ? 0.25: (((IDX3 == 0) || ((IDX3 == (M - 1)) || ((IDX4 == 0) || (IDX4 == (N - 1))))) ? 0.166666666666667:0.111111111111111))); }}}} (*((*(B + (IDX3*N))) + IDX4)) = ANS1; }}}}}}}}

End of Tools Demo

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Reuse: Right Idea, Wrong representation?