Research Article A Low-Noise Delta-Sigma Phase …downloads.hindawi.com/journals/tswj/2014/521717.pdfRF phase modulation for GSM/EDGE polar transmitters, achieving good trade-o between

Research ArticleA Low-Noise Delta-Sigma Phase Modulator forPolar Transmitters

Bo Zhou

School of Information and Electronics Beijing Institute of Technology Beijing 100081 China

Correspondence should be addressed to Bo Zhou zhoubo07biteducn

Received 26 November 2013 Accepted 17 January 2014 Published 25 February 2014

Academic Editors P Colantonio and F L Tofoli

Copyright copy 2014 Bo Zhou This is an open access article distributed under the Creative Commons Attribution License whichpermits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

A low-noise phase modulator using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-lockedloop (PLL) is fabricated in 018120583mCMOS for GSMEDGE polar transmitters A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity Experimental results show that the presentedarchitecture performs RF phase modulation well with 20mW power dissipation from 16V supply and achieves the root-mean-square (rms) and peak phase errors of 4∘ and 85∘ respectively The measured and simulated phase noises of minus104 dBcHz andminus120 dBcHz at 400-kHz offset from 18-GHz carrier frequency are observed respectively

1 Introduction

Polar transmitters can achieve both high power efficiencyand good linearity and become growing popular in modernwireless systems [1 2] Polar modulation utilizes envelope 119860and phase Φ components to represent the baseband symbolsinstead of the conventional 119868119876 format A constant-envelopephase-only signal going through a phase-modulation pathis multiplied with the signal envelope going through anenvelope-modulation path in a switched-mode power ampli-fier (PA) to reconstruct the original baseband complex signal(119868+119895119876)The high power efficiency is achieved by using a non-linear switched-mode PA to handle the constant-envelopephase-modulated RF signal and the good linear transmissionis accomplished by modulating the signal envelope throughthe supply voltage of the switched-mode PA [3]

The delta-sigma (ΔΣ) fractional-N phase-locked loop(PLL) [4] enables phase modulation function when the frac-tional division ratio ismodulated by the baseband signal sim-plifying the overall transmitter architecturewithout requiringdigital-to-analog converters (DACs) and RF upconverters[5] Figure 1 shows the existing phase modulation methodsbased on fractional-N PLLs for polar transmitters Sincethe conventional PLL bandwidth is not wide enough toaccommodate the required modulation symbol rate digital

precompensation [6] or two-pointmodulation [7] techniquesare employed to overcome the PLL bandwidth limitationbut are prone to quantization noise jamming from the ΔΣmodulator (DSM)

The quantization noise qn of the DSM needs be con-cerned for a PLL The existing noise cancellation technique[4 8] requires good linearity and strict matching of theanalog charge pump (CP) circuit complicating circuit designThe reported finite-impulse-response (FIR) noise filteringmethod [9] effectively suppresses DSM noise but causesunexpected signal attenuation when the DSM input isvarying phase component rather than fixed

In this paper with simplified inverse-FIR and -PLL digitalfilters proposed to compensate for the signal attenuation anFIR-embedded ΔΣ fractional-N PLL is presented to performRF phase modulation for GSMEDGE polar transmittersachieving good trade-off between transmitter noise andlinearity

The paper is organized as follows Section 2 presents theFIR-embedded ΔΣ phase modulation and clarifies the pro-posed FIR-compensated low-noise architecture In Section 3detailed design implementations are described and simplifiedinverse-FIR digital compensation filter is proposed followedby experimental results in Section 4 Finally conclusion isgiven in Section 5

Hindawi Publishing Corporatione Scientific World JournalVolume 2014 Article ID 521717 8 pageshttpdxdoiorg1011552014521717

2 The Scientific World Journal

CORDIC

Differentiator

Timealignment

Compensationfilter

VCO

DividerPLL

Envelopemodulation

LPFIQGen

I

QIQ

A

A

divideFref

Fref

ΦΦ

PFDandCP

PA

modulatorΔΣ1

2120587middotdΦ

dt

(a)

DACDelaymatch

CORDICIQGen

I

QIQ

A

AΦΦ

Differentiator

Timealignment

VCO

DividerPLL

Envelopemodulation

LPF

divideFref

Fref PFDandCP

PA

modulator

divide

1

2120587middotdΦ

dt

ΔΣ

KVCO

KVCO

(b)

Figure 1 Polar transmitters with ΔΣ PLL based phase modulation (a) digital precompensation and (b) two-point modulation techniques

Chargepump

VCO

MMD

FIR Frequency to phase

Out

In

In

qn

DSM

Noise TF

Out

LPFH(s)

divideN + p0

divideN + pkminus1

PFD0

PFDkminus1(ICP )

Fref

Fref

MCMC

0 MC1 MCkminus1

modulator D1n

D2n Dkminus1

n

1k

+

+

+ TFFIR

G(s) =H(s) middot ICP middot KVCO

N middot s + H(s) middot ICP middot KVCO

DSM and shifted DFFs

DAC and filterG(s)

⋱⋱

middot middot middot





(KVCO )

ΔΣ

Σ

zminusn zminusn zminusn

2120587 int(middot)dt

Figure 2 Conceptual diagram and signal model of FIR-embedded ΔΣ PLL with DSM noise suppression

2 FIR-Compensated ΔΣ Phase Modulation forPolar Transmitters

21 FIR-Embedded ΔΣ Fractional-N PLL Figure 2 illus-trates conceptual diagram and small-signal model of FIR-embedded ΔΣ fractional-N PLL For the embedded FIR filterwith a transfer function (TF) shown in (1) the numerator isperformed by 119896-tap shifted D flip-flops (DFFs) with a delaydepth of 119899 and by 119896-path multimodulus dividers (MMDs)and phase-frequency detectors (PFDs) and the denominatoris done by a 119896-branch charge pump (CP) with 119896-phase inputs[9] The multiple MMDs in parallel with sequential controlbits from shifted DFFs perform FIR filtering on the DSMoutput

TFFIR =(1 + 119911

minus119899

+ 119911minus2119899

+ 119911minus3119899

+ sdot sdot sdot + 119911minus(119896minus1)119899

)

119896 (1)

Under PLL reference clock 119865ref the notch frequencyof FIR filter is located at multiples of 119865ref(119899 times 119896)) thus

the DSM output is conducted low-passed filtering While thequantization noise qn is suppressed the signal phase sentto the DSM is also attenuated with linearity degradationTherefore a digital compensation filter with inverse-FIRfeature shown in (2) needs to be added before the DSMto offset the signal attenuation without affecting the noisesuppression Obviously high 119899 times 119896 value complicates theinverse-FIR filter design

TFInverse-FIR =119896

(1 + 119911minus119899 + 119911minus2119899 + 119911minus3119899 + sdot sdot sdot + 119911minus(119896minus1)119899) (2)

The signal path from the DSM input to the voltage-controlled oscillator (VCO) output excluding the FIR fil-tering is functionally equivalent to a DAC with a PLL TF119866(119904) followed by amultiplication factor119865ref and an integratorwith frequency-phase conversion [10] The PLL TF 119866(119904) haslow-passed feature with a limited signal bandwidth whichinversely degrades the phase-path bandwidth Thereforeanother digital compensation filter with inverse-119866(119904) feature

The Scientific World Journal 3

Inverse FIRDigital compensation filter

LC VCO

MMD

(DSM)

MCInverse PLL

CORDIC

Timealignment

Envelopemodulation

LPFIQGen

I

QIQ

A

AFref

ΦΦ PFDandCP

divideFref

Differentiator

modulator

Class-EPAFB

Shifted DFFs (n = 2 k = 8)

VC

fin

65

MH

z

ΔΣ

1

2120587middotdΦ

dt

FB⟨0⟩

FB⟨0⟩

FIR-embedded ΔΣ fractional-N PLL

Figure 3 Proposed low-noise ΔΣ phase modulator with compensated-FIR filtering for polar transmitters

shown in (3) a differentiator with phase-frequency conver-sion and a divider-by-119865ref also should be added before thePLL to ensure the signal fidelity while phase modulation isperformed

TFInverse-PLL =1

119866 (119904)= 1 +

119873 times 119904

119867 (119904) times 119868CP times 119870VCO (3)

22 Proposed Low-Noise Phase Modulator for Polar Transmit-ters Figure 3 gives the proposed low-noise delta-sigma phasemodulator for polar transmitters based on the discussionabove 119868119876 components of GSMEDGE signals are generatedbased on a look-up table technique The coordinate rotationdigital computer (CORDIC) algorithm [11] accomplishes theconversion from 119868119876 to polar coordinate 119860Φ with theoriginal signal bandwidth of 200 kHz spread to more than600 kHz Here the phase- and envelope-path bandwidths areset to 1MHz

Considering the PLL inherently contains a multiplicationfactor of 119865ref and an integrator in function a differentiatorwith phase-frequency conversion and a divider-by-119865ref areintroduced A digital filter having the equivalent inverse-119866(119904)TF shown in (3) compensates for the low-pass property of thePLL andwidens the signal pathThe other digital filter havingthe equivalent inverse-FIR TF depicted in (2) is employed tooffset the gain attenuation by the FIR filtering

A 4th-order type-II fractional-N PLL with FIR-embedded ΔΣmodulation and digital compensation filters isdesigned to perform RF phase modulation Baseband digitalphase is converted to RF analog phase by controlling thefractional division ratio via the DSM In order to suppress theDSMnoise the FIR filtering with 119899 = 2 119896 = 8 is chosenWith119865ref of 26MHz the notch frequency located at multiples of1625MHz is achieved which not only effectively suppressesthe quantization noise but also does not complicate theinverse-FIR filter design

3 Design Implementations

31 Baseband Component Generation Figure 4 gives theblock diagram of GMSK based GSM and 8PSK basedEDGE signal generation Under symbol rate of 270833 kSps65MHz 119868119876 components are generated based on look-uptable technique [12] where the tap coefficients of the 5-symbol-length Gaussian and shaping filters with a BT valueof 03 a modulation index ℎ of 05 and an oversampling ratio(OSR) of 24 are stored in a read-only memory (ROM) A221minus1 pseudo random bit source (PRBS) with a normal burstframe architecture produces the transmit data The symbolrotation operation with 31205878 phase shift ensures that theEDGE signal has the envelope component larger than 022Vwhich lowers the nonlinear AM-AMandAM-PMdistortionsof the PA in polar transmitters

The modified CORDIC [11] algorithm with low hardwarecost is employed to accomplish the conversion from 119868119876 topolar coordinate119860Φ The algorithm typically converges to avery small deviation after 10th or 11th iterationTherefore 16-times iteration is enough for the conversion resolution For119894 = 1 and input vector (119868 119876) from GSMEDGE signal

1199092= 119876 119910

2= minus119868 120579

2= 05 (4)

And the remaining iterations (for 119894 = 2 sim 16) are shown in(5) and finally the desired phase and envelope componentsare given in (6)

119889119894=

1 119910119894ge 0

minus1 119910119894lt 0

119909119894+1= 119909119894+ 119889119894sdot 2minus2(119894minus2)

sdot 119910119894

119910119894+1= 2 [119910

119894minus 119889119894sdot 119909119894] 120596

119894=tanminus12minus(119894minus2)

120587

120579119894+1= 120579119894+ 119889119894sdot 120596119894

(5)

120601 = 120587 sdot 12057917 119860 =

11990917

164676 (6)


PRBS Differentialencoder

Polarity conversion

Gauss filterI

Q

minus1 10

minus1

1

0BT = 03

OSR = 24and integral(h = 05)

(a)

PRBS Group into Grayencoder

I

Q

Symbolmapping

Symbolrotation

OSR = 24 andShaping filter(BT = 03)

minus1

0

1

minus1

0

1

minus1

0

1

minus1 0 1minus1 0 1minus1 0 1

3bit triplets

(b)

Figure 4 Block diagram of baseband 119868119876 signal generation (a) GMSK for GSM and (b) 8PSK for EDGE

0 100 200 300 400 500minus390minus260minus130

260390

1300

0

05

1

15

025

075

125

Envelope component A (V)

Frequency component fin (kHz)

Time (120583s)

Figure 5 Simulated envelope and frequency components for EDGEsignal

For the given five consecutive phase component inputs aderivation algorithmusing a five-point-interpolationmethodwith phase jump preprocess is shown in (7) under a samplingclock of 65MHz to accomplish the phase-frequency conver-sion and generate the desired frequency component

119891in119896 =65 times 10

6

24120587(120601119896minus2

minus 8 sdot 120601119896minus1

+ 8 sdot 120601119896+1

minus 120601119896+2) (7)

Figure 5 gives the simulated baseband components forEDGE signal Both the envelope component with an ampli-tude range of 022ndash144V and the frequency component witha range of minus340ndash340 kHz are observed A peak frequencyoccurs when the envelope has a local minimum [2] ForGSM signal both a constant envelope of 1V and a frequencyrange of minus70ndash70 kHz are achievedThe frequency componentdivided by 119865ref (26MHz) is amplified by the sequent digitalcompensation filters with high-passed feature which is stillsmall enough for the DSM input not to cause the overflow

32 Proposed Digital Compensation Filters Since thefractional-N PLL has a low-passed feature with additional

01 05 10 15 20 25 30Frequency (MHz)

100

50

0

minus100

minus50

Gai

n (d

B)

FIR

Ideal inverse FIRProposed inverse FIR

Compensated TF

Figure 6 Simulated frequency responses of FIR-compensatedfilters ideal versus proposed implementations

IIR compensation filter

Proposed phase modulator

1 10 100 1000Frequency (kHz)

25

0

minus100

minus75

Gai

n (d

B)

minus50

minus25

FIR-embedded PLL

Figure 7 Simulated frequency response of presented phase modu-lator

FIR attenuation digital compensation filters need to bedesigned not only to compensate for the limited path


GND

VDD

COICP

UP⟨0⟩ UP⟨1⟩ UP⟨2⟩ UP⟨3⟩ UP⟨4⟩ UP⟨5⟩ UP⟨6⟩ UP⟨7⟩

DN⟨0⟩ DN⟨1⟩ DN⟨2⟩ DN⟨3⟩ DN⟨4⟩ DN⟨5⟩ DN⟨6⟩ DN⟨7⟩

Figure 8 Multiphase charge pump schematic

M1 M2

M3 M4

C

Switch bank

C0 C0S0

C1 C1S1

C4 C4S4

VON

VC

RL

CL

L3

L1 L2

IVCO

VOP

Figure 9 LC VCO schematic

bandwidth caused by the PLL but also to offset the gainattenuation due to the FIR filtering

TFInverse-FIR =8

(1+119911minus2+119911minus4+119911minus6+119911minus8+119911minus10+119911minus12+119911minus14)

(8)

TFInverse-FIR =2

(1 + (2227) sdot 119911minus2 + (0527) sdot 119911

minus3) (9)

Larger FIR parameter 119899 or 119896 contributes to lesser DSMnoise but makes the inverse-FIR filter more complex As atrade-off between the noise and complexity 119899 = 2 119896 = 8

is chosen However the ideal inverse-FIR filter conforming to(8) is prone to instabile responsewith 14th-order high-passedfeature Under 65MHz sampling clock a simplified 3rd-order filter is proposed in (9) which features unobvious high-passed or slight overshoot response but has the same propertyas the ideal inverse-FIR one within the desired frequency

band up to 1MHz The circuit-level simulation results infrequency response for both ideal and proposed inverse-FIRfilters are depicted in Figure 6The proposed implementationis simple and stabile with slight overshoot but has the samecompensation feature within desired frequency band whencompared to the ideal one

Since the type-II PLL with 4th-order TF inherently has4 poles and 1 zero in 119866(119904) accordingly there are 4 zerosand only 1 pole existing in the inverse-119866(119904) TF To ensurethe compensation filter stable additional 3 poles with fartherlocations are added to the inverse-119866(119904)filter without affectingthe frequency responsewithin the desired frequency band Tofurther simplify filters the proposed 3rd-order inverse-FIRand 4th-order inverse-119866(119904) filters are combined together byemploying a 7th-order infinite-impulse-response (IIR) digitalfilter with a high-pass property Figure 7 shows the simulatedfrequency response of the presented phase modulator Forthe PLL with a loop bandwidth of 100 kHz the 7th-order IIRfilter has a high-pass propertywith 100-kHz cut-off frequencyand then rolls off at 13MHz As a result the phase-pathbandwidth of 1MHz is achieved The frequency component119891in divided by119865ref and then amplified by the IIR filter is smallenough for the DSM input not to cause overflow

33 PLL Core Modules To ensure phase-modulation lin-earity it is important to ensure strict match of the TFsbetween the inverse-119866(119904) filter and the fractional-N PLLConsidering that the PLLTF is dependent onprocess voltageand temperature (PVT) variations and the compensationfilter is digitally fixed thus in most cases the PLL loop-gaincalibration or constant 119868CP119870VCO techniques [13] need to beemployed However for the proposed design the VCO gain119870VCO varies little under small control voltage range and thecharge pump current 119868CP is external reconfigurable and thelow-passed filter (LPF) of the PLL is off-chip and thus fixedAll these benefit the PLL TF robust over PVT

With embedded FIR filtering the 4th-order type-II PLLwith 100-kHz bandwidth employs eight PFDs in paralleland all the lead-lag phase errors converted to push-pull


CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB

Prescaler Multiple in parallel

2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]

Figure 10 PS-based MMDmodule

INPINN

OUTP

OUTN

Figure 11 CML divider-by-2 schematic

pulse currents are summed at the output of the 8-phasecharge pump The schematic of the 8-phase charge pumpis shown in Figure 8 Cascode biasing architecture helps toreduce switching noise from the multiple current switchesand improves static and dynamic current match betweenthe up and down branches The current 119868CP is externalreconfigurable to ensure 119868CP119870VCO constant

The summed push-pull error current is low-passed fil-tered to generate an error control voltage 119881

119862 which tunes

the sequent VCO shown in Figure 9 The VCO employsthe conventional cross-coupled three-transistor differentialarchitecture with LC tankTheMIM switched capacitors hav-ing high quality factor are used for binary-weighted coarsetuning by a 5-bit control word to achieve plusmn15 frequencytuning range while an NMOS accumulation-mode varactoris employed for fine frequency tuning by the input controlvoltage 119881

119862 An inductor 119871

3is inserted between the current

source M2 and the cross-couple pair M3-M4 to reduce thesecond-order harmonic noise and the embedded RC LPFsuppresses the bias noise

The VCO differential output is sent to the sequentMMD and compared to the reference clock Figure 10 showsphase shifter (PS) based MMD [9 14] module to providea programmable division ratio of 64ndash127 controlled by thebaseband phase signal via the DSM The high frequencycurrent-mode-logic (CML) divider with a fixed division ratio

LC VCO

PFD amp CPMMDCML4

DSM amp digital filters

SPI

S4P

FIR

Figure 12 Chip micrograph

of 4 generates quadrature output phases which are shapedto nonoverlapping quadrature clocks to ease the timingrequirement of logic circuits and are fed into eight parallelPS-based MMDs with 4-stage single-ended 23 prescalerssupporting the division ratio of 16ndash31 The CML divider-by-4 is composed of two-stage cascaded dividers-by-2 Figure 11gives the schematic of the CML divider-by-2 which is similarto two-stage cross-coupled latch architecture

Considering that fewer DSM output levels result insmaller instantaneous phase error at the PFD output andthus less phase noise and on the other hand the widerDSM output levels have more efficient randomization anddithering and generate less fractional spurs to the PLL [15]the DSM employs 4th-order single-loop architecture [14] asthe trade-off between in-band noise and fractional spurs

4 Experimental Results

Theproposed digital compensation filters and FIR-embeddedfractional-N PLL are fabricated in 018 120583mCMOS and 16-bitbaseband components are generated in a field programmablegate array (FPGA) Figure 12 gives the chip micrograph

The Scientific World Journal 7Lo

g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150

Ref minus50dBcHzCarrier powerminus785dBm

Mkr1 399kHzminus1043dBcHz

100 kHz 100MHz

10dBdiv

1

Rawsmoothed

Figure 13 Measured phase noise of fractional-N PLL

with the active core area of 2mm2 and the measured powerdissipation of 20mW from a 16V supply excluding theclass-E PA In order to save chip pads on-chip 4-bit series-to-parallel conversion (S4P) and off-chip 4-bit parallel-to-series conversion (P4S) are used to accomplish the datacommunication between the chip and FPGA

The simulated and measured phase noise depicted inFigure 13 of the fractional-N PLL dominating the phasemodulator system noise isminus120 andminus104 dBcHz at 400-kHzoffset frequency from the oscillating frequency of 18 GHzrespectively The PLL bandwidth of 100 kHz is observedwhich is compensated by the digital filters to ensure thephase-path bandwidth of 1MHzThe measured tuning rangeand gain of the LC VCO centered at 18 GHz are plusmn15and 5MHzV respectively The VCO has a small controlvoltage range of minus70ndash70mV which contributes to small119870VCOvariation with PVT

Figure 14 shows the simulated transient response of theproposed modulator for 8PSK signal The phase modulationperformance can be indirectly estimated by observing thetracking performance of VCO control voltage 119881

119862with base-

band frequency component 119891in Both a fixed delay causedby the limited path bandwidth (1MHz) and a fixed multi-plication factor caused by the VCO gain 119870VCO (5MHzV)are observed between the curves of 119891in and 119881

119862with similar

waveforms The presented architecture performs RF phasemodulation well with slight phase ripples rising from littleDSM quantization noise and VCO phase noise

Figure 15 shows the transmitter output constellationfor GMSK The root-mean-square (rms) and peak phaseerrors are 4∘rms and 85

∘

peak respectively meeting error vectormagnitude (EVM) requirements [16] of GMSK Due to littlenonlinearity caused by slight TF mismatch between thecompensation filter and PLL the deviation of the symbolvectors from the four homocentric points is observed in theconstellation The loop gain autocalibration technique [13]as discussed above ensuring 119868CP119870VCO constant and thus TFstrict matching may be considered to further optimize themodulation linearity

minus390minus260minus130

260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200

Figure 14 Simulated modulation performance of proposed archi-tecture for 8PSK

minus15

15

Figure 15 Transmitter output constellation for GMSK

5 Conclusions

A phase modulator employing FIR-compensated ΔΣ PLL isfabricated in 018120583mCMOSwith baseband components gen-erated by FPGA Digital compensation filters are proposed totrade off the noise and signal integrality The experimentalresults show that the presented architecture performs RFphase modulation correctly with good noise and linearityperformances

Conflict of Interests

The author declares that there is no conflict of interestsregarding the publication of this paper

Acknowledgment

The author would like to thank the National Natural ScienceFoundation of China (no 61306037) for the financial sup-port

References

[1] J Lopez Y Li J D Popp et al ldquoDesign of highly efficientwideband RF polar transmitters using the envelope-trackingtechniquerdquo IEEE Journal of Solid-State Circuits vol 44 no 9pp 2276ndash2294 2009


[2] C Mayer B Neurauter G Marzinger C Munker and RHagelauer ldquoA robust GSMEDGE transmitter using polarmodulation techniquesrdquo in Proceedings of the 8th EuropeanConference on Wireless Technology pp 93ndash96 Paris FranceOctober 2005

[3] J Mehta V Zoicas O Eliezer et al ldquoAn efficient linearizationscheme for a digital polar EDGE transmitterrdquo IEEETransactionson Circuits and Systems II vol 57 no 3 pp 193ndash197 2010

[4] A Swaminathan K J Wang and I Galton ldquoA wide-bandwidth24GHz ISM band fractional-N PLL with adaptive phase noisecancellationrdquo IEEE Journal of Solid-State Circuits vol 42 no 12pp 2639ndash2650 2007

[5] R B Staszewski J L Wallberg S Rezeq et al ldquoAll-digital PLLand transmitter for mobile phonesrdquo IEEE Journal of Solid-StateCircuits vol 40 no 12 pp 2469ndash2482 2005

[6] M H Perrott T L Tewksbury III and C G Sodini ldquoA 27-mWCMOS fractional-N synthesizer using digital compensationfor 25-Mbs GFSK modulationrdquo IEEE Journal of Solid-StateCircuits vol 32 no 12 pp 2048ndash2060 1997

[7] M Youssef A Zolfaghari BMohammadi H Darabi and A AAbidi ldquoA low-power GSMEDGEWCDMA polar transmitterin 65-nm CMOSrdquo IEEE Journal of Solid-State Circuits vol 46no 12 pp 3061ndash3074 2011

[8] S Pamarti L Jansson and I Galton ldquoA wideband 24-GHzdelta-sigma fractional-N PLLwith 1-Mbs in-loopmodulationrdquoIEEE Journal of Solid-State Circuits vol 39 no 1 pp 49ndash622004

[9] X Yu Y Sun L Zhang W Rhee and Z Wang ldquoA 1GHzfractional-NPLL clock generatorwith low-OSR998779Σmodulationand FIR-embedded noise filteringrdquo in Proceedings of the IEEEInternational Solid-State Circuits Conference (ISSCC rsquo08) Digestof Technical Papers pp 346ndash347 San Francisco Calif USAFebruary 2008

[10] M H Perrott M D Trott and C G Sodini ldquoA modelingapproach for Σ-Δ fractional-N frequency synthesizers allowingstraightforward noise analysisrdquo IEEE Journal of Solid-StateCircuits vol 37 no 8 pp 1028ndash1038 2002

[11] A Chen and S Yang ldquoReduced complexity CORDIC demod-ulator implementation for D-AMPS and digital IF-sampledreceiverrdquo in Proceedings of the IEEE Global TelecommunicationsConference (GLOBECOM rsquo98) vol 3 pp 1491ndash1496 SydneyAustralia November 1998

[12] Y Xiao Arithmetic study and ASIC implementation ofGMSK8PSK modulation [MS Dissertation] Universityof Electronic Science and Technology Chengdu China 2002

[13] Y Akamine M Kawabe K Hori et al ldquoA loop-bandwidthcalibration system for fractional-N synthesizer and 998779Σ PLLtransmitterrdquo in Proceedings of the IEEE International Solid-StateCircuits Conference (ISSCC rsquo05) vol 1 of Digest of TechnicalPapers pp 314ndash315 San Francisco Calif USA February 2005

[14] X Yu Y Sun W Rhee Z Wang H K Ahn and B-H ParkldquoA 998779Σ fractional-N synthesizer with customized noise shapingfor WCDMAHSDPA applicationsrdquo in Proceedings of the IEEECustom Integrated Circuits Conference (CICC rsquo08) pp 753ndash756San Jose Calif USA September 2008

[15] W Rhee B Zhou and Z Wang ldquoFractional-N frequencysynthesis overview and design perspectivesrdquo in Proceedingsof the 4th IEEE International Symposium on Radio-FrequencyIntegration Technology (RFIT rsquo11) pp 125ndash128 Beijing ChinaDecember 2011

[16] T Sowlati D Rozenblit R Pullela et al ldquoQuad-bandGSMGPRSEDGE polar loop transmitterrdquo IEEE Journal ofSolid-State Circuits vol 39 no 12 pp 2179ndash2189 2004

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CORDIC

Differentiator

Timealignment

Compensationfilter

VCO

DividerPLL

Envelopemodulation

LPFIQGen

I

QIQ

A

A

divideFref

Fref

ΦΦ

PFDandCP

PA

modulatorΔΣ1

2120587middotdΦ

dt

(a)

DACDelaymatch

CORDICIQGen

I

QIQ

A

AΦΦ

Differentiator

Timealignment

VCO

DividerPLL

Envelopemodulation

LPF

divideFref

Fref PFDandCP

PA

modulator

divide

1

2120587middotdΦ

dt

ΔΣ

KVCO

KVCO

(b)

Figure 1 Polar transmitters with ΔΣ PLL based phase modulation (a) digital precompensation and (b) two-point modulation techniques

Chargepump

VCO

MMD

FIR Frequency to phase

Out

In

In

qn

DSM

Noise TF

Out

LPFH(s)

divideN + p0

divideN + pkminus1

PFD0

PFDkminus1(ICP )

Fref

Fref

MCMC

0 MC1 MCkminus1

modulator D1n

D2n Dkminus1

n

1k

+

+

+ TFFIR

G(s) =H(s) middot ICP middot KVCO

N middot s + H(s) middot ICP middot KVCO

DSM and shifted DFFs

DAC and filterG(s)

⋱⋱






(KVCO )

ΔΣ

Σ

zminusn zminusn zminusn

2120587 int(middot)dt

Figure 2 Conceptual diagram and signal model of FIR-embedded ΔΣ PLL with DSM noise suppression

2 FIR-Compensated ΔΣ Phase Modulation forPolar Transmitters

21 FIR-Embedded ΔΣ Fractional-N PLL Figure 2 illus-trates conceptual diagram and small-signal model of FIR-embedded ΔΣ fractional-N PLL For the embedded FIR filterwith a transfer function (TF) shown in (1) the numerator isperformed by 119896-tap shifted D flip-flops (DFFs) with a delaydepth of 119899 and by 119896-path multimodulus dividers (MMDs)and phase-frequency detectors (PFDs) and the denominatoris done by a 119896-branch charge pump (CP) with 119896-phase inputs[9] The multiple MMDs in parallel with sequential controlbits from shifted DFFs perform FIR filtering on the DSMoutput

TFFIR =(1 + 119911

minus119899

+ 119911minus2119899

+ 119911minus3119899

+ sdot sdot sdot + 119911minus(119896minus1)119899

)

119896 (1)

Under PLL reference clock 119865ref the notch frequencyof FIR filter is located at multiples of 119865ref(119899 times 119896)) thus

the DSM output is conducted low-passed filtering While thequantization noise qn is suppressed the signal phase sentto the DSM is also attenuated with linearity degradationTherefore a digital compensation filter with inverse-FIRfeature shown in (2) needs to be added before the DSMto offset the signal attenuation without affecting the noisesuppression Obviously high 119899 times 119896 value complicates theinverse-FIR filter design

TFInverse-FIR =119896

(1 + 119911minus119899 + 119911minus2119899 + 119911minus3119899 + sdot sdot sdot + 119911minus(119896minus1)119899) (2)

The signal path from the DSM input to the voltage-controlled oscillator (VCO) output excluding the FIR fil-tering is functionally equivalent to a DAC with a PLL TF119866(119904) followed by amultiplication factor119865ref and an integratorwith frequency-phase conversion [10] The PLL TF 119866(119904) haslow-passed feature with a limited signal bandwidth whichinversely degrades the phase-path bandwidth Thereforeanother digital compensation filter with inverse-119866(119904) feature



LC VCO

MMD

(DSM)

MCInverse PLL

CORDIC

Timealignment

Envelopemodulation

LPFIQGen

I

QIQ

A

AFref

ΦΦ PFDandCP

divideFref

Differentiator

modulator

Class-EPAFB


VC

fin

65

MH

z

ΔΣ

1

2120587middotdΦ

dt

FB⟨0⟩

FB⟨0⟩




TFInverse-PLL =1

119866 (119904)= 1 +

119873 times 119904








1199092= 119876 119910

2= minus119868 120579

2= 05 (4)


119889119894=

1 119910119894ge 0

minus1 119910119894lt 0

119909119894+1= 119909119894+ 119889119894sdot 2minus2(119894minus2)

sdot 119910119894

119910119894+1= 2 [119910

119894minus 119889119894sdot 119909119894] 120596


120587

120579119894+1= 120579119894+ 119889119894sdot 120596119894

(5)

120601 = 120587 sdot 12057917 119860 =

11990917

164676 (6)



Polarity conversion

Gauss filterI

Q

minus1 10

minus1

1

0BT = 03


(a)


I

Q

Symbolmapping

Symbolrotation


minus1

0

1

minus1

0

1

minus1

0

1


3bit triplets

(b)



260390

1300

0

05

1

15

025

075

125



Time (120583s)



119891in119896 =65 times 10

6

24120587(120601119896minus2


+ 8 sdot 120601119896+1

minus 120601119896+2) (7)



01 05 10 15 20 25 30Frequency (MHz)

100

50

0

minus100

minus50

Gai

n (d

B)

FIR


Compensated TF





25

0

minus100

minus75

Gai

n (d

B)

minus50

minus25

FIR-embedded PLL




GND

VDD

COICP




M1 M2

M3 M4

C

Switch bank

C0 C0S0

C1 C1S1

C4 C4S4

VON

VC

RL

CL

L3

L1 L2

IVCO

VOP



TFInverse-FIR =8


(8)

TFInverse-FIR =2

(1 + (2227) sdot 119911minus2 + (0527) sdot 119911

minus3) (9)








CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB


2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]


INPINN

OUTP

OUTN




119862 which tunes






LC VCO

PFD amp CPMMDCML4


SPI

S4P

FIR







g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











LC VCO

MMD

(DSM)

MCInverse PLL

CORDIC

Timealignment

Envelopemodulation

LPFIQGen

I

QIQ

A

AFref

ΦΦ PFDandCP

divideFref

Differentiator

modulator

Class-EPAFB


VC

fin

65

MH

z

ΔΣ

1

2120587middotdΦ

dt

FB⟨0⟩

FB⟨0⟩




TFInverse-PLL =1

119866 (119904)= 1 +

119873 times 119904








1199092= 119876 119910

2= minus119868 120579

2= 05 (4)


119889119894=

1 119910119894ge 0

minus1 119910119894lt 0

119909119894+1= 119909119894+ 119889119894sdot 2minus2(119894minus2)

sdot 119910119894

119910119894+1= 2 [119910

119894minus 119889119894sdot 119909119894] 120596


120587

120579119894+1= 120579119894+ 119889119894sdot 120596119894

(5)

120601 = 120587 sdot 12057917 119860 =

11990917

164676 (6)



Polarity conversion

Gauss filterI

Q

minus1 10

minus1

1

0BT = 03


(a)


I

Q

Symbolmapping

Symbolrotation


minus1

0

1

minus1

0

1

minus1

0

1


3bit triplets

(b)



260390

1300

0

05

1

15

025

075

125



Time (120583s)



119891in119896 =65 times 10

6

24120587(120601119896minus2


+ 8 sdot 120601119896+1

minus 120601119896+2) (7)



01 05 10 15 20 25 30Frequency (MHz)

100

50

0

minus100

minus50

Gai

n (d

B)

FIR


Compensated TF





25

0

minus100

minus75

Gai

n (d

B)

minus50

minus25

FIR-embedded PLL




GND

VDD

COICP




M1 M2

M3 M4

C

Switch bank

C0 C0S0

C1 C1S1

C4 C4S4

VON

VC

RL

CL

L3

L1 L2

IVCO

VOP



TFInverse-FIR =8


(8)

TFInverse-FIR =2

(1 + (2227) sdot 119911minus2 + (0527) sdot 119911

minus3) (9)








CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB


2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]


INPINN

OUTP

OUTN




119862 which tunes






LC VCO

PFD amp CPMMDCML4


SPI

S4P

FIR







g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











Polarity conversion

Gauss filterI

Q

minus1 10

minus1

1

0BT = 03


(a)


I

Q

Symbolmapping

Symbolrotation


minus1

0

1

minus1

0

1

minus1

0

1


3bit triplets

(b)



260390

1300

0

05

1

15

025

075

125



Time (120583s)



119891in119896 =65 times 10

6

24120587(120601119896minus2


+ 8 sdot 120601119896+1

minus 120601119896+2) (7)



01 05 10 15 20 25 30Frequency (MHz)

100

50

0

minus100

minus50

Gai

n (d

B)

FIR


Compensated TF





25

0

minus100

minus75

Gai

n (d

B)

minus50

minus25

FIR-embedded PLL




GND

VDD

COICP




M1 M2

M3 M4

C

Switch bank

C0 C0S0

C1 C1S1

C4 C4S4

VON

VC

RL

CL

L3

L1 L2

IVCO

VOP



TFInverse-FIR =8


(8)

TFInverse-FIR =2

(1 + (2227) sdot 119911minus2 + (0527) sdot 119911

minus3) (9)








CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB


2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]


INPINN

OUTP

OUTN




119862 which tunes






LC VCO

PFD amp CPMMDCML4


SPI

S4P

FIR







g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










GND

VDD

COICP




M1 M2

M3 M4

C

Switch bank

C0 C0S0

C1 C1S1

C4 C4S4

VON

VC

RL

CL

L3

L1 L2

IVCO

VOP



TFInverse-FIR =8


(8)

TFInverse-FIR =2

(1 + (2227) sdot 119911minus2 + (0527) sdot 119911

minus3) (9)








CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB


2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]


INPINN

OUTP

OUTN




119862 which tunes






LC VCO

PFD amp CPMMDCML4


SPI

S4P

FIR







g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










CML4

CMLto

CMOS

Nonoverlapshaping

Phaseshifter(4~7)

16~31CLK

EN FB


2 46

DelayEN DFF

2DFF

2

MUX MUXCLK

120579012057990

120579180120579270

120579012057990120579180120579270

120579901205791801205792701205790

+MC[5 4]

MC[5 4] MC[3 0]MC[5 0]


INPINN

OUTP

OUTN




119862 which tunes






LC VCO

PFD amp CPMMDCML4


SPI

S4P

FIR







g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










g

Frequency offset

minus60

minus70

minus80

minus90

minus100

minus110

minus120

minus130

minus140

minus150



100 kHz 100MHz

10dBdiv

1

Rawsmoothed





119862with base-


119862with similar



∘



260390

1300

08

09

10

085

095

Time (120583s)

V

25 50 75 100 125 150 175 200


minus15

15


5 Conclusions




Acknowledgment


References




















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation



























RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









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