Report 2 (D3, Digital)

8/12/2019 Report 2 (D3, Digital)

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Laboratory KEEE 1174

Experiment 3: Half-Adder and Full-Adder Circuit (Digital Lab)

TAN JIA HUEI (KET 120044)

Name of demonstrators:

1. Abstract

In this experiment, we constructed various adder circuits including half-adder,

full-adder, high speed adder carry generator circuit and also BCD code adder. We

also looked into the functioning of the circuits. We understood the characteristics

of half-adder and full-adder in the arithmetic unit.

2. Introduction

1. In electronics, an adder or summer is a digital circuit that performs addition of

numbers. In many computers and other kinds of processors, adders are used

not only in the arithmetic logic unit(s), but also in other parts of the processor,

where they are used to calculate addresses, table indices, and similar

operations.

2. Although adders can be constructed for many numerical representations, suchas binary-coded decimal or excess-3, the most common adders operate on

binary numbers. In cases where two's complement or ones' complement is

being used to represent negative numbers, it is trivial to modify an adder into

an adder subtractor. Other signed number representations require a more

complex adder.


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3. The half adder adds two single binary digits A and B. It has two outputs, sum

(S) and carry (C). The carry signal represents an overflow into the next digit of

a multi-digit addition. The value of the sum is 2C + S. The simplest half-adder

design, pictured on the right, incorporates an XOR gate for S and an AND gate

for C. With the addition of an OR gate to combine their carry outputs, two half

adders can be combined to make a full adder.

4. A full adder adds binary numbers and accounts for values carried in as well as

out. A one-bit full adder adds three one-bit numbers, often written as A, B, and

C in; A and B are the operands, and C in is a bit carried in from the next less

significant stage. The full-adder is usually a component in a cascade of adders,

which add 8, 16, 32, etc. binary numbers. The circuit produces a two-bit

output, output carry and sum typically represented by the signals C out and S,

where . The one-bit full adder's truth table is:

Inputs Outputs

A B C in C out S

0 0 0 0 0

1 0 0 0 1

0 1 0 0 1

1 1 0 1 00 0 1 0 1

1 0 1 1 0

0 1 1 1 0

1 1 1 1 1

Table 1: Truth table for the Full-Adder


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5. To reduce the computation time, engineers devised faster ways to add two

binary numbers by using carry-lookahead adders. They work by creating two

signals (P and G) for each bit position, based on whether a carry is propagated

through from a less significant bit position (at least one input is a '1'),

generated in that bit position (both inputs are '1'), or killed in that bit position

(both inputs are '0'). In most cases, P is simply the sum output of a half-adder

and G is the carry output of the same adder. After P and G are generated the

carries for every bit position are created. Some advanced carry-lookahead

architectures are the Manchester carry chain, Brent Kung adder, and the

Kogge Stone adder.

6. A BCD Adder is a digital combinational circuit that is used for the addition of

two numbers in BCD arithmetic's. The primary difference between the binary

and BCD arithmetic lays in the representation of the numbers greater than 9 in

these two systems. A 4-bit BCD code is used to represent the ten numbers 0 to

9. Since the 4-bit Code allows 16 possibilities, therefore the first 10 4-bit

combinations are considered to be valid BCD combinations. The latter six

combinations are invalid and do not occur.


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3. Results:

1. Half-Adder with Basic Logic Gates:

a. The truth table for the circuit (half-adder):

INPUT OUTPUT

SW1 (B) SW0 (A) F1 F2

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Table 2: Truth table for the Half-Adder

b. The sum is F2, while the carry is F1.

c. The truth table for the circuit (full-adder):

INPUT OUTPUT

SW3 (C) SW2 (B) SW1 (A) F3 F5

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1Table 3: Truth table for the Full-Adder

d. The sum is F5, while the carry is F3.


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2. Full-Adder Circuit with IC

a. The truth table for the circuit:

INPUT OUTPUT

Y X F1 (CARRY)

0 0 0 0

0 1 1 0

0 6 6 0

0 9 9 0

0 F F 0

1 3 4 0

1 6 7 0

1 8 9 0

3 6 9 0

4 8 C 0

4 F 3 1

8 7 F 0

9 9 2 1

A B 5 1

C E A 1

F F E 1

Table 4: Truth table for Full-Adder Circuit with IC


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3. High-Speed Adder Carry Generator Circuit


INPUT OUTPUT

B3 B2 B1 B0 A3 A2 A1 A0 C n+x C n+y C n+z

0 0 0 1 0 0 0 1 1 0 0 1 1

0 0 1 0 0 0 1 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1

0 0 1 1 0 0 1 1 1 1 0 1 1

1 0 1 0 1 0 0 0 0 0 0 0 1

1 1 1 0 1 1 1 1 1 1 1 0 1

1 1 1 1 1 1 0 1 1 1 1 0 1

0 1 1 1 0 1 1 0 1 1 1 1 1

1 0 0 1 0 1 0 1 1 0 0 1 1

Table 5: Truth table for High-Speed Adder Carry Generator Circuit

b. The results are identical to the truth table provided in the lab manual.


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4. BCD Code Adder Circuit


INPUT OUTPUT (U5) AST (U9)

X3 X2 X1 X0 Y3 Y2 Y1 Y0 F1 F11 F10 F9 F8 F2 F3 F7 F6 F5 F4

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0

0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 1 1

0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 0 0 0 0

0 0 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 1

0 1 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 1 00 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1

0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0

0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 0 0 1

0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1

0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1

0 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 1 0

1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 1 1 1

1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 0

1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 01 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 1 0 0

1 0 1 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0

Table 6: Truth table for BCD Code Adder Circuit


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4. Questions :

1. What can be constructed with one XOR and one AND gate?

b. Half-adder

2. F.A. is the abbreviation for:

b. Full-adder

3. What is the correct compensation when binary adding is converted to BCD code

adding?

a. Add 6

4. If S = A + B, C = A3B for a half-adder. S could be expressed as:

S = A + B

5. What is the final sum (S) and carry (C) for a F.A. if both inputs A and B are equal

to 1 and the previous carry is 1?

a. C = 1, S = 1

6. Which of the following equations is true for inputs A, B, sum S and carry C?

a. S = A + B, C = A x B

7. Which of the following statements is true for BCD adding?

b. It cant be done using binary adding operation s but has to be compensated


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5. Conclusion :

From the experiment,

1.

we learned and understood the operation of various adder circuits.2. we are able to further explain its operation.

3. we have verified the truth table for different types of adder circuits.

4. we learned that Half-Adder can be only use for numbers with 1- bit whereas

Full-Adder manage to sum or deduct numbers that are more than 1-bit with

carry input.

5. we learnt that BCD Adder are used to sum or deduct Binary-coded Decimals

and 6 need s to b e added when the sum or carry exceeded 9.

6. References :

1. M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall, 1979, ISBN 0-13-21450-3, pp.119-123

2. Ovidiu Ghita. (2003). Digital Electronics [online] Available:

http://elm.eeng.dcu.ie/~digital1/notes/notes2.pdf

3. Arithmetic Operations in Digital Computers, R. K. Richards, 397pp, D. Van Nostrand Co., NY, 1955

4. Harpreet. (2012, August). What is a BCD Adder [online] Available:http://www.trivology.com/articles/527/what-is-a-bcd-adder.html

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