Renesas Electronics Europe GmbH 00000-A © 2010 Renesas Electronics Corporation. All rights reserved. RL78 Clock Generator

Renesas Electronics Europe GmbH

00000-A© 2010 Renesas Electronics Corporation. All rights reserved.

RL78 Clock Generator

© 2010 Renesas Electronics Corporation. All rights reserved.2

PurposeThis course provides an introduction to the RL78 clock generator.

Different oscillator and operation modes will be explained. Finally the new Snooze mode will be explained.

ObjectivesLearn about the functions RL78 clock generator . Understand the different int. and ext. oscillatorsUnderstand the Snooze mode capabilities.

Content23 pages (including this page)

Learning Time = 30 minutes

Introduction


16-Bit CPU core Operates up to 32MHz clock oscillation (@ VDD = 2.7V-5.5V)

Operates up to 4MHz clock oscillation (@ VDD = 1.6V-5.5V)

Minimum instruction cycle time 31.25ns @ 32MHz

Wide operating voltage range VDD = 1.6V-5.5V

High-speed on-chip oscillator (1,2,3,4,6,8,12,16,24,32 MHz) On-chip voltage regulator (2.1V) leads to low current consumption and low

EMI

Internal voltage regulator


Up to four different oscillatorsMain system clock oscillator up to 20MHz Internal selectable on-chip oscillator 1 to 32MHz

– Reduces power consumption

– Best speed / IDD relation

Internal “low speed” on-chip oscillator 15kHzSubsystem clock oscillator (32.768kHz) (if available)

CPU core operation on all clocks possible

(except “15kHz” on-chip osc.)

Clock generator


Example for RL78/G13 64 pin

Oscillator terminals can be used as ports, if no external oscillator is connected.

Clock generator (cont.)

CPU

Watchdog Timer

Peripherals

Int. Oscillator

15 kHz ± 15 %

Sele

ctor

Ext.Oscillator

32.768 kHz

Int. Oscillator24,32 MHz ± 1%

Ext. Oscillator1…20 MHz

Interval TimerRTC


Block Diagram

Clock generator


+/- 1% accuracy over voltage and temperature Note1

Two pre-set frequencies: 24 MHz and 32MHz Note 2

Improved accuracy with correction registerDown to 0.05

Note 1: Target for RL78/G13Note 2: RL78/G13

% Accuracy

1.8 2.7 4.5 5.5

Vcc (V)

4

- 4

Typical MCU

RL78

-40 -20 0 +25 +40 +85Temp (C)

24 or 32 MHz +/- 1 %

- 1

1

3.3

Factory Guaranteed!

Internal oscillators


Clock dividing

Select 24MHz or 32MHz frequency by bit 3 of option-byte(00C2H).after reset. Bit 2 to bit 0 are transferred to HOCODIV then dividing rate of source

frequency is decided. This makes a clock of 32MHz to 1MHz.

Software can change HOCODIV that transferred value of option byte.

Selection of 32MHz or 24MHz

Transfer to HOCODIV after reset.

It is possible to rewrite dividing rate by

software.


“High Speed main” mode

0.1

1.0

10.0

1 2 3 4 5 6VDD[V]

IDD

[mA

]

Internal 32MHz

Internal 16MHz

Internal 8MHz

4.7mA @32MHz

“Low Speed main” mode

0.1

1.0

10.0

1 2 3 4 5 6

VDD[V]

IDD

[mA

]

Internal 8MHz

Internal 1MHz

1.2mA @8MHz

32KHz operation

0.1

1.0

10.0

1 2 3 4 5 6

VDD[V]ID

D[μ

A]

32KHz RUN

32KHz/2 RUN

32KHz HALT + RTC

0.7uA with RTC0.7uA with RTC

Typical power consumption

Power consumption values with code execution from Flash


1 to 20MHz oscillation speed Supports external quartz, resonator or external clock

signalCan be selected by software

After reset the device starts always with the internal high speed osc.

Oscillator terminals can be used as ports, if no external oscillator is connected.

External oscillator


Start-Up behaviour of the oscillators

Item Typ. Max Unit

Startup time of HOCO including reset processing 16.75 25.61 Us

Automatically started by reset

Started by software if necessary

Oscillator startup


Clock generator initialisation Startup behavior in case ext. Oscillator is used

void OscInit(void) // Clock generator initialization{ CMC = 0x51; // Set up the operation mode of the X1/P121, X2/EXCLK/P122,

// XT1/P123, and XT2/P124 pins can be written only once!! OSTS = 0x07; // Select the required oscillator stabilization time CKC = 0x00; // Select the CPU and the peripheral hardware clock. MSTOP = 0; // Enable X1 input clock operation while (OSTC < 0xFF) // Wait until X1 input clock stabilization time has been changed { __no_operation(); } do { // Switch CPU clock to fX1 input clock and MCM0 = 1; // check, if CPU is operating on fX1 input clock } // If not, switch CPU clock again to fX1 input clock and check

again while (MCS != 1);

// HIOSTOP = 1; // Switch off the high-speed on-chip oscillator and// XTSTOP = 1; // the subclock if not needed

PER0 = 0xFF; // Switch on the peripheral clock supply PER1 = 0x01;}


Definition of instruction cycle timeOne instruction clock cycle (TCYCL) is one cycle of the CPU clock

(fCPU) selected by the system clock control register (CKC).

Example:

– fX = 32MHz, CKC = 0x10 => fCPU = 32MHz => TCYCL = 1 / fCPU = 31.25ns

– e.g. MOV r, #Byte : TINST = 1 clock * TCYCL => TINST = 1 * 31.25ns = 31.25ns

Instruction time


Minimum instruction cycle time vs. supply voltage

0

1

2

3

4

5

6

0.1 1 10 100

“Low voltage main” mode

Vd

d [

V]

Frequency [MHz]

“Low Speed main” mode

“High Speed main” mode

Mode select by Flash “Option byte”

Operating range


Main system clock and high-speed on-chip oscillator

Halt mode– Oscillator is operating, CPU core is stopped, peripherals are

active– Halt mode release possible with interrupts or reset

Stop mode– Oscillator is stopped, CPU core is stopped, peripherals are not

active– Stop mode release possible with external interrupts or reset

or internal interrupts by internal low speed osc. Or sub-system-clock operated peripherals.

Snooze mode (internal high-speed oscillator)– CSI00 or UART0 data reception possible – Timer triggered A/D-conversion

Possible chip operation modes


15kHz on-chip oscillator Only the watchdog timer, interval timer and RTC can operate with

the low-speed on-chip oscillator

Subsystem clockOperation mode

– CPU core and peripherals are using subsystem clock

Halt mode– CPU core is stopped, peripherals are using subsystem clock– Halt mode release possible with external interrupts, reset,

peripherals supplied by subsystem clock or watchdog timer

Possible chip operation modes (cont.)


Operation mode transitions

Mode transitions:

HALT Instruction

STOP Instruction

HALT Instruction

Release by• ext. interrupt• interrupt from wake up timer• reset

Release by• ext. interrupt• int. interrupt• reset

RESET

Release by• valid serial reception• AD value match

Release by• reception detection• timed AD trigger

Release by• no valid reception• no AD value match

SNOOZECPU Clock Peripheral

STOPCPU Clock Peripheral

HALTCPU Clock Peripheral

RUNCPU Clock Peripheral

Peripheral; DMA, etc operation is possible

Reduce current consumption below HALT mode

Release by• valid serial reception• AD value match

NEW


Benefits of snooze mode

What is the new „SNOOZE“ mode

MAIN RUN

HALT

STOP

SNOOZE

SUB HALT

SUB RUN

<-

• Keep lowest power- current consumption between STOP & HALT mode

• Receive & check UART & CSI without active CPU• Convert & check AD conversion without active CPU

SNOOZE MODE advantages

SNOOZESet the CPU into STOP mode and…… Receive & check Serial Data… Convert & check conversion resultwithout usage of the CPU

Snooze mode is something in betweenSTOP and the RUN mod


ADC operation during standby state Four comparison criteria: Within/Outside Window, Higher/Lower than Limit Over 60% reduction in power consumption vs. to standard ADC operation

Low Power: Snooze Mode (ADC)


Serial interface operation during standby state Wake up from SNOOZE by valid reception

Low Power: Snooze Mode (serial interface)


In this course, we learned about:Functions RL78 clock generator . Different int. and ext. oscillatorsOperating ModesSnooze mode capabilities.

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Summary

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Renesas Electronics Europe© 2010 Renesas Electronics Corporation. All rights reserved.

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Renesas Electronics Europe GmbH 00000-A © 2010 Renesas Electronics Corporation. All rights reserved. RL78 Clock Generator