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A INITIAL RELEASE M. BANCISORAUG-2016
AUG-2016
AUG-2016
AUG-2016
AUG-2016
AUG-2016
N/A
N/A
N/A
02_043758
1:1 CodeID
Ano_template
HW TYPE : Customer Evaluation ZProduct(s): ad9363 : NA
PACKAGE : N/A-lead N/A N/A-family : Pitch-pitch StyleVendor Style
<User Define><User Define>
91
TBD
<User Define>
R. MACDONALD
N/A
M. BANCISOR
M. JOSE
R. AMARILLE
N/A
G. CELEDONIO
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.
SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
STANDBY - 1 OR OPEN: OSCILLATION
PLACE NEAR XC7Z010 (VCCO_MIO1)
BANK_501
ZYNQ BANK 501
USB PHY
2 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
4.7K
0.1UF
10K
DNI00 DNI
20K
8.06K
39
4.7K 4.7K 4.7K
10K
2.2UF1UF1UF1UF
100UF 0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.47UF
TCA9517DGKR
USB3320C-EZK
XC7Z010-1CLG225C
4.7UF
24.000MEGHZ
R75
R86R85
R76
R77
R82
R78 R79R80 R81
R74
C165 C168C154C140
C158 C162
C164
C163
C161
C167C166
C159 C160
U11
Y1
U15
U4
PS_MIO07_500_USB_RESET_B
1V8
ADM1177_SCL
ADM1177_SDA
VIN
SCL
SDA
PS_MIO29_501_USB0_DIR
PS_MIO31_501_USB0_NXT
PS_MIO34_501_USB0_D2
PS_MIO36_501_USB0_CLK
PS_MIO37_501_USB0_D5
PS_MIO38_501_USB0_D6
PS_MIO39_501_USB0_D7
PS-SRST#
1V8
1V8 1V8
VDD33_USB
1V8
1V8
1V8
VIN
PS_MIO36_501_USB0_CLK
PS_MIO31_501_USB0_NXT
PS_MIO32_501_USB0_D0
PS_MIO38_501_USB0_D6
PS_MIO39_501_USB0_D7
USB_OTG_P
USB_OTG_N
VDD33_USB
PS_MIO07_500_USB_RESET_B
PS_MIO30_501_USB0_STP
PS_MIO29_501_USB0_DIR
VIN
PS_MIO28_501_USB0_D4
PS_MIO30_501_USB0_STP
PS_MIO32_501_USB0_D0
PS_MIO33_501_USB0_D1
PS_MIO35_501_USB0_D3
PS_MIO33_501_USB0_D1
PS_MIO34_501_USB0_D2
PS_MIO35_501_USB0_D3
PS_MIO28_501_USB0_D4
PS_MIO37_501_USB0_D5
1V8
1V8
A13
8
7
1
325
4
B12
C14B14
E14
C10
B13
A15D11B15C12E15C11D15A14
B11
12
26
16
PAD
25
1
231
1315
1918
2122
2927
23
97
56
10
4
8
20
3
241411
2
3
6
C13A12D13
D14
1
4
323028
17
GND
VCCB
SCLBSDAB
ENGND
SDAASCLA
VCCA
GND
GND
GND
GND
PINSPARE
PINSPARE
GND
PINSPARE
PINSPARE
GND
GND_FLAG
VDDI
O
DIR
VDD1
8
STP
VDD1
8
RESETB
REFCLK
XO
RBIAS
IDVBUSVBAT
VDD3
3
DMDP
CPEN
SPK_RSPK_L
REFSEL2
DATA7
N/C
REFSEL1
DATA6DATA5
REFSEL0
DATA4DATA3DATA2DATA1DATA0
NXT
CLKOUT
PINSPARE
GND
GND
GND
VDDSTANDBY
GNDOUTPUT
GND
VCCO
_MIO
1_50
1VC
CO_M
IO1_
501
VCCO
_MIO
1_50
1
PS_SRST_B_501
PS_MIO53_501PS_MIO52_501PS_MIO49_501PS_MIO48_501PS_MIO39_501PS_MIO38_501PS_MIO37_501PS_MIO36_501PS_MIO35_501
PS_MIO34_501PS_MIO33_501PS_MIO32_501PS_MIO31_501PS_MIO30_501PS_MIO29_501PS_MIO28_501
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
BANK_500
ZYNQ BANK 500
QSPI FLASH
S4(MIO5)
CASCADED JTAG
NAND (NA)
0
1
0
1
1
1
0
QSPI
SD CARD
0
S3(MIO4)BOOT MODE
PLACE NEAR XC7Z010 (VCCO_MIO0)
3 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
XC7Z010-1CLG225C
DNI
0.1UF0.1UF
DNI0
0
33.333MEGHZ
10KDNI
0
20K 20K
39
20K
20K
20K20K 20K
240
20K
4.7UF 0.47UF 0.01UF100UF
N25Q256A11E1240
DNI10K
0.1UF
0.1UF
C53
C46
R15
R8
R11
R10
R83 R84
R12
R119
R13
R116R122 R120
R14
R121
C50 C51
Y2
C49
U13
U4
R9
C47
C48
C52
1V8
PS_MIO01_500_QSPI0_SS_B
PS_MIO03_500_QSPI0_IO1
1V81V8
REF_CLK_SG
PS-SRST#
PWR_GD_1.35V
PS_MIO02_500_QSPI0_IO0
PS_MIO04_500_QSPI0_IO2
PS_MIO05_500_QSPI0_IO3
PS_MIO06_500_QSPI0_SCLK1V8 1V8
1V8
UART_RX
UART_TX
1V8
1V8
PS_MIO05_500_QSPI0_IO3
PS_MIO04_500_QSPI0_IO2
PS_MIO03_500_QSPI0_IO1
PS_MIO02_500_QSPI0_IO0
1V8
PS_MIO01_500_QSPI0_SS_B
1V8
PS_MIO06_500_QSPI0_SCLK
A5
E5E4E3E2E1D51
2
3
4
B3 B5B1A3
D3B2 D2
D4
A2 A5 C1 C3 C5 D1
A4C2
B4
C4
D7
A8
C7
D8
C9
A6
B10
D9B5
D10B9C6
A10B6
A7C8A9 D6
B7
GND
VDDSTANDBY
GNDOUTPUT GND
GNDGND
GND
GND
GND
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
RESET/NC
CDQ0
VSS
W#/VPP/DQ2DQ1
S#
VCC
HOLD#/DQ3
GND
GND
VCCO_MIO0_500VCCO_MIO0_500
PS_POR_B_500
PS_MIO9_500PS_MIO8_500PS_MIO7_500
PS_MIO6_500PS_MIO5_500PS_MIO4_500PS_MIO3_500PS_MIO2_500
PS_MIO15_500PS_MIO14_500PS_MIO13_500PS_MIO12_500PS_MIO11_500PS_MIO10_500
PS_MIO1_500PS_MIO0_500
PS_CLK_500
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ON
VTTREFS3STATE
S0
VTT
ON
S5
HI
DDR 3
HI
PLACE NEAR XC7Z010 (VCCO_DDR)
PLACE NEAR DDR3
4 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
240
240
MT41K256M16TW-107 IT:P
0.01UF
10UF
10UF10UF
0
0
80.6
10K 10K
240 1K
4.7UF 4.7UF
4.7UF
4.7UF
0.47UF 0.47UF
0.47UF 0.47UF 0.47UF 0.47UF
0.22UF
0.01UF
0.01UF
0.01UF
0.01UF0.01UF
TPS51206DSQR
0.1UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF0.1UF100UF
100UF
XC7Z010-1CLG225C
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
120
R41
U2C61
C79
C82C83
R43
R44
R142
R221 R222
R165
R40 R42
C86 C87
C55
C101
C88 C89
C56 C57 C58 C59
C81
C102C63
C84
C62
C80U14
C96 C97C95C94C92C91
C60C54
C100
U4
R21
R20
R27
R19
R18
R17
R16
R25
R23
R22
R26
R24
R31
R32
R33R39
R34R28
R36
R35
R38
R37
R30
R29
VTT_0P75
DDR3_RST#
DDR3_ODT
DDR3_RAS#
DDR3_CK_P
DDR3_CS#
DDR3_A1
DDR3_DQS0_P
DDR3_A4
1V35
DDR3_WE#
DDR3_DQS0_PDDR3_A6
DDR3_DM1
DDR3_DQS0_N
DDR3_WE#
DDR3_RAS#
DDR3_A8
DDR3_A14
DDR3_A13
DDR3_RST#
DDR3_A11
DDR3_A9
DDR3_A7
DDR3_A2
DDR3_A5
DDR3_BA1
DDR3_A12
DDR3_A0
DDR3_A3
DDR3_BA2
DDR3_BA0
DDR3_A10
DDR3_CS#
DDR3_CKE
DDR3_CK_N
DDR3_CAS#
DDR3_ODT
DDR3_CK_P
DDR3_DQ5
DDR3_DQ7
DDR3_DQ4
DDR3_DQ6
DDR3_DQ3
DDR3_DQ1
DDR3_DQ2
DDR3_DM0
DDR3_DQ0
DDR3_DQ8
DDR3_DQ10
DDR3_DQS1_P
DDR3_DQ9
DDR3_DQ11
DDR3_DQ14
DDR3_DQS1_N
DDR3_DQ12
DDR3_DQ15
DDR3_DQ13
DDR3_DM0
DDR3_CK_P
DDR3_CK_N
DDR3_CKE
DDR3_CAS#
VTT_0P75
DDR3_BA0
DDR3_DM1
VIN
1V35
1V8
VIN
DDR3_DQ9
DDR3_A5
DDR3_A6
DDR3_CK_N
DDR3_CS#
DDR3_ODT
DDR3_CKE
DDR3_CAS#
DDR3_RAS#
DDR3_WE#
DDR3_BA2
DDR3_BA1
DDR3_BA0
DDR3_A13
DDR3_A12
DDR3_A11
DDR3_A10
DDR3_A9
DDR3_A8
DDR3_A7
DDR3_A3
DDR3_A2
DDR3_A1
DDR3_A0
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQS0_N
DDR3_DQS1_N
DDR3_A9
DDR3_A14
DDR3_A4
1V35
DDR3_A7
DDR3_A8
VTTVREF
DDR3_A10
DDR3_A11
DDR3_A5
DDR3_A6
DDR3_BA1
DDR3_BA2
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ8
DDR3_DQS1_P
VTT_0P75
1V35
1V35
1V35
VTTVREF
VTT_0P75
DDR3_DQ11
DDR3_DQ10
DDR3_A14
DDR3_A4
DDR3_DQ7DDR3_A12
DDR3_A13
DDR3_A3
DDR3_A2
DDR3_A1
DDR3_A0
L4K3
6
8PA
D
9
4
35
7
210
1
D3
A3
B1R2N3N2L3
C1
M1
E1
E4 F1 J2 M3
K1
L2
N1
P6
R4B3
R3H3J3R6
G2C2F2B2H2H1G1F3E3E2D1
C3A4B4
C4A2D4
R5N6
M6
K2M2
J1N4
M5P5P4P3M4
R1
P1
VSS
A8
A14A13
RESET#
VSS
VDD
A6
A11
A9
A7
VDD
VSS
A4
A1A2
A5
VSS
VDD
BA1
A12/BC#
A0
A3
VDD
VSS
VREF
CA
NC
BA2
BA0
VSS
NC
ZQ
A10/AP
WE#
CS#
NC
CKE
VDD
CK#
CAS#
VDD
ODT
NC VSS
CK
RAS#
VSS
NC
VDDQ
DQ5
DQ7
DQ4
VDDQ
VREF
DQ
VSSQ
VSS
VDD
LDQS#
DQ6
VSSQ
VSSQ
DQ3
DQ1
LDQS
DQ2
VDDQ
VDDQ
VSSQ
LDM
DQ0
VSSQ
VSS
VDD
VSSQ
DQ8
UDM
VDDQ
VSSQ
VDDQ
DQ10
UDQS
DQ9
DQ11
VDDQ
VSSQ
DQ14
UDQS#
VSS
VDD
VSSQ
VSS
VDDQ
DQ12
DQ15
DQ13
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
PIN
SP
AR
E
GND
GNDGND
GND
GND
GND
PAD
VDD
S5
GND
S3 VTTREF
VTTSNS
PGND
VTT
VLDO
IN
VDDQSNS
GND
GND
GND
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
VCCO
_DDR
_502
PS_DDR_WE_B_502PS_DDR_VRP_502PS_DDR_VRN_502
PS_DDR_RAS_B_502PS_DDR_ODT_502
PS_DDR_DRST_B_502PS_DDR_DQS_P1_502PS_DDR_DQS_P0_502PS_DDR_DQS_N1_502PS_DDR_DQS_N0_502
PS_DDR_DQ9_502PS_DDR_DQ8_502PS_DDR_DQ7_502PS_DDR_DQ6_502PS_DDR_DQ5_502PS_DDR_DQ4_502PS_DDR_DQ3_502PS_DDR_DQ2_502
PS_DDR_DQ15_502PS_DDR_DQ14_502PS_DDR_DQ13_502PS_DDR_DQ12_502PS_DDR_DQ11_502PS_DDR_DQ10_502
PS_DDR_DQ1_502PS_DDR_DQ0_502
PS_DDR_DM1_502PS_DDR_DM0_502
PS_DDR_CS_B_502PS_DDR_CKP_502PS_DDR_CKN_502PS_DDR_CKE_502
PS_DDR_CAS_B_502PS_DDR_BA2_502PS_DDR_BA1_502PS_DDR_BA0_502
PS_DDR_A9_502PS_DDR_A8_502PS_DDR_A7_502PS_DDR_A6_502PS_DDR_A5_502PS_DDR_A4_502PS_DDR_A3_502PS_DDR_A2_502
PS_DDR_A14_502PS_DDR_A13_502PS_DDR_A12_502PS_DDR_A11_502PS_DDR_A10_502
PS_DDR_A1_502PS_DDR_A0_502
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PLACE NEAR XC7Z010 (VCCO_0)
0.05 PITCH JTAG AND UART CONNECTOR
SHORT TO GND FOR JTAG BOOT
GND/VCC
VCCINT
ZYNQ BANK 0VCCINT
PLACE NEAR XC7Z010 (VCC_AUX)
PLACE NEAR XC7Z010 (VCC_PINT)
PLACE NEAR XC7Z010 (VCC_PLL)
PLACE NEAR XC7Z010 (VCC_PAUX)
ZYNQ
PLACE NEAR XC7Z010 (VCC_INT)
USER LED
5 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
100UF
100UF 100UF
XC7Z010-1CLG225C
XC7Z010-1CLG225C
0.1UF
600OHMS
BSS138LT1G
DNI
FTSH-105-01-L-D
LTST-S220TBKT0.01UF
L0805100OHM
L0805100OHM
47UF
47UF
47UF
4.7UF
4.7UF 4.7UF
4.7UF 4.7UF
0.47UF
0.47UF 0.47UF 0.47UF
0.47UF 0.47UF0.47UF 0.47UF
470
4.7K
4.7K
0
BSS138LT1G
0.47UF470
LTST-S220TBKT
C76C64
U4
U4
C98
L12
Q4
P1P1
DS1
C99E5
E6
C65
C77
C85C174
C67 C73
C66 C78
C178
C93
C69 C74 C75
C68 C90C70 C72
C71
R87
R47
R45
Q1
R46
R48
DS2
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TMSUART_RX1V8
VCCPINT1V8
VCCPLL
VCCPLL
VCCPINT
1V8VCCPINT
1V8
VCCPINT
VTTVREF1V8
1V8
USR_LED
1V8
1V8
PS_MIO05_500_QSPI0_IO3
UART_TX
JTAG_TDO
JTAG_TCK
1V8
1V8
VIN
JTAG_TDO
1V8
JTAG_TDI
1V8
VIN
B8 C5 D2 D12 E5 E9 F10
G3
G5
G13 H6 H1
0 J5 J9 K4 K7 K10
K14 L1 L5 L11
M8 N5 N15 P2 P12 R9
F4 H9 J8 K9 E10
F9 G10
J10
L10
J6 L6 G6
H5 K5 F5
E7C15
A11A1
D5
G4
G9L7
L8
H8G7G8H7
M7
F8
J7
H4J4E8
1 2
3
1
2
10
2
864
1
9
53
7
L9
K8
F6
K6
F7 E6
GND
GND
GND
GND
GND
GND
VCCP
LLVC
CPIN
TVC
CPIN
TVC
CPIN
TVC
CPAU
XVC
CPAU
XVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCA
UXVC
CAUX
VCCA
UXPS
_DDR
_VRE
F0_5
02
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
VREFP_0VREFN_0VP_0VN_0
VCCO
_0VC
CBAT
T_0
VCCA
DC_0
TMS_0
TDO_0
TDI_0TCK_0
RSVD
VCC3
RSVD
VCC2
RSVD
VCC1
RSVD
GND
PROGRAM_B_0INIT_B_0
GND
ADC_
0
DXP_0DONE_0CFGBVS_0
SPAREPIN
SPAREPIN
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
SPARE PIN
PLACE NEAR XC7Z010 (VCCO_34)
PLACE NEAR XC7Z010 (VCCO_35)
SPARE PIN BANK_34
ZYNQ BANK 34,35
BANK_35
6 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
XC7Z010-1CLG225C
XC7Z010-1CLG225C
0.1UF
0.1UF
0.01UF
0.01UF47UF
47UF 4.7UF4.7UF
4.7UF4.7UF
0.47UF0.47UF0.47UF
0.47UF0.47UF0.47UF
0.47UF
0.47UF
U4
U4
C117
C118
C119
C120C104
C103
C108C106
C107C105
C116C114C112
C115C113C111
C110
C109
IO_L20_34_TX_D10
IO_L19_34_TX_D9
IO_L19_34_TX_D8
CTRL_IN2
CTRL_IN3
CTRL_IN0
CTRL_IN1IO_L23_35_SPI_CLK
IO_L23_35_SPI_ENB
IO_L24_35_SPI_DO
IO_L24_35_SPI_DI
IO_L09_34_TX_FRAME
SCL
IO_L08_34_CTRL_OUT0
IO_L08_34_CTRL_OUT1
IO_L01_34_FB_CLK
IO_02_34_AD9361_CLKOUT
IO_02_34_AD9361_RST
IO_L22_34_CTRL_OUT6
IO_L22_34_CTRL_OUT7
IO_L21_34_CTRL_OUT4
IO_L21_34_CTRL_OUT5
IO_L20_34_TX_D11
IO_L18_34_TX_D7
IO_L16_34_TX_D3
IO_L11_34_TXNRX
IO_L11_34_ENABLE
USR_LED
IO_L10_34_EN_AGC
1V8
1V8
1V8
1V8
SDA
IO_L07_34_RX_FRAME
IO_L06_34_RX_D10
IO_L06_34_RX_D11
IO_L02_34_RX_D3
IO_L04_34_RX_D7
IO_L05_34_RX_D8
IO_L01_34_RX_D1
IO_L01_34_RX_D0
IO_L03_34_RX_D5
IO_L02_34_RX_D2
IO_L03_34_RX_D4
IO_L04_34_RX_D6
IO_L05_34_RX_D9
IO_L17_34_TX_D4
IO_L12_MRCC_34_DATA_CLK
IO_L13_34_CTRL_OUT3
IO_L13_34_CTRL_OUT2
IO_L15_34_TX_D0
IO_L16_34_TX_D2
IO_L15_34_TX_D1
IO_L17_34_TX_D5
IO_L18_34_TX_D6
H12
N12
J14M11
R8
K12K13
G11H13G12H14G14K15J15
M14
L13
K11M12
R11P11R13R12P14P13N9M9
R7
M10N8
P9P8R10P10
M13
N10
P7 R14
N7
J12
L12
L14
J13J11
N13M15L15
H15E13F12E12E11 F14
F15G15
F11
F13
R15P15
N14H11
N11
VCCO
_34
VCCO
_34
VCCO
_34
VCCO
_34
VCCO
_34
IO_L9P_T1_DQS_34IO_L9N_T1_DQS_34IO_L8P_T1_34IO_L8N_T1_34IO_L7P_T1_34IO_L7N_T1_34IO_L6P_T0_34IO_L6N_T0_VREF_34IO_L5P_T0_34IO_L5N_T0_34IO_L4P_T0_34IO_L4N_T0_34IO_L3P_T0_DQS_PUDC_B_34IO_L3N_T0_DQS_34IO_L2P_T0_34IO_L2N_T0_34
IO_L24P_T3_34IO_L24N_T3_34IO_L23P_T3_34IO_L23N_T3_34IO_L22P_T3_34IO_L22N_T3_34
IO_L21P_T3_DQS_34IO_L21N_T3_DQS_34
IO_L20P_T3_34IO_L20N_T3_34
IO_L1P_T0_34IO_L1N_T0_34
IO_L19P_T3_34IO_L19N_T3_VREF_34
IO_L18P_T2_34IO_L18N_T2_34IO_L17P_T2_34IO_L17N_T2_34IO_L16P_T2_34IO_L16N_T2_34
IO_L15P_T2_DQS_34IO_L15N_T2_DQS_34
IO_L13P_T2_MRCC_34IO_L13N_T2_MRCC_34IO_L12P_T1_MRCC_34IO_L12N_T1_MRCC_34
IO_L11P_T1_SRCC_34IO_L11N_T1_SRCC_34IO_L10P_T1_34IO_L10N_T1_34
GND
GND
VCCO_35VCCO_35IO_L5P_T0_AD9P_35IO_L5N_T0_AD9N_35
IO_L3P_T0_DQS_AD1P_35IO_L3N_T0_DQS_AD1N_35IO_L2P_T0_AD8P_35
IO_L2N_T0_AD8N_35IO_L1P_T0_AD0P_35IO_L1N_T0_AD0N_35
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
AD9363
E/D HAS INT PULL-UP
RX1A INPUT
RX SMA CONNECTOR
NOT USED
14.3K 1%
NOT USED
TX SMA CONNECTOR
7 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
AD9363ABCZ
14.3K
1000PF
1000PF
1000PF
1
140MEGHZ
330NH330NH
DNI
18PF
18PF
18PF
18PF
18PF
18PF
TCM1-63AX+
TCM1-63AX+
142-0701-871
142-0701-871
0.1UF
1UF
DNI
0
10UF
10UF
1UF
U5
R49
C128
C125
C129
R52
R51
Y3
L8 L9C132
C131
C134
C133
C123
C124
T5
T1
TX1A
RX1A
C122
C127
R50
C130
C121
C126
TX1A_N
1P3_TX1A
IO_L22_34_CTRL_OUT7
IO_L22_34_CTRL_OUT6
IO_L21_34_CTRL_OUT5
IO_L21_34_CTRL_OUT4
IO_L13_34_CTRL_OUT3
IO_L13_34_CTRL_OUT2
TX1A_P
IO_L08_34_CTRL_OUT1
IO_L08_34_CTRL_OUT0
IO_L02_34_RX_D2
VDD_INTERFACE
VDD_GPO
VDDD_DIG
VDDA_TX_LO
IO_L06_34_RX_D10
IO_L05_34_RX_D9
IO_L05_34_RX_D8
IO_L04_34_RX_D7
IO_L04_34_RX_D6
IO_L03_34_RX_D5
IO_L03_34_RX_D4
IO_L02_34_RX_D3
IO_L01_34_RX_D1
IO_L01_34_RX_D0
CTRL_IN0
CTRL_IN1
CTRL_IN2
RX1A_P
TX1A_N
VDDA_RX_TX
REF_CLK_SG
TX_VCO_1P1V_SUPPLY
VDDA_TX_LO
VDDA_RX_LO
VDDA_RX_LO
VDDA_RX_SYNTH
IO_L23_35_SPI_CLK
VDDA_TX_SYNTH
VDDA_BB
RX1A_P
RX1A_N
TX1A_P
VDDA1P1_RX_VCO
IO_L23_35_SPI_ENB
IO_L24_35_SPI_DI
IO_L06_34_RX_D11
RX1A_N
1P3_TX1A
IO_L17_34_TX_D5
IO_L11_34_TXNRX
IO_02_34_AD9361_RST
IO_L09_34_TX_FRAME
VDDA1P1_RX_VCO
TX_VCO_1P1V_SUPPLY
IO_L07_34_RX_FRAME
IO_L24_35_SPI_DO
IO_02_34_AD9361_CLKOUT
IO_L12_MRCC_34_DATA_CLK
IO_L15_34_TX_D0
IO_L15_34_TX_D1
IO_L16_34_TX_D2
IO_L16_34_TX_D3
IO_L17_34_TX_D4
IO_L18_34_TX_D6
IO_L18_34_TX_D7
IO_L19_34_TX_D8
IO_L19_34_TX_D9
IO_L20_34_TX_D10
IO_L20_34_TX_D11
IO_L01_34_FB_CLK
IO_L10_34_EN_AGC
IO_L11_34_ENABLE
CTRL_IN3
1V8
F8
K11
C3B3
G4F4
J6
D1
J1
M10
A8
H11
B7
A2
H8
M12
H7F7D12
M6
M4
L12
L11
L10L9L8L7L3L2K2J2H6H5H3H2G1F3C12
C11
C10C9C8C7C2B12B2B1
F12
K4 B10
K3E3B9 F2D3 J3D2E2A11
G3
H12
B8
H4
B11
A5M5
H9
A10A9
A7
M9
M7M8
C4
K6
L6
J4
G2
G8G7
C1
E1F1
A1
K1L1
H1
M1M2
K5L4
J7J8K7J9K8
K9J11K10J12
E7
D7E8D8E9D9E10D10E11
M3A3
B4B5B6
F10
G6G5
F5F6E6E5E4D4
D5D6C6
J5
L5
E12D11
G9
F9 F11
G12 H1
0K1
2
M11
G11
C5
G10
J10
A4 A6 A12
3
2
1
4
2
36
5 1
4
4
3
2
51
6
GND
GND
NC
GND
GND
GND
GNDGND
GND
NC
GND
GND
GND
GND
E/DGND
VDDOUT
GND
SPAREPIN
SPAREPIN
SPAREPIN
SPAREPIN
GND
GND
GND
GND
XTALN
NC
TX1B_NTX1B_P
TX1A_NTX1A_P
VSSA
TX_MON1
VSSA
NC
RX1A_NRX1A_P
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA SPI_DO
AUXADC
RBIAS
VSSA
VSSA
RX1C_N
VSSD
P1_D0/RX_D0_N
P1_D2/RX_D1_N
P1_D4/RX_D2_N
P1_D6/RX_D3_N
P1_D8/RX_D4_N
SPI_ENB
RESETBVD
DAP3
_BB
VDDA
1P3_
TX_S
YNTH
VSSA
RX1C_P
P1_D1/RX_D0_P
P1_D3/RX_D1_P
P1_D5/RX_D2_P
P1_D7/RX_D3_P
P1_D9/RX_D4_PP1_D10/RX_D5_N
CLK_OUT
SPI_CLKSPI_DI
VDDA
1P3_
RX_S
YNTH
VSSA
RX1B_N
VDD_
INTE
RFAC
E
DATA_CLK_N
VSSD
TX_FRAME_N
P1_D11/RX_D5_P
VSSD
VSSA
VSSA
TXNRX
VSSA
VSSA
RX1B_P
VSSD
DATA_CLK_P
FB_CLK_N
TX_FRAME_P
RX_FRAME_PRX_FRAME_N
ENABLEEN_AGC
CTRL_OUT7
VDDA
1P1_
RX_V
CO
RX_VCO_LDO_OUT
VSSA
VDDS
1P3_
DIG
VSSD
FB_CLK_P
VSSD
P0_D10/TX_D5_N
VSSD
CTRL_OUT4CTRL_OUT5CTRL_OUT6
VSSA
VDDA
1P3_
RX_V
C_LD
O
RX2B_N
P0_D0/TX_D0_N
P0_D2/TX_D1_N
P0_D4/TX_D2_N
P0_D6/TX_D3_N
P0_D8/TX_D4_N
P0_D11/TX_D5_P
CTRL_OUT3CTRL_OUT2CTRL_OUT1
VDDA
1P3_
TX_L
O_B
UFFE
R
VDDA
1P3_
RX_L
O
RX2B_P
VSSD
P0_D1/RX_D0_P
P0_D3/TX_D1_P
P0_D5/TX_D2_P
P0_D7/TX_D3_P
P0_D9/TX_D4_P
CTRL_IN2CTRL_IN3
CTRL_OUT0VD
DA1P
3_RX
_TX
VDDA
1P3_
RX_R
F
RX2C_N
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
CTRL_IN1CTRL_IN0
TEST/ENABLE
AUXDAC2
VSSA
RX2C_P
VSSA
TX_VCO_LDO_OUT
VDDA
1P3_
TX_V
CO_L
DO
VDDA
1P3_
TX_L
O
VDD_
GPO
GPO_0GPO_1GPO_2GPO_3
AUXDAC1
VSSA
VSSA
VSSA
VDDA
1P1_
TX_V
CO
TX2B_PTX2B_N
TX2A_PTX2A_N
VSSA
TX_MON2VS
SA
NC
RX2A_PRX2A_N
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
1V8 RAIL POWERS THE AD9363
DUAL INDUCTORS USED BECAUSE THE
POWER SELECTOR
1V0SELECTOR
PL:
1ST
VCCINT
1V81V35
---
---
PS:
3RD
VCCPINT
-------->USB
---->1V3
POWER + DATA USB POWER ONLY USB
VCCO_DDR
RF (1V3)
VDD_INTERFACE (1V8)---
VCC0_34, VCCO_35
VCCAUX, VCCO_0
--------->
AD9363:
SLEW LIMIT
2A TRACE
USB CONNECTORS
2A TRACE
POWER MANAGEMENT SECTION
CURRENT MONITOR
POWER SEQUENCE:
2ND--------->
VCCPAUX, VCC_PLL
VCCO_MIO0, VCC_MIO1
THIRD START 1.35V PS
1.2 MHZ
SECOND START 1.8V PS
USE POWER USB IF AVAILABLE
INRUSH AND OVERCURRENT PROTECTION
2A CURRENT LIMIT
2A @ 1.35V
2A @ 1.8V
8 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
10UF 10UF
10UF10UF
23.2
K46
.4K
10K
10K
100K4.7K
27.4K
10K
10K
DNI
10K
10K
10K
10K
240
0.47UF
10
180NH
47UF 47UF
100OHM
SI2304BDS-T1-E3
5600
PF
0.047UF
0.047UF
1UF
ADP2114ACPZ
100UF
ADM1177-1ARMZ
1.5UH
3300PF
150P
F
47590-0001
1K 1K
NCP339AFCT2G
47590-0001
0.05
NCP339AFCT2G
10UF
180P
F
0.047UF
100OHM
14.3K
DNI
100OHM10UF10UF
47UF47UF22UF
1.5UH
BSS138LT1G
17.8K
C135 C137
C138C136
R65
R64
R61
R60
R59R54
R53
R68
R69
R67
R70
R72
R71
R66
C156
R56
L5
C149 C150
C145 C148
C144
C139
E2
E3
R73E7Q
3
U10
C157
C155
C7
R55
C147
P2
U6
R58
D1
U8
D2
P3
C153
U9
C141
C143
R63
C151
L2
C152C146
L3
C142
Q2
R62
ADP2114_VIN
FB_1P8V
FB_1P35V
VIN_5V_USB_DATA
FB_1P8V
PG_1P8V
FB_1P35V
PG_1P8V
ADM1177_SDA
COMP_1P8V
ADP2114_VIN
VINVIN_5V_USB
VIN_5V_USB
USB_OTG_P
VIN_5V_USB_DATAVIN_5V_USB_POWER
VIN_5V_USB_POWER
1V8
USB_OTG_N
VIN_5V_USB
ADM1177_SCL
VIN_5V_USB_DATA
PG_1P0V
COMP_1P35V
PWR_GD_1.35VVIN
VIN
VIN
1V35
COMP_1P35V
VIN
ADP2114_VIN
COMP_1P8V
VIN_5V_USB_POWER
1.35V
21
9
3 2
2
1
19PA
D
7
17
4
2926
13
31
34
8
24
2
16
SH3
26
A1
23
2
C1
1
SH1SH2
21
C
B2
1
11
1
1
1218
2021
6
27
22
43
9
C
A
5
B1
5
1 2
3 10
A2
SH2SH1
43
5
A
C1
C2
A2
C2
SH3
B2 B1
5
A1
78
10
1514
303228
25
2
1
3
GND
GND
GNDGNDGNDGNDGND
ENGND
IN OUTIN OUT
ENGND
IN OUTIN OUT
GND GND
GND
GND
GND
GND GNDGNDGNDGND
GNDGND
GND
GND
GATESS
ADR SDASCL
TIMERGND
ON
SENSEVCC
GND
GNDGND
GNDGND
GND
VIN6VIN5VIN4
VIN3VIN2VIN1
VDD
PAD
PGND
4PG
ND3
PGND
2PG
ND1
GND
SS2FB2 V2SET
SW4SW3
COMP2
PGOOD2
SW2SW1
COMP1
PGOOD1
EN2
SS1FB1 V1SETEN1
OPCFG
SYNC_CLKOUTFREQSCFG
GND
GND
GND
GNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
BALL K3
5V
3A @ 1V
BALL J3
BALL F12
POWER MANAGEMENT SECTION
BALL K4
FIRST START 1V PS
BALL E2 & F2
A10, A9, A8, A7, M9, M10
BALL B9 & B10
BALLS E3, D3,
9 9
<DESIGN_VIEW>
: NAProduct(s): ad9363HW TYPE : Customer Evaluation Z
1:1
A02_043758
M. BANCISOR
27.4K 17.8K
10UF 10UF
10UF 10UF
10UF
10UF
10UF
46.4K
1K
10K
10K
0.1UF
1UF
1UF
1UF
1UF
1UF 1UF
1UF
1UF
1UF
1UF
47UF 47UF 47UF
1UH
47UF
47UF
0.47UH
N/A
100OHML0805
7002112N/A
A-00
N/A
N/AN/A
10
0.1UF
N/A
N/A
N/A
N/AN/A
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/AN/A
N/A N/A
N/A
N/A
N/A
N/A
N/AN/A
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/AN/A
N/A
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/AN/A
N/A N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/AN/A
N/A
N/A N/A
N/A
N/A
A-00
A-00A-00
A-00 A-00
A-00
A-00
N/A
N/AN/A
N/A N/A
N/A
N/A
7001953
ADP1754ACPZ-1.3
ADP1754ACPZ-1.3
ADP2164ACPZ
L0805100OHM
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
7001953
0.01UF
0.1UF
7002112
0.1UF
0.1UF
7002112
0.1UF
7002112
0.1UF
7002112
0.1UF
70021120.1UF
7002112
0.1UF
7002112
N/AA-00
7002112N/A
R4
C3 C4
C14 C15
C32
C9
C22
R3
R2 R7
R6
R5
C35
C34
C29
C28
C38 C45
C31
C37
C36
C30
C19 C20 C21C17
C11
C33
C8
C2
R1
L1
C13
U7
U1
L4
U3
E4
E1
C24
C26
C41
C42
C27
C44C43
C12 C23
C39
C40
C1
C10
C18C16
C5 C6
C25
1.0V
VDDA_RX_TX
1P3_TX1A
FB0
1P3_SUPPLY_B
VDDD_DIG
VDD_INTERFACE
VDD_GPO
PWR_GD
VDDA_RX_SYNTH
PG_1P0V
VDDA_BB
1P3_SUPPLY_A
VDDA_RX_LO
VDD_INTERFACE
VCCPINT
VDDA_TX_SYNTH
1V8
PWR_GD
VDDA_TX_LO
VIN
SYNC
12
12
16
1
12
2
1
4 13
10
10
6
14
111615321
7
5
8
14
161532
79
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PAD
9
6
12
131211
1043
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12
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1415
85 76
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GNDGNDGNDGNDGND
GND
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GNDGND
GNDGND
GNDGND
GND
SYNC
PADPGNDGND
SW
PGOOD
RT
FBTRKENVIN
PVIN
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GND
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VOUT
NC
SS
GND
PG
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VIN
PADGNDGNDGND
GND
GNDGND
GND
GNDGND
GNDGND
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
![Intel® AVX-512 Architecture - LLVM...A0 A1 A2 A3 A1 A2 A3 A6 A4 A5 A6 A7 A7 Mask: k[] = 01110011 Zeroed in the ss register form X A0 A1 A2 A0 A1 A2 A3 X X A3 A4 A4 Mask: k[] = 01110011](https://img.pdfslide.us/doc/110x75/5f31b370c034de36036a9e97/intel-avx-512-architecture-llvm-a0-a1-a2-a3-a1-a2-a3-a6-a4-a5-a6-a7-a7-mask.jpg)
