Reiner Hartenstein. Informatik Department, TU ... filedriving ban (Germany) 1973 1979/1980 (depencence on near east oil countries) [email protected]

[email protected]

http://hartenstein.de

Keynote, The 1st Brazilian-German Workshop on Micro and Nano Electronics (BGME’2010), October 6 - 8, 2010, Porto Allegre, RS, Brazil 1

Reiner Hartenstein. Informatik Department, TU Kaiserslautern, Germany

Directions of Programming Research:

Seeking a Needle in the Haystack?

Reiner Hartenstein

IEEE fellow

Keynote, 1st Brazilian-German Workshop on Micro and Nano

Electronics (BGME’2010), Oct 6-8, 2010, Porto Alegre, RS, Brazil

1

Brasil-Alemanha 2010 / 2011: Ano da Ciência, Tecnologia e Inovação,

Karlsruhe Institute of Technology

member,

German-Brazilian Year of Science - Technology and Innovation 2010/2011,

Deutsch-Brasilianisches Jahr der Wissenschaft, Technologie und Innovation 2010/2011

http://hartenstein.de/BGME-10.pdf © 2008, [email protected] http://hartenstein.de 2010, 2010,

Abstract (Preface)

2

But the Energy Consumption of Computing worldwide will become unaffordable.

We need to reinvent Computing.

Reconfigurable Computing (RC) could be a Silver Bullet to solve such Problems

And the Performance Progress is stalled by the Parallelism Wall and the Power Wall

However all this is massively handicapped by Programmer Productivity Problems etc.

We need more Computing Services

© 2008, [email protected] http://hartenstein.de 2010, 2010, 3

The Twin Wall Crisis:

Power & Performance

Worldwide two drastically disruptive Developments:

µP Industry changed Strategy over to „manycore“

(away from faster Clock Speed)

A Variety of Power Consumption Problems

The Programming Wall

The Power Wall

© 2008, [email protected] http://hartenstein.de 2010, 2010,

Outline

• The coming Shortage of Energy

• Why Computing is important

• Energy Consumption of Computing

• The Programmability Crisis

• Rescue by Reconfigurable Computing ?

• The Reconfigurability Paradox

• We need to Reinvent Computing

• Reinventing Programmer Education

• Conclusions

4


No more cheap oil

5

Currently: >80 $

Tendency: growing


Oil crises: weekend

driving ban (Germany)

6

1973 1979/1980

(depencence on near east oil countries)

[email protected]





Beyond Peak Oil

7

J. S. Gabrielli de Azevedo: Petrobras

e o Novo Marco Regulatório;

São Paulo, December 1, 2009


Cheap Oil Era reached its End

Rapidly growing energy prices (IEA: factor of 3) predicted.

50% Reserves are under Water. Off-shore Projects re-calculated.

IEA: “need six more Saudi Arabias for Demand predicted for 2030“

80% of Crude Oil is coming from Decline Fields.

Higher Standards of living: China, India, Brazil, Mexico, newly Industr. Countries.

R.H.: Growing Power Consumption of Computers: 10 more Saudi Arabias!

IEA estimates: Demand will at least double til the Year 2030

China passes the U.S. in Energy use [IEA]

8

© 2008, [email protected] http://hartenstein.de 2010,

Beyond Oil: Literature

9

US: ~3 $

… post petroleum …

… hundreds of books


Beyond oil:

Literature (2)

10


Outline









• Conclusions

11 © 2008, [email protected] http://hartenstein.de 2010, 12

Banking without Computers

[email protected]





Business Information Systems

without Computers

13

Lufthansa Reservation

anno 1960

http://wiki.answers.com/Q/Why_are_computers_important_in_the_world

[Courtesy Ernst

Denert]


Computing is important

Survival and Success of the global Economy

14

We have to convince all Funding Sources


Computers everywhere

15 © 2008, [email protected] http://hartenstein.de 2010, 16

... Ecosystem: just one example

16


... Supercomputers ...

17 © 2008, [email protected] http://hartenstein.de 2010, 2010,

Data Centers ...

18

[email protected]





more to come ...

… more to come and more needed


Innovation-driven computing

[Andy Hopper]

• Simulation and Modelling are important Tools which will help predict Global Warming and its Effects.

20

• Computing will play a Key Part in optimizing use of Resources in the physical World.

• The Amount of Infrastructure making up the Digital World is continuing to grow rapidly and starting to consume significant Energy Resources.

• To help generate Momentum and achieve these Goals, it is important that a coordinated set of challenging international Projects are investigated.

• We are experiencing a Shift to the digital World in our daily Lives as witnessed by the wide scale Adoption of the World Wide Web.

Green IT:

• Smart energy Meters: Housing, Buildings, Facilities

• Carpooling and public Transport by Info Web Sites

• Road Traffic and Transport Logistics Optimization

• Reduce Travelling by Telecommuting.


Some Grand Challenge

Examples for CPS*

21

[Ed. Lee]

• Blackout-free electricity generation and distribution,

• Extreme-yield agriculture,

• Safe, rapid evacuation in response to natural or man-made disasters,

• Perpetual life assistants for busy, senior/disabled people,

• Location-independent access to world-class medicine,

• Near-zero automotive traffic fatalities, minimal injuries, and significantly reduced traffic congestion and delays,

• Reduce testing and integration time and costs of complex CPS systems (e.g. avionics) by 1 to 2 orders of magnitude,

• Energy-aware buildings and cities,

• Physical critical infrastructure that calls for preventive maintenance,

• Self-correcting cyber-physical systems for “one-off” applications,

• Disaster Response: Large-Scale Emergency Evacuation,

• Assistive Devices.

*) Cyber-Physical Systems http://varma.ece.cmu.edu/Summit/


The World Economic Forum’s

"Global Redesign Initiative”

Organizations like UN, UNESCO; GATT, G8, G20 are increasingly inept at fixing what ails the world:

22

• economic growth • climate protection • poverty eradication • conflict avoidance • human security • global vaccine protocol • global risk management • promotion of shared values • intelligent water management • smart energy production/distribution …

“Existing global institutions require extensive rewiring to confront contemporary challenges."

Wikinomics approach for agile world-wide mass collaboration without bureaucracy.

for citizen juries, polling, digital brainstorms, policy

wikis, town hall meetings …

New paradigm to involve world citizens by global IT networks

with graphic user interfaces

Doha,

Qatar,

30-31 May

2010


Growing Number of Computers

Trends [Glesner's List]: • Security • Mobility • Communication • Health • Bio-medical • Support of the Elderly • Quality of Life • Leisure • Environment • Sustainable Development • Energy

23

List by Rene Penning de Fries: •Energy •Water •Food •Environment •Poverty •Terrorism •War •Disease •Education •Democracy •Population (2050: ~10 billion people)

[Courtesy Manfred Glesner]


Outline









• Conclusions

24

[email protected]





Growth of the Internet

The trends are illustrated by :

expanding wireless internet,

growing number of users.

shipping electronic books,

more cloud computing?

and many other services.

25

2007 to 2030 factor x30 predicted

Broadband connections NA, Mex, WE by end’ 2007: 155 millions - predicted for after 2011: 228 millions.

larger e-mails,

services integr’g video and software

increasing popularity of games,

massive use of video on demand,

high-definition video and pay-TV,

services by mobile phone companies.

[G. Fettweis, E. Zimmermann: ICT Energy Consumption - Trends and Challenges; WPMC'08, Lapland, Finland, 8 –11 Sep 2008]


Power Consumption of Computers

[Albert Zomaya 2008]

26

at Dallas

[Randy Katz: IEEE Spectrum, Febr. 2009]

Energy cost may overtake

IT equipment cost in the near future

„Google causes 2% of the worlds

electricity consumption“

(Google denied)

at Quincey

at Boardman

2009

Exascale (1018) supercomputer predicted for ~2020: 120 MW

“Largest supercomputers, including exaflops, should not be thought of as computers. They’re strategic scientific instruments. Their usage patterns and scientific impact are closer to major facilities such as CERN, ITER, or Hubble.” [Andrew Jones, Numerical Algorithms Group, ZDNet]


Electricity Bill: a Key Issue

„The possibility of computer equipment power consumption spiraling out of control could have serious consequences for the overall affordability of computing.”

Patent for water-based data centers

Google data center cost determined by monthly power bill

[L. A. Barrosso, Google, 2009]

27

Google going to sell electricity

• Already 2005, Google’s electricity bill higher than value of its equipment.


How Societies Chose

to Fail or Succeed

Unaffordability of von-Neumann-centric computing could jeopardize all facets of our global economy.

Manycore: failure could jeopardize both, IT industry & most sections of the economy depending on rapid improvement of IT. [Dave Patterson]

Several recent outages of cloud computing services.

Stuxnet worm: only propaganda trick?


without Cyber Infrastructure ?

29

?

copyrighted!

? ?

homo computensis

homo Neanderthalensis?


Outline









• Conclusions

30

[email protected]





The Trouble with Manycore

The growing core counts are racing ahead of programming paradigms and programmer productivity

31

- a challenge to CS education

to major extent also in mass markets

going to FPGA: for programmers a paradigm shift

in supercomputing &

Chipmakers busy designing microprocessors that most programmers can’t program … [David Patterson, IEEE Spectrum, July 2010]

… doing so without any clear notion of how such devices would in general be programmed

They hope, someone will be able to figure out how to do that


The vast majority of HPC or supercomputing applications originally written for single processor with direct access to main memory.

32

Programmability Crisis

But the first petascale supercomputers employ more than 100,000 processor cores each, and distributed memory.

They hope, that dozens of applications are inherently parallel enough to be laboriously decomposed, sliced and diced, for mapping onto HPC

Large applications only modestly scalable. >50% apps don’t scale beyond 8 cores, only 6% can exploit >128 PE cores, a tiny fraction 100,000 or more cores.

we are in an all-dominant


Multicore is not new

•ACRI •Alliant •American Supercomputer •Ametek •Applied Dynamics •Astronautics •BBN •CDC •Convex •Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent

•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland Computer •Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel Machines

•Kendall Square Research •Key Computer Laboratories

Dead (Super)Computer Society [Gordon Bell, keynote, ISCA 2000]

•MasPar •Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer •Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics

the single core sequential mind set was the winner

only 2 or 3 successes

most in 1985-1995

- mainly research

33


Can we get it right this time?

The “parallel programming problem”: has been addressed for at least 25 years.

34

Only a small number of specialized developers can write parallel code.

[T. Mattson, M. Wrinn: Parallel Programming:

Can we PLEASE get it right this time? DAC 2008, Anaheim, CA, June 8-13, 2008],

A massive worldwide effort is required, taking many years, creating masses of jobs We need to reinvent

programmer education

We need to reinvent computing

„The proud era

of von Neumann architecture passes into history.“

„Foundational change will disrupt traditional habits throughout the discipline ....“

[Michael Wrinn, (keynote, SIGCSE2010): Suddenly, All Computing is Parallel:

Seizing Opportunity Amid the Clamor] http://www.sigcse.org/sigcse2010/attendees/keynotes.php


Amid the Clamor

35

How to

bring parallel

computing into

mainstream of

undergraduate

education ?

[Michael Wrinn]

current discussions: despairingly seeking a needle in a haystack.


We need a new Textbook

36

having an impact like Mead & Conway

"The book that changed everything“; Electronic Design News, Feb. 11, 2009

http://www.sigcse.org/sigcse2010/attendees/keynotes.php

[email protected]





Outline









• Conclusions 37 © 2008, [email protected] http://hartenstein.de 2010, 2010,

The Tail wagging the Dog

38

„Central“: it controls

(almost) everything

However,

it needs

accelerators

accelerators CPU

CPU „Central Processing Unit“


Twin paradigm systems

39



(almost) everything

However,

it needs

accelerators

CPU

hardwired

accelerators

reconfigurable

accelerators second paradigm

accelerators

ASIC: 3%

FPGA: 97%

[Dataquest, 2009]

design start ratio


A Clean Terminology, please

program source result

Software instruction streams

Flowware data streams

Configware datapath structures configured


FFT

100

Reed-Solomon Decoding 2400

Viterbi Decoding 400

1000

MAC

DSP and wireless

molecular dynamics simulation

88

BLAST 52

protein identification

40

Smith-Waterman pattern matching

288

Bioinformatics

GRAPE

20 Astrophysics

SPIHT wavelet-based image compression 457

real-time face detection

6000

video-rate stereo vision

900

pattern recognition 730

Image processing, Pattern matching, Multimedia

3000 CT imaging crypto

1000

28500

DES breaking

1

1000

1,000,000

Spe

edup

-Fac

tor

Speed-up

factors

obtained

by Software

to Configware

migration

8723 DNA seq.

100

10

10,000

100,000


Energy saving factors: ~10% of speedup

42

FFT

100



1000

MAC

DSP and wireless


88

BLAST 52


40

Smith-Waterman pattern matching 288

Bioinformatics

GRAPE

20 Astrophysics

crypto 1000

28500 DES breaking

1

1000

1,000,000

Spe

edup

-Fac

tor

Power save

factors

obtained

(FPGAs) SPIHT wavelet-based

image compression 457


6000


900



3000 CT imaging

8723 DNA seq.

100,000

10,000

100

10

[email protected]





FPGA vs.x86 Clock Frequency

43

1995 2000 2005100

1

10GHz

GHz

MHz

Pentium IV

Pentium III

Celeron

Celeron to Pentium IV: x20

growing clock speed

growing power consumption

(migration papers: power save not reported before 2005)

Pentium I (1989) to Pentium IV: x60

1995 – 2005: speed-ups obsolete?

-> not obsolete !!


Hitting 28nm, and beyond

Both de facto FPGA giants (Xilinx and Altera) are hitting 28nm at end of 2010.

44

2009: Intel ships 32nm,

2010: foundries to ship 28nm

Intel will ship 22 nm in 2011,

16 nm in 2013

Also FPGAs benefit from Technology progress.

New Xilinx and Altera products push the power limits also for FPGA use in battery-powered small portables

(IGLOO from Altera, from Xilinx: 28 nm low-power process at TSMC and Samsung Foundry)


[Tarek El-Ghazawi et al.: IEEE COMPUTER, Febr. 2008]

Application . Speed-up factor

Savings Power Cost Size

DNA and Protein sequencing 8723 779 22 253

DES breaking 28514 3439 96 1116

much less equipment

needed

massively saving energy

RC*: Demonstrating the intensive Impact

SGI Altix 4700 with RC 100 RASC compared to Beowulf cluster

Tarek El-Ghazawi

*) RC = Reconfigurable Computing © 2008, [email protected] http://hartenstein.de 2010,

Drastically less Equipment needed

For instance: a hangar

full of racks replaced by a single rack

without air

conditioning

46

or ½ rack


END

SGI® RASC™ Module (Version1) Xilinx Virtex II-6000 FPGA 16MB QDR SRAM Rack-mountable Dual NUMAlink™ 4 ports Seamless direct attach to server's shared memory fabric Datasheet (PDF 145K)

SGI® RASC™ RC100 Blade Dual Virtex 4 LX200 FPGAs 80MB QDR SRAM or 20GB DDR2 SDRAM Blade or rack-mountable form factor Dual NUMAlink™ 4 ports Seamless direct attach to server's shared memory fabric Datasheet (PDF 137K)

Hetero HPC

SGI® RASC™


The silver bullet

Reconfigurable Computing is really the silver bullet for massively saving energy

48

scene „Green Computing“ Reinvent Computing

predicted energy saving

factor of about 3 orders of magnitude

http://www.sgi.com/pdfs/3863.pdf

http://www.sgi.com/pdfs/3920.pdf

[email protected]





Outline









• Conclusions


FPGA: much worse Technology?

Lower Clock Frequency (x3 – x5)

50

huge Wiring Overhead (for routing)

Reconfigurability Overhead: e. g. only about 4 % of Transistors serve the Application

& Routing Congestion …

Speed-up by Orders of Magnitude with an Orders of Magnitude worse Technology?

The Reconfigurability Paradox

© 2008, [email protected] http://hartenstein.de 2010, 51

the tremendous inefficiency of

computers causes immense

electricity consumption

the tremendous inefficiency of

computers causes immense

electricity consumption

51

because

of The von Neumann

Syndrome


All but ALU is overhead: x20 efficiency

52

(data cashe)

x20

inefficiency:

just one

of several

overhead

layers

[R. Hameed et al.: Understanding Sources of Inefficiency in General-Purpose Chips; 37th ISCA, June 19-23, 2010, St. Malo, France]


Massive Overhead Phenomena

proportionate to the number of processors

overproportionate to the number of processors

53

overhead von Neumann

machine

instruction fetch instruction stream

state address computation instruction stream

data address computation instruction stream

data meet PU + other overh. instruction stream

i / o to / from off-chip RAM instruction stream

Inter PU communication instruction stream

message passing overhead instruction stream

transactional memory overh. instruction stream

multithreading overhead etc. instruction stream


Critique of the von Neumann Model

Brad Cox 1990:

Planning the Software

Industrial Revolution

Dijkstra 1968: The Goto considered harmful

R. Hartenstein, G. Koch 1975: The universal Bus considered harmful

Backus 1978: Can programming be liberated from the von Neumann style

Arvind et al., 1983: A critique of Multiprocessing the von Neumann Style L. Savain 2006: Why Software is bad

Critique of von Neumann is not new:

Peter G. Neumann 1985-2003: 216x “Inside Risks“ 18 years inside back cover of Comm_ACM

Peter G. Neumann

54

overhead piles up to code sizes

of astronomic dimensions

“von Neumann

Syndrome”: C.V. Ramamoorthy; UC Berkeley

Nathan’s Law: Software is a gas.

It expands to fill all its containers ...

Nathan Myhrvold

Wirth‘s Law

“software is slowing faster

than hardware is accelerating“

[email protected]





Software is too easy to change: Overhead, Featuritis, and: Bugs

Featuritis & Overhead

Configware is less easy to change: a highly important advantage ?

Robert N. Charette: Why Software Fails; IEEE Spectrum, Sep 2005


56

von Neumann overhead vs.

Reconfigurable Computing

overhead von Neumann

machine datastream machine

instruction fetch instruction stream none*

state address computation instruction stream none*

data address computation instruction stream none*

data meet PU + other overh. instruction stream none*

i / o to / from off-chip RAM instruction stream none*

Inter PU communication instruction stream none*

message passing overhead instruction stream none*

transactional memory overh. instruction stream none*

multithreading overhead etc. instruction stream none*

56


The History of Computing

(1)

57

The 1st electrical computer, ready

prototyped for mass production ?

Guess: which year, which company ?


The History of Computing

(2) Prototype 1884: Herman Hollerith

datastream-based

the first reconfigurable computer

DPU

The first Xilinx FPGA came 100 years later

size: like about 3 refrigerators

1989 used for US population census


Early LUT

60 years later: RAM available – e. g. ferrite core

non-volatile configuration memory

field-programmable:

manually

swapping plug boards

(motivation for von Neumann machine paradigm)


60 years later

60

much larger than 3 refrigerators

just for a few ballistic tables:

the „von Neumann“ paradigm

von Neumann syndrome

[email protected]





Outline









• Conclusions

61 © 2008, [email protected] http://hartenstein.de 2010,

62

term controlled by execution

triggered by paradigm

CPU program counter

(at ALU)

instruction fetch

instruction stream

DPU**

rDPU**

data counter(s) (at memory)

data arrival* data-stream-based

*) “transport-triggered” **) does not have a program counter

- no instruction fetch

Single Paradigm (from the

Mainframe Age) is obsolete


63

term controlled by execution

triggered by paradigm

CPU program counter

(at ALU)

instruction fetch

instruction stream

DPU**

rDPU**

data counter(s) (at memory)

data arrival* data-stream

+ New Machine Model for FPGAs

*) “transport-triggered” **) does not have a program counter

- no instruction fetch

twin paradigm

twin paradigm


Acceleration Mechanisms

parallelism by multi bank memory architecture auxiliary hardware for address calculation address calculation before run time

avoiding multiple accesses to the same data. avoiding memory cycles for address computation optimization by storage scheme transformations optimization by memory architecture transformations

Accelerate tasks by streaming

Can achieve 100x in improved use of memory.

MISD structured computation: streaming computations across a long array before storing results in memory.


Programming Model: Flowware

Adder

Speaker

FMDemod

LPF1

Split

Gather

LPF2 LPF3

HPF1 HPF2 HPF3

Source:

MIT

StreamIT

• Pros for streaming – Streamlined, low-overhead

communication – (More) deterministic behaviour – Good match for many simple media

rich applications

[Pierre Paulin]

We‘ve to find out, which applications types and programming models Students should exercise for the flowware approach

• Cons – control-dominated applications – shunt yard problem


The Machine Model Dichotomy

(1) von Neumann versus data stream machine

66

PE

Program Engineering

*) do not confuse with „dataflow“!

Flowware

Engineering

FE

auto-sequencing Memory

asM

SE

Software

Engineering

CPU

1st

Step:

The Generalization of

Software Engineering

[email protected]





Programming Language Paradigms

(1)

language category Computer Languages Languages f. Anti Machine

both deterministic procedural sequencing: traceable, checkpointable

operation sequence driven by:

read next instruction, goto (instr. addr.),

jump (to instr. addr.), instr. loop, loop nesting

no parallel loops, escapes, instruction stream branching

read next data item, goto (data addr.),

jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching

state register program counter data counter(s)

address computation

massive memory cycle overhead overhead avoided

Instruction fetch memory cycle overhead overhead avoided

parallel memory bank access interleaving only no restrictions

language features control flow + data manipulation

data streams only (no data manipulation)

Flowware Languages Software Languages

imperative language twins


Programming Language Paradigms

(2)

Computer Languages Languages f. Anti Machine

procedural sequencing: traceable, checkpointable

read next instruction, goto (instr. addr.),

jump (to instr. addr.), instr. loop, loop nesting

no parallel loops, escapes, instruction stream branching

read next data item, goto (data addr.),

jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching

program counter data counter(s)

massive memory cycle overhead overhead avoided

memory cycle overhead overhead avoided

interleaving only no restrictions

control flow + data manipulation

data streams only (no data manipulation)

Flowware Languages Software Languages

imperative language twins




69 PE

Program Engineering

Flowware

Engineering

FE


asM

SE

Software

Engineering

CPU

CE

Configware Engineering structures

pipe network

model etc. DPU Data-Path- Unit

Data-Path- Array DPA


Software Engineering —

2nd

Step:




70 PE

Program Engineering

Flowware

Engineering

FE


asM

SE

Software

Engineering

CPU

CE

Configware Engineering structures

pipe network

model etc. DPU Data-Path- Unit

Data-Path- Array DPA

time to time time to space

mapping issue


Software Engineering —

2nd

Step:


A Clean Terminology, please

program source result

Software instruction streams

Flowware data streams

Configware datapath structures configured


CPU-centric Flat World Model

Aristotelian model

This Software-only world model

is obsolete CPU not visible from SE

(CS: introduced in the 40ies)

72

CPU-centric sequential-only

mind set

CPU-centric sequential-only

mind set

1,000,000 100,000 10,000

1000 100 10

but no hardware know-how

but no hardware know-how

[email protected]





Outline









• Conclusions


The Language and Tool Disaster

Software people don‘t speak VHDL

Hardware people don‘t MPI nor OpenMP

Bad quality application development tools

86% designers hate their tools [FCCM’98]

progress stalled by qualification problems in industry and academia

Comprehensibility barrier between procedural and structural mind set

N. Conner et al.: FPGAs for Dummies; Wiley, 2008

74


Dual Paradigm Mind Set: an old Hat

Mapped into a Hardware mind set: action box = Flipflop, decision box = (de)multiplexer

Software mind set: instruction-stream-based: flow chart -> control instructions

(mapping from procedural to structural domain)

C. G. Bell et al: The Description and Use of Register-Transfer Modules (RTM's); IEEE Trans-C21/5, May 1972

W. A. Clark: Macromodular Computer Systems; 1967 SJCC, AFIPS Conf. Proc. 1967:

1972:

FF

token bit

evoke

FF FF

We need


POIIP: Loop turns into Pipeline

76

[1979]

(reconfigurable) DataPath Unit:

rDPU loop body

rDPU

rDPU

rDPU

Pipeline:

rDPU loop body

loop:

complex loop body nested loops

complex rDPU or pipe network inside rDPU

complex pipe network

CPU

Memory


Locality Awareness is

essential for Flowware

How data are moved

Software: by addresses, read from instruction

Flowware: by wire (configured before run time)

time to space mapping

Software

Configware

Flowware

space to time mapping

locality awareness

Programmer instruction for Reconfigurable Computing:


Development with VHDL is expensive

78

FPGAs Achilles’ Heel is their long development time: Low level HDLs (VHDL/Verilog) are still dominant

Unlike software, FPGAs do not offer forward/backward compatibility

[Khaled Benkrid, Un. of Edinburg] FPGAs: low technology maturity; small user base, compared to software”

FPGA ASIC eASIC

Variety of Tool Flows

Survey urgently needed: Manpower required!

Complicated IP Core Scene

BDTI High-Level Synthesis

Tool Certification Program™ Grant Martin, Gary Smith. “High-Level Synthesis: Past, Present, and

Future,” IEEE Design and Test of Computers, July/August 2009.

TSMC creates a 'soft' IP cores collaboration program to improve soft IP readiness for EDA and IP suppliers including Arteris, Atrenta, Cadence, Chips & Media, Imagination Technologies, Intrinsic-ID, MIPS Technologies, Sonics, Synopsys and Vivante.

[email protected]





Productivity vs. Efficiency

79

[courtesy Richard Newton]

„The nroff of EDA“ [R. N.]

how to hide the ugliness from the user [Herman Schmit]

HDLs: zero ease of use !!!


Language-of the Year Phenomenon

[R. Newton]

[courtesy Richard Newton]

80

KARL


HLL programming models


Understanding Complex

Hetero Systems

82

Layers of Abstraction and Automatic Parallelization hide critical sources of, and limits to efficient parallel execution

Efficient Distribution of Tasks being memory limited

Internode Communications reduces Computational Efficiency

We must change how programmers think

essential: awareness of locality,

Focusing on memory mapping issues and transfer modes to detect overhead and bottlenecks

Understanding streams through complex fabrics needed


Understanding Architecture

83

NoC

memory

memory

memory

ASIC

ASIC

ASIC

ASIP

ASIP

ASIP

FPGA

FPGA

FPGA

µP

µP

µP

I/O

I/O

I/O

ANN

ANN

memory,

streams

off-chip

th

e m

em

ory

wa

ll

several transfer modes

reconfigurable accelerators

hardwired accelerators

self-reconfigurable accelerators

many-core


>60 NoC Projects

Jih-Sheng Shen, Pao-Ann Hsiung (editors): Dynamic Reconfigurable Network-on-Chip Designs: Innovations for Computational Processing and Communication; Information Science Reference, Hershey, USA, April 1, 2010

84

Industry faces 'platform collision'

Which platform technology will win ? ASIC, ASSP, FPGA, MCU or IP core?

NoC research: world-wide >60 projects

"It's not clear, all may coexist”

Battles will get further interesting if/when the parallel programming crisis is over

[Brad Howe,

VP IC, Altera]

[email protected]





Variety of Architectures

85

AS Application-Specific DP DataPath DPA DataPath Array EPP Extensible Programmable

Platform FP field-programmable GA Gate Array IC Integrated Curcuit IP Instruction Set Processor PU Processing Unit R reconfigurable

CPU, IP

FPDPA, FPGA

FPASIP

(Tensilica, Fujitsu)

ASIC

EPP (Xilinx)

ASIP, ASPU

U Unit

…. and

many,

many

more

X86, ARM … Temsilica


Parallel Architecture Visualization

86

Pipe Network Model

RTL Visualization

Supporting Locality Awareness

EDA

C++ ? C

IP Cores

other Models? (concurrent)

new mix of skills needed

essential: locality awareness

focus on memory mapping issues and transfer modes to detect

overhead and bottlenecks

understanding streams through complex fabrics


Newer Developments in

Semiconductor Technology

Limits by increasing power density

87

significant problems in performance, power consumption and reliability: great challenges for Reconfigurable Computing.

the golden

CMOS era

is gone

Technology scaling does not deliver significant performance speedup

transistors less reliable: additional sources of errors*

defective at manufacture time

degrade and fail over the expected lifetime

process variations

increasing number of soft errors

December 28, 2009

Fault-Tolerance Techniques needed

(EM, HCD, TDDB)

*) J. M. P. Cardoso, M. Hübner (editors): Reconfigurable Computing, 2011, Springer *) S. Borkar: Designing reliable systems from unreliable components; 2005. © 2008, [email protected] http://hartenstein.de 2010, 2010,

Fault Tolerance

88

CPU

hardwired

accelerators

reconfigurable

accelerators

Fault Tolerance Implementation

accelerators


Neurocomputing

89

The Memristor

hp:

discovered

2008, prod.

announced

for 2013

direct synapse emulation replacing massively inefficient digital simulation

less transistors for logic circuits

resistor w. memory: doping moved by electric field

third paradigm:


Mem(r)istor History

1963: Memistor Corp. founded by Prof. Bernie Widrow, Stanford U.

Foto: Storz 1975

1960: missing device postulated by Prof. Karl Steinbuch

2007: Stan Williams, hp, finds Memristor

[Picture: Leon Chua]

1971: Leon Chua, UCB, specifies Memristor

90

1958: Mark I Perceptron: 512 motor-driven potentiometers

2013 ? agreement Hewlett Packard,

Hynix Semiconductor

Frank Rosenblatt

Lernmatrix: ANN patents in the 50ies

[email protected]





Triple paradigm systems?

91

accelerators CPU

hardwired

accelerators

reconfigurable

accelerators

(self-reconfigurable) neurocomputing

Self-organizing Fault Tolerance


[Olivier Temam: The Rebirth of Neural Networks; 37th ISCA, June 19-23, 2010, Saint-Malo, France]

[Olivier Temam, 2010]

[Olivier Temam,

2010]

What ANNs can do

[picture: Olivier Temam, 2010]

1989: single hidden layer enough


Defects-Tolerant Accelerators ?

93 [Olivier Temam, 2010]

for self-reconfigurable neuro computing


Reconfigurable

Neuro Computing or: x1 + x2 + x3 ≥ 1

and: x1 + x2 + x3 ≥ 3

w. Memristor LUT

VDD

RNC

from Boolean Algebra

Generalization of the LUT

to Steinbuch Algebra

from Reconfigurable Computing to Reconfigurable Neuro

Computing (RNC)

Field-Programmable

Neuron Array (FPNA)

Threshold Logic (Majority Logic)


Outline









• Conclusions

95 © 2008, [email protected] http://hartenstein.de 2010, 2010, 96

Conclusions

Legacy Software creates Masses of Jobs for Decades ….

To avoid future unaffordability of our Cyber Infrastructure we need a Massive Migration Effort

achieves much more than most Climate Protection Proposals

RC is the Silver Bullet

We have to activate the Public and the Media, currently fully ignoring this wordwide vital issue

We must start this Campaign as long as we can afford it

A fascinating Challenge to reach new Horizons of research.

We need a Twin Paradigm Co-Education

[email protected]





http://hartenstein.de/bio.pdf

Obrigado!

[email protected]

http://hartenstein.de/BGME-10.pdf


END


Backup for Discussion


Rewriting needed anyway

• Rewriting of software needed anyway: for the survival ot the µP industry (to cope with the transision to manycore)

100

• Extended scope of Software Rewriting: to save energy by orders of magnitude

• different from „classical“ green computing

stro

ng s

yne

rgy


ANN 101 © 2008, [email protected] http://hartenstein.de 2010,

normal Hype Curve

102



[email protected]





normal Hype Curve

103




Neural Network Hype Curve

104



(Olivier Temam never mentions Karl Steinbuch)



105





no

stopped Funding for 15 Years

106

[Olivier Temam,

2010]

Marvin Minsky,

Seymour Papert:

Perceptrons; 1969.

(world-wide)

SVM: Support vector machines: set of supervised learning methods to analyze data and recognize patterns


no

Marvyn Minski‘s blind alarm

107

20 y

ears

earl

ier

!

W. Hilberg: Karl Steinbuch, ein zu Unrecht vergessener Pionier der Künstlichen Neuronalen Systeme; FREQUENZ 1995, 49#(1-2):28-35.

[Olivier Temam,

2010]

1962: Karl Steinbuch

(was ignored by Marvyn

Minski book)

Steinbuchs Lernmatrix

1960


miscellaneous

108

[email protected]





Complex Programmability Crisis

109

Concurrent vs. FPGA Programming

hetero Programming

Fine Grain vs. Coarse Grain Programming vs.

Survey urgently needed: Manpower required!

Acceleration needs an in-depth Application Study: requires more Programming Effort


Processor inside FPGA vs.

FPGA inside Processor: EPP

110

-> totally changed concept

device more like heterogeneous SoCs: significant benefits for HPC applications:

FPGAs became

software-centric:

-> EDUCATION !!!!-

not hardware centric:

Xilinx: Extensible Processing PlatformTM


Structured ASICs

Structured ASICs like eASIC are based mostly on FPGA-like architecture with special configuration mechanism to program at mask level: not re-programmable (more performance for less cost).

111

configware on ROM


RTL Programming to ASIC / ASSP

Platform-Language of Silicon: attractive for IP providers

112

Tools-Path to ASICs/ASSPs, across FPGAs

RTL is inherently parallel, mapped application are automatically optimally parallelized by CAD tools.

Application-Specific Standard Products

now ESL (Electronic System Level) bridging HDL and ANSI C/C++ (at industrial level )

Battle between FPGAs vs MPSoC:

it is RTL vs Software programming.


Design methods and tools

Tools have impact on designer productivity

113

Synthesis tools focus on:

automatically mapping high level descriptions into efficient hardware implementations

according to performance metrics, such as speed, size, and power consumption.

can support verification of functionality, timing and

testability

covers all the main steps of synthesis and analysis, including:

capturing domain-specific knowledge,

profiling,

design space exploration,

multi-core partitioning,

(H/S)system partitioning,

data representation optimization,

static and dynamic reconfiguration,

optimal custom instruction set generation,

functional simulation,

programming mixed SW/RHsystems,

ensuring effective cross-boundary communication (another challenging issue).


Graphical / Dataflow Languages

114

E. El-Araby et al.: Comparative Analysis of High Level Programming for Reconfigurable Computers: Methodology And Empirical Study; Proc. SPL2007 Symp., Mar del Plata, Argentina, Febr. 2007

We should have a look at DSPlogic

We should have a look at DSPlogic

Evaluation Metrics

[email protected]





New boundary constraints are the limiting factor

115

Legacy scientific applications: predominantly sequential

The entire software ecosystem needs to evolve (including curricula): O/S, Libraries SW development environments, compilers and languages

additional levels of parallelism: chaining, pipelining, systolic, super-systolic, wavefront arrays additional data structures and

storage organization: the new distributed memory discipline

Evolve the Software Ecosystem


Tools for Team Design

28-nm FPGAs deliver the equivalent of a 20- to 30-million gate ASIC.

Tools for team-design are coming up:

• Distributed and parallel development,

• Design flows,

• Tracking and reporting

Top level subproject management and integration, including

• source code version control

• Design / IP re-use

• Time budgeting

• In-context synthesis

116

FPGA design tool operation in a reasonable time impossible


>15000

PISA project

117

FFT

100



1000

MAC

DSP and wireless


88

BLAST 52


40

Smith-Waterman pattern matching

288

Bioinformatics

GRAPE

20 Astrophysics

SPIHT wavelet-based image compression 457


6000


900



3000 CT imaging crypto

1000

28500

DES breaking

1

1000

1,000,000

Spe

edup

-Fac

tor

Speed-up

factors are

not new

by avoiding the

von Neumann

paradigm

8723 DNA seq.

100

10

10,000

100,000


118 Speed-up the mid’ 80ies

PISA project

one DPLA* replacing 256 early Xilinx FPGAs

*) fabricated by E.I.S. project


The transition from machine level to higher level languages led to the biggest productivity gain ever made

It‘s alarming that today‘s megabytes of code are compiled from languages at low abstraction levels (C, C++,Java)

The wrong Direction: by Herd Instinct ?

[Fred Brooks]

119

Java is a religion – not a language [Yale Patt]

Bud Lawson‘s Dilbert Cartoon on the Process Manager

„portable assembler language“


Burroughs B5000/5500: language-friendly stack machine

IBM 260/370 & intel x86 highly complex instruction set

MULTICS (GE, Honeywell): well manageable (impl. in PL/1)

UNIX: complexity problems, compatibility problems

Pascal killed by C, coming as an infection, along with UNIX

unnecessary complexity

inside

Widening the Semantic Gap

[Harold „Bud“ Lawson]

„portable assembler language“

[email protected]





Danger of the Situation

Unnecessary Complexity

1963 2010


Danger of the Situation

Unnecessary Complexity

1963 2010

Parallel Programming Gap


Scientific Revolutions

scientific scenes follow the herd instinct

Thomas Kuhn

1st Newtons Law (inertia): „people do not change direction“

Gordon Bell


>40 years Software Crisis

F. L. Bauer 1968, coined „Software Crisis“ - N. N. 1995: THE STANDISH GROUP REPORT Robert N. Charette 2005: Why Software Fails; IEEE Spectrum, Sep 2005

Anthony Berglas 2008: Why it is Important that Software Projects Fail

Oct 1957

The Economist: Nov 19th 1955

In 1955, Parkinson could not have foreseen the impact of software.

The size of bureaucracy is independent of the amount of real work to be done.

124


Apropos Herd Instinct

125

Some Programming Languages

G. Bell: „People do not change Direction“ (follow Herd Instinct)


Architecture visible

The software programming model:

Which hardware architecture parts are visible

and under the programmer’s direct control ?

126

The RC programming model:

how the programmer can control data transfers between FPGA, onboard memory, the microprocessor and its memory

to the programmer

[email protected]





The Human Brain …

“The human brain needs only a few watts for about 10,000,000,000,000,000 (ten million billion) compute operations per second.

127

Von-Neumann-paradigm-based it would need more than a MegaWatt, the electric power needed for a small town and it would sizzle off in a fraction of a second.” [Alfred Fuchs].


SoC - System-on-Chip

128

System on a Chip development:

Yesterday’s chip is today’s functional block!

New design methodologies needed

3.0 1.0 0.5 0.2

20K gates

Schematics

& simulation

50K gates

Schematics

& Synthesis

500k gates

Simulation,

Emulation,

Synthesis,

Formal equivalence

2.5 million gates New Design Paradigm

Source: ICE



Vertical Disintegration


129

Electronic

Company

Foundry Foundry

1960 200X

IP

Company Semicon-

ductor

company

Fabless

Semicon-

ductor

Fabless

Semicon-

ductor

System

company

System

company

System

company


Participants in the Value Chain

130

Source: Gartner



Twin paradigm systems

131



(almost) everything

However,

it needs

accelerators

CPU

hardwired

accelerators

reconfigurable

accelerators second paradigm

accelerators

ASIC: 3%

FPGA: 97%

[Dataquest, 2009]

design start ratio



132




Documents

Reiner Hartenstein. Informatik Department, TU ... filedriving ban (Germany) 1973 1979/1980 (depencence on near east oil countries) [email protected]