Reconfigurable Computing -Options in Circuit Design

John MorrisChung-Ang University

The University of Auckland

‘Iolanthe’ at 13 knots on Cockburn Sound, Western Australia

=keyi?

Serial Circuits

Space efficient Sloooow

One bit of result produced per cycle Sometimes this isn’t a problem

Highly parallel problems

• Search• Many operations on the same data stream eg search a text database for many keywords in parallel

Text stream

=key0?

=keyn?

Data rate:

x MB/s

Serial processing needs:

8x Mbits/s - Easy!

Effective performance may require comparison with

1000’s of keys

space for key circuits critical!

small, compact bit-serial comparator ideal!

=keyi? =keyi?

Serial Circuits

Bit serial adder

ENTITY serial_add IS PORT( a, b, clk : IN std_logic; sum, cout : OUT std_logic ); END ENTITY serial_add;

ARCHITECTURE df OF serial_add IS

SIGNAL cint : std_logic; BEGIN

PROCESS( clk ) BEGIN

IF clk’EVENT AND clk = ‘1’ THEN

sum <= a XOR b XOR cint; cint <= (a AND b) OR (b AND cint) OR (a AND cint ); END IF;

END PROCESS;

cout <= cint;END ARCHITECTURE df;

2-b

it

reg

iste

r

cout

suma

b

cin

FA

Note:

The synthesizer will insert

the latch on the internal signals!

clock

It will recognize the

IF clk’EVENT … pattern!

Multipliers

‘Long’ multiplication

x x x x

x x x x

x x x x

x x x x

x x x x

x x x x

x x x x x x x

multiplier

multiplicand

partialproducts

product

In binary, the partial products

are trivial–

if multiplier bit = 1, copy the multiplicand

else 0

Use an ‘and’ gate!

Multipliers ‘Long’ multiplication

a3 a2 a1 a0

b3 b2 b1 b0

x x x x

x x x x

x x x x

x x x x

x x x x x x x

In binary, the partial products are trivial–

if multiplier bit = 1, copy the multiplicand

else 0

Use an ‘and’ gate!

b0

b1

b2

b3

a0

b0

a1a2a3

first row of partial products

Multipliers We can add the partial products with FA blocks

b0

b1

a0a1a2a3

FAFAFAFA

FA

0

FAFAFA

p0p1

b2

FAFAFAFA

product bits

Parallel Array Adder

We can build this adder in VHDL with two GENERATE loops

FOR j IN 0 TO n-1 GENERATE -- For each row

FOR j IN 0 TO n-1 GENERATE –- Generate a row

pjk : full_adder PORT MAP;( … )

END GENERATE;

END GENERATE; This part is straight-forward!

SIGNAL pa, pb, cout : ARRAY( 0 TO n-1 ) OF ARRAY( 0 TO n-1 ) OF std_logic;

…but you need to fill in the PORT MAP

using internal signals!

Multipliers We can add the partial products with FA blocks

b0

b1

a0a1a2a3

FAFAFAFA

FA

0

FAFAFA

p0p1

b2

FAFAFAFA

product bits

Optimization 1:

Replace this rowof FAs

Time?

What’s the worst case propagation

delay?

Multipliers We can add the partial products with FA blocks

b0

b1

a0a1a2a3

FAFAFAFA

FA

0

FAFAFA

p0p1

b2

FAFAFAFA

product bits

Try to use a

more efficient adder in each row?

A simpler scheme

uses a ‘carry save’ adder – which

pushes the carry out’s down to the

next row!

Note that an extra adder is needed below the last row to

add the last partial products and the carries from the row above!Carry select adder