Re- I ift coni stability ar

F.L. Luo

Indexing terms: DC voltage con

Abstract: The 're-lif the self-lift convertei positive DC-DC stel high efficiency, higl topology in a sin voltage and current Two capacitors are voltage by twice o f t voltage of the re-lifl the self-lift converter

1 Introduction

DC-to-DC converters h ter hardware and indu: computer peripheral power supplies, servom ment. In recent years th has greatly developed. ' high efficiency, high PO in a simple structure. E [6-101 and SEPIC [ll-I

VI

Fig. 1 Re-lgt converter circu

The voltage lift techn circuit design. It was I

converter design for w created [l , 21. The re-1 step-up circuit has bel Fig. 1. It is derived fro lift converter performs sion and consists of 12 switches S, SI, three i 0 IEE, 1998 IEE Proceedings online no. 195 Paper first received 28th April The author is with the School Block S2, Nanyang Techn Singapore 639798

ZEE Z'roc.-Eiecrr. Puwer Appi., E

erter: design, test, simulation and alysis

rter, High efficiency, Boost converter

converter is derived from 2nd performs a positive-to- up voltage conversion with power density and cheap le structure. The output ' this converter are smooth. applied to lift the output : input voltage. The output :onverter is double that of

fe widely been used in compu- rial applications [l-51 such as )wer supplies, car auxiliary tor drives and medical equip- DC-DC conversion technique le main objective is to reach a er density and cheap topology lr example, the Cuk converter ] are good topologies.

diagram

pe is widely used in electronic ccessfully applied in DC-DC ich the self-lift converter was ; converter as a new DC-DC

developed and is shown in the self-lift converter. The re-

:p-up DC-DC voltage conver- mssive components: two static ductors L, , L7 and L?, four

804

d in revised form 21st November 1997 f Electrical and Electronic Engineering, igical University, Nanyang Avenue,

f45, No. 4, July 1995

capacitors C, CI, C2 and CO, three diodes D, D1 and D,. The static switches S and SI are implemented by p- channel power MOSFET device with the driving circuit controlled by a PWM pulse train. The switching period is T = l / f ( f is the switching frequency) and the conduc- tion duty cycle is k, so that the switch-on period is kT and switch-off period is (1 - k)T. Capacitors C1 and C, lift capacitor C voltage V, by twice the input voltage VI. Inductor L3 performs the function as a ladder hinge to joint the voltages V,, and Va across capacitors C 1

and C2.

- v o + + V u -

C

Fig. 2, Re-liff converter models a Feeding phase, S , S, on; D off b Freewheeling phase, S, Si off; D on c Resting phase (applied to discontinuous mode only), S, Si off; D off

In this paper for any component X, its instantaneous current and voltage values are expressed as ix and vx, or idt) and vdt), its average current and voltage values are expressed as I , and V,, and its peak current and voltage values are expressed as I,, and Vxm. All capac- itors are assumed to be large enough so that the ripple voltages across the capacitors can be considered negli- gible for average value discussion. Since the average voltages across inductors L,, L2 and L, are zero, the voltage across C is equal to V, in the continuous mode. This converter may operate in the continuous or dis- continuous modes. Figs. 2a-c show the converter mod- els. The idealised current and voltage waveforms for the continuous and discontinuous modes of operation are depicted in Figs. 3 and 4.

315

Son $off Son Soff -7 c - ) + - - - - - P

t t a b

Fig. 3 Idealised current and voltage waveform of re-lft converter

b Discontinuous mode

a t

,, A

t

k ; h f p

b t 0

Fig. 4 (1) -Vr + Io) (11) (V, - av, ~ vL3 )/L a Continuous mode@ b Discontinuous mode

Idealised current and voltage waveforms of re-lft converter

According to Fig. 2a, when switches S and SI are on and D is off, voltages vL1 and vL2 are equal to VI. Cur- rents iL1 and iL2 increase linearly with slopes VI/L, and VIlL2, respectively. Current i,, which is equal to (icl + iL3 + in) is an exponential function h(t). Consequently, the input current iit) = iLl(t) + iL2(t) + h(t>. Defining L = LIL2/(L1 + L2), the input current iAt) = VItiL + s(t) during switch on. Usually C1 = C2 and icl = ic2 = 8(t) so that 8(t) = [26'(t) + iL3]. Function s(t) is a very high value at the moment of power on, but it is small in the steady state since voltages vcl and vc2 are nearly equal to v,.

According to Fig. 2b, when switches S and S1 are off and D is on, both inductor voltages vL1 and vL2 are equal to -( V, - 2VI- VL3-,g). Therefore currents iL1 and iL2 decrease linearly with slopes -( V, - 2VI - VL3-,fl)/L, and -( V, - 2 VI - VL3.0g)/L,, respectively. Currents -icl, iL3, -ic2 and io are equal to (iL1 + iL2), and they decrease with slope -( V, - 2 VI - VL3-,g)/L. If the falling current io flowing through diode D does not reach zero before the switch is turned on again, the circuit acts in the continuous mode of operation as shown in Fig. 2b, the corresponding waveforms are shown in Fig. 3. If, however, the diode current io falls to zero before the switch is turned on again, the circuit acts in the discon- tinuous mode of operation, as shown in Fig. Id; the corresponding waveforms are shown in Fig. 4.

The analysis of the re-lift converter is performed under the following assumptions: (i) The components of the converter are ideal (ii) The capacitance of all capacitors is large enough so that the voltage across capacitors is constant and equal to V, or VI. Under this assumption, C and C, can be replaced by the voltage sources V, and Cl by VI, respectively, in the converter models, as shown in Fig. 2 (iii) In Figs. 1-4, 'S on' means switches S and S1 are turned on, and 'S off means switches S and S1 are turned off.

2 operation

Steady-state analysis of continuous mode of

2, I Average current and voltage values The waveforms with enlarged variations are shown in Fig. 3. The equivalent circuits with switching-on and off states are shown in Figs. 2a and b. Assuming capac- itors C1 and C2 are sufficient large, voltages Vc, and Va equal to VI in the steady state. Since the average value of voltage vL3 is zero, it is equal to VI during switch-on so that its value during switch off is

Current iL1 increases during switch-on and decreases during switch-off. The voltages applied across inductor LI are VI and -( Vc - 2 VI - VL3-,,g), so that

Hence kTVI = (1 - k)T(Vc - 2V1 - V~s-~ff) ( 2 )

( 3 ) 2

1 - k vc = - VI

Current iL2 increases on switch-on, and decreases on switch-off. The corresponding voltages applied across L, are (VI + Vc - V,) and -( V, - 2 VI - VL3-off). Thus

kT(Vc +VI - VO) = (1 - k)T(Vo - 2Vl - VLS-~S~) (4)

316 IEE Proc.-Elecir Power Appl , Voi 145, No 4, July 1998

Therefore 1~ vo = - vl j 1:k ( 5 )

Assuming the output pc that is Po = PI or VoIo =

Define the voltage transker gaTn M of continuous mode to be I

(7)

The characteristics of iz! against conduction duty k are shown in Fig. 5. t

i

0 0.2 0.6 0.8 1 .o I I I I I

against conduction duty k for con-

Because capacitor CO erforms as a low-path filter,

L2 = I o ( 8 ) ~

The charge on the capal itor C decreases during switch- on period kT 1

Current flowing througl/l L3 during switch off is

Instantaneous currents 'i,, and in are an exponential function sl(t) during sw tch on. Currents icl and ia are equal to (iL1 + iL2) in he switch-off period (1 - k)T, and the charges on C1 and C2 decrease. The charges increase during the swi ch-on period kT, so that their average currents in the iwitch-on period kT (see Figs. 3 and 4) are

i

(11) During switch-on the source current iI and the switch current is is

so that i I = i s = ZL1 + i L 2 + 2c1 + i L 3 + ic2

11 = I s = k'l, = ~ ( I L I -k I L ~ + Ici + I L ~ + Ic2)

The average current and voltage values are v, = v, = v,, = MVI VD = k v , VD, = vc1 = vc2 = vs = VI v,, = VL2 = v,3 = 0 I,, = Io = IIIM I,, = kMIoi2 = kIl12 I,, = I,, + IL2 = 1112 I, = I, I , = I,, = I,, = 0

2.2 Peak values of currents and voltages From the preceeding analysis and Figs. 3 and 4 the peak values of currents and voltages are

ILl, = kIIl2 + kTVIl2L1 IL2, = Io + kTVII2L2 IL3m = 1112 + kTVIl2L3 II, = Is, = ILl , + IL2, + s(t) = kIII2 + I, + kTVII2L + s(0 ID, = ILl, + IL2m = kIII2 + I, + kTVI12L Iclm = Ic2, = - I D , = - (kIII2 + I, + kTVII2L) VS, = vDm = VDlm = v,

2.3 Variations of currents and voltages Current iL1 increases and is supplied by VI during switch-on. Therefore its peak-to-peak variation is

Thus, the variation ratio of the current IL1 is

(14) A ~ L I / ~ - kVrT - VI - R q=----- ~

I L I kLiII I i L i f - M 2 f L i Current iL2 increases and is supplied by the voltage (VI + V, - V,) = VI during switch-on. Therefore its peak- to-peak variation is

Thus, the variation ratio of current iL2 is

" (16)

Current iL3 increases and is supplied by the voltage VI during switch-on. Therefore its peak-to-peak variation is

c=------- A i ~ 2 / 2 - kV1T - IL2 2 L d o 2 M f L 2

01

IEE Proc -Electr Power Appl , Vdl 145, No 4, July 1998 317

Thus, the variation ratio of current iL3 is

(18) A i L 3 / 2 ~ V I T kR - [=- - -

IL3 L311 M 2 f L 3 The peak-to-peak variation of vc is

Hence, the variation ratio is

The charges on capacitors C1 and C2 increase during switch-on, and decrease during switch-off period by the current IL3 = (ILl + IL2). Therefore their peak-to-peak variations are

and

Thus, the variation ratio of Vcl is

( 2 3 ) AVC1/2 - ( 1 - k ) I I -

- - 01 = ~

VCl 4V1Cif 2.f CiR and the variation ratio of Vc2 is

The charge on the capacitor CO is

Q = covo and

AQ = C o A v o AQ is caused by AiL2 and corresponds to the area of the triangle with height AiL2/2 and width of half Tl2, which is shown in Fig. 3.

The half peak-to-peak variation

(25) a v o - AQ - ~ T ~ v I - ~ - - -

2 CO 8CoL2 Thus, the variation ratio of output voltage Vo is

Assuming that k = 0.5, f = 50Hz, L1 = L2 = 200pH, L3 = l O O p H , C = C1 = C2 = CO = 20pF, R = 100Q2, then

= 5 = E = 0.625, p = 0.0025 and ol = 4 = 0.02, e = 0.00156. All capacitor voltage variations are small although the inductor current variations are large. Spe- cially, the output voltage Vo is almost a real direct volt- age with very small ripple. Because of the resistive load, the output current io(t) is almost a real DC waveforms with very small ripple as well, and Io = V,/R.

2.4 Instantaneous value of currents and voltages The instantaneous current and voltage values are

(27)

(28)

0 for O < t < k T Vo for k T < t 5 T

Vo for 0 < t 5 kT 0 f o r k T < t < T

'us= { V D = {

i I = is

i ~ 1 ( 0 ) + i ~ 2 ( 0 ) + 6 ( t ) + q t for 0 < t L k T for k T < t 5 T

(32 )

i L I ( 0 ) + zt for 0 < t 5 kT

vo- 2 + 1 : k iLl(JCT) - ( L1 -Iv1 (t - k T )

for kT < t 5 T (33)

iL2(0) + gt for 0 < t 5 k T

(t - kT) vo - ( 2 + A ) VI

iL1 =

i L 2 ( k T ) - Lz

for k T < t 5 T (34)

i L 3 ( 0 ) + g t for 0 < t 5 kT

i L 2 =

(t - k T ) vo - ( z+ & ) VI

for k T < t 5 T (35)

+ i ~ 2 ( k T ) - L ( t - k T )

(36)

for 0 < t 5 kT vo ~ (2+ A) V I

for kT < t 5 T

(37) 6(t) for 0 < t 5 kT 0 for k T < t S T zD1

for 0 < t 5 kT for k T < t 5 T i ~ l ( k T ) - v ( t - k T )

(38)

tc1 = ic2

for 0 < t 5 kT Vo ~ (2+ &) V I

= { :::l(kT) - i ~ z ( k T ) + L ( t - k T ) for k T < t 5 T

(39)

iL2(0) + gt - Io for 0 < t 5 kT

(t - k T ) - I o vo ~ (2+ A) V I iLZ(kT) - Lz

for k T < t 5 T (40)

i L l ( 0 ) = kI1/2 - k V I / 2 f L , i ~ i ( k T ) = kI1 /2 + kV1/2 fL1

ice =

where

(41)

IEE Proc -Electr Power Appl., Vol 145, No. 4, July 1998 318

2.5 Boundary beti continuous and

Tli, - (2 + A) VI ( t - k T ) 5 0

I L zL l ( kT)+iL2(kT) - -1

I ( t = T ) (44) 1

Substituting eqns. 41 ai d 42 into eqn. 44, 1

Considering eqn. 7, ~

I

1 Therefore

Considering R = Vo,/Io, the boundary equation is obtained

~

(45)

where (RIJZ) is the rormalised load. Direct voltage transfer gain A4 agai st normalised load (RIJZ) is shown in Fig. 6. Com] ared with the continuous mode boundary of SEPIC [ 1, 121, it can be seen that the

I than that of SEPIC. 1 continuous mode’s arc i a of re-lift converter is greater

32 , R - fL

Fig.6 various values of k

Direct voltage trunsjg gain M agaimt normalrsed loud R/ f l at

2.6 Minimum inductance for continuous mode Eqn. 45 gives the condition to select the minimum inductance for continuous mode

where L,, = LlL21(LI + L,) and usually L3 = L1L21(L, + L2). The variables k and R should choose their possi- ble values to make the item to be maximum. Actually, k = 113 results in (k/M2) = 1/27 = 0.037 which is its maximum value. Usually, a larger inductance is chosen to reduce the inductor current variations, as q and are smaller than 1, i.e. inductor currents are continu-

All capacitances should be sufficiently large to keep the capacitor voltage variations small. Usually, the out- put voltage variation is required smaller than 0.01. Therefore from eqn. 26 the minimum capacitance of CO is

ous.

(47) [(I - k)k]mas

f 2L2 = 6.25 look

CO-min 2 ~ 8 M f 2 L 2 where k /M = [(l - k ) k]/2 has its maximum value of 0.125 when k = 0.5. Other capacitors may have the same capacitance but the corresponding voltage varia- tion may be higher. ii

2.7 Examples to design re-lift converter working in continuous mode Continuous mode is usually selected. There are two examples for reference.

2.7. I Variable output current: Specifications: VI = 20V, Vo = 8OV and I, = 0.2 ~ 2.OA. Solution: The voltage transfer gain M = V,/VI = 4, so that k = (1 - 21M) = 0.5. Source current II = MI,, hence, I,,, = 4 x 0.2 = 0.8A, and I,,,, = 4 x 2 = 8A. The load R,, = 8012 = 40Q, and R,,, = 8010.2 = 400Q which are used for the further calculation. A chopping frequency f = 5OkHz was selected. From eqn. 46, L,, = 25OpH. L = 300pH and L1 = L2 were chosen, hence L1 = L, = 600pH, L3 = L = 3 0 0 p . From eqn. 47, Co.min = 1.04pF. One can select all capacitances C = C1 = CO = 5pF. V,, = Vo = SOY. Therefore the following data are obtained: q = 5 = = 0.08 ~ 0.83, p = 0.005 - 0.005 and ol = o2 = 0.04 - 0.4, E = 0.002.

2.7.2 Variable output voltage: Specification: VI = 20V, V, = 50 - 200V and R = 50Q. Solution: Voltage gain M,, = 50/20 = 2.5, and M,,, = 200120 = 10, so that k = 0.2 - 0.8. The output current 1, = 1 - 4A. Source current 11,, =

Chopping frequency f = 50kHz was selected. From eqn. 46, using k = 113, L,, = 37pH. L = 75pH is chosen so that L1 = 300pH and L2 = 1OOpH and L3 = 75w. From eqn. 47, using k = 0.5, [(l - k)k],,, = 0.25, = 6.25pF. One can select all capacitances C = C, = C2 = CO = 1OpF. V,, = V, = 200V. Consid- ering maximum values for q at k = 0.2; 5 at k = 112; 5 and E at k = 113 and the others at k = 0.8, Therefore

1 2.5 = SA, rImaX = 4 X i o = ~ O A .

319 IEE Proc -Elect? Power A p p l , Vol 145, No 4, July 1998

the following data are obtained q = 0.03 - 053. - 0.625 and 0, = 0.05 - 0.2, E = 0.004 - 0.006.

3

3.1 Circuit explanation All the description in Section 2 for the switch-on state is correct for the discontinuous mode. Discontinuous mode means that the instantaneous current io reduces to zero at t = tl = [k + (1 - k)m]T where kT < tl < T, 0 < m < 1, and where m is the current filling factor. Mathematical manipulation for the value of m obtains

= 0.4 = 0.1 - 0.5, p = 0.004 - 0.016 and 0, =

Analysis of discontinuous mode of operation

A 1 2 i “l m y - %

From this equation one can see that the discontinuous mode is caused by the following factors:

- switching frequency f is too low - duty cycle k is too small - inductance L is too small - load resistance R is too big

To analyse the circuit working procession, the current and voltage waveforms with enlarged variations are shown in Fig. 4. The equivalent circuits with switch-on and off states are shown in Fig. 2. Since inductor cur- rent iL3 = 0 at t = t l , so that

5 (1 - k)m Vl VL3-0 f f = (49)

Inductor current iL1 increases in the switch-on period: t = 0 to kT, and decreases in the switch-off period t = kT to t,, i.e. (1 - k)mT. The corresponding voltages applied are VI and -( Vc - 2 VI - VL3.0ff). Therefore

Hence,

(1 - IC k)m ] V I

Inductor current iL2 increases during switch-on with (VI + Vc - V,), and it decreases during switch-off with -( V, - 2 , - VL~-&) in (1 - k)mT and with -(Vu - Vc) in (1 - k)(l - m)T. Thus,

kT(Vc + VI - Vo)

+ (1 - k ) ( l - m)T(Vo - VC) Hence,

v , = 2 I t ] V I [ (1 - k ) m Considering eqns. 50 and 5 1,

3.2 Output voltage V, against load resistance R The boundary between the continuous and discontinu- ous modes given by eqn. 45 is indicated by the dashed curve in Fig. 7. Substituting eqns. 48-51, we obtain the relation of output voltage against load R.

320

The results of this analysis were experimentally verified with the condition V = 20V, f = SOkHz, L = 20pH, the load resistance R = 20Q - 24kQ. The output voltage calculated by eqn. 52 is indicated by the solid lines in Fig. 7 and the corresponding measured values are indi- cated by the dotted curves. Because all components are real parts rather than ideal ones, the measured data are lower than theoretical calculations.

200

100

> >O

60

30 P

I I I

90 /200 417 2000 20000 I 25b--- ‘ I 20

180 24 000 R,

Fig.7 20 V, f = 50kHz and L = 20pH V , = lOV;f= 50kHa; L = 2OOpH

Measured and calculated characteristics of V, against R at VI =

~ -0- - measured ~ theoretical

4 Experimental results

The experimental results were obtained. The measured waveforms of the pulse-width modulated (PWM) switching signal, inductance voltage vL1 and the output voltage v, are shown in Figs. 8-15 for the condition VI = lOV,f= SOkHz, L1 = L2 = 0.2mH, L3 = O.lmH, C = C1 = C, = CO = IObF and k = 0.1 - 0.95. Two p- channel MOSFET (PMOS) devices IRFP9240 were employed to be the static switches S and SI. The three diodes are fast switching diodes UF5042. The load R was selected form 1OOQ to 24kQ. The PWM switching signal was generated by a digital signal processor plus a 586 personal computer. The DSP + PC work at the machine frequency l5OMHz. The switching pulse was formed with amplitude 5V and rise/fall time 20ns (the switching response riseifall time is longer than this). The DSP card TMS320C30 (floating point) was used for this project. For all oscilloscope traces in Figs. S- 15, (channel I is the PWM switching signal which is only the leading edge but whole waveform) channel 2 is the inductance voltage vL1, channel 3 is the output volt- age v,. From these waveforms it can be seen that the analysis and calculation in Section 2 are verified.

Because all components are real parts rather than ideal ones, there is some energy consumption during the voltage conversion. All measured data with some power loss are recorded in Table 1 .

To keep the output voltage equal to the calculated value, a high load resistance was selected. The corre- sponding power transfer efficiency is listed in the Table. From the experimental results the average effi- ciency can reach as high as 85.2% (0.3 s k 5 0.8) and

IEE Proc -Electr Power Appl , Vol 1’45, Nu 4, July 1998

the highest efficiency is switches and diodes cai essary to choose the CI

higher efficiency.

= 0.6. Since the static energy consumption it is nec-

carefully to realise a

Fig.8 f = 5OkHz; V, = 22V; R = 100Q/; q = 0.71; 5p.s and 20V per div.

Experimental results: Laveforms of V,, and V , at k = 0.1

Fig.9 Experimental results: Caveforms of VLl and V, at k = 0.3 f = 50kHz; V , = 28V; R = 14081 q = 0.81; 5 p and 20V per div.

Fig. 10 f = 50kHz; V, = 40V; R = 3 3 0 8 ; ~ rl = 0.86; 5p.s and 20V pef div.

IEE Proc.-Electr. Power Appl., Vu!. 145, No. 4, July 1998

Experimental results:~ waveforms of V,, and V at k = 0.5

,

Fig. 11 Experimental results: waveforms of VLI and V, at k = 0.6 f = 5OkHz: V , = 50V: R = 4008; q = 0.88; 5ps and 20V per div.

I

Fig. 12 f = 50kHz: V,, = 67V; R = 6608; q = 0.87; 5~ and 2OV pe:)div.

Experimental results: wuveforms of VLI and V at k = 0.7

Fig. 13 f = 50kHz; V, = 100V; R = 1.5k8; q = 0.85; 5p3 and 20V per div.

Experimental results: waveforms of VLl and V, at k = 0.8

321

Fig. 15 f = 5OkHz; V, = 400V; R = 24kQ; 11 = 0.62; 5ps and 20V pzr div

Experimental results: waveforms of VLl and V at k = 0.95

Table 1: Experimental data for f = 50kHz, V, 10 V, L, L, = 200pH, L, = 100pH and all C = 1OpF

v o 10 R Po I / PI (V) (mA) (a) (W) (mA) (W) efficiency k

0.1 22 220 100 4.84 682 6.82 0.71

0.2 25 250

0.3 28 200

0.4 33 165

0.5 40 121

0.6 50 125

0.7 68 102

0.8 100 67

0.9 200 40 0.95 400 6.7

100

140

200

330

400

660 1500

5000 2400

6.25

5.60

5.45

4.85

6.25

6.80

6.67

8.00 6.67

822

69 1

649

564

710

782

184

1080 1070

8.22 0.76

6.91 0.81

6.49 0.84

5.64 0.86

7.10 0.88

7.82 0.87

7.84 0.85

10.8 0.74 10.7 0.62

5 PSpice simulation results

Corresponding to the experimental results, PSpice [ 141 simulation transient conditions are set as print step 1 p; final time 15ms; no-print delay 0; step ceiling 20011s; switching pulse T, = Ins; Tf = Ins; P, = 2 ~

1 9 ~ ; period = 20p.s. Since all components are quasi- ideal parts without power loss and switch pulse rise time T, and fall time Tf are very short (1 ns), the trans-

322

fer efficiency is nearly 100'%. Because the voltage drops of switch S and diodes D and D1 are not zero, some voltages are slightly lower than the calculations. Switching frequency f = SOkHz, period T = 2 0 p . PSpice simulation results for various duty values of k from 0.1 to 0.95 (P, = 2 ~ 19p.s) are shown in Figs. 16- 19. From there more waveforms are presented: I(L1) in the plots corresponds to iLl in text; I(L2) corresponds to iL2; I (D) to io; I(Vr) to iI; and V(4) to v, or Vo; V(L2; 1, 2) to vc or V,; and V(2) to vLI; V(5) to vcl or Vel.

350mA [ ,(14.962m, 291.903m)

300mA

0

14.96 14.97 14.98 14.99 15.00 time, ms

b Fig, 16 a 0 1 (Ll) v I (L3) b 0 V (3, 2) A V (9)

O V ( 8 )

PSpice simulation results k = 0.1

: :: 0 I (L2) A I ( D )

2,0A, ( l r m , 26.763m) (14 .970~ 912.788m)

OA

(14.970~1, -1.8620) -5.OA

U 1 (i 4.960m, 26.753m)

L(14.980m, -8.1 667) S E b >

-9.OA

-38V I I

14.96 14.97 14.98 14.99 15.00 time, ms

h Fig. 17 PSpice simulation results k = 0.5 a OI(L1) A I ( D ) b 0 V (3, 2) A V (9)

0 I (L2) 0 I (VI) 0 V (4) 0 V ( 8) v V (2) v I (L3)

IEE Proc.-Electr. Powev Appl., Vol. 145, No. 4, July 1998

4.0A c (1 d.976m. 1 ,4646)

OA

(14.978m, 53.152)

15.00 I , I , ~ 1 (14.978m, -44-076)

-1 oov 14.96 14.97 I 14.98 14.99

~ time, ms ~b

Fig. 18 PSpice simulation vbults k = 0 8 a 0 I (LI) A I (D) b 0 V(3, 2) A V(9)

0 I (L2) 0 I (VI) O V ( 4 ) O V ( 8) v v (2) 'r7 I (L3)

4'0A I (14.979m, ,(14.979m, 1.2135)

(14.979m, 625.162 (14.960m, 265.103m)

(14.979m, -3

500V

ov

-5OOV 1

a

(1 4 . 9 6 6 ~ ~ 482.628)

I (1 4 980111, -232.869) I 96 14.97 14.98 14.99 1500

time, s l b

Fia. 19 PSuice simulation rlesults k = 0.95 u a E I (Ll) 'A I (D) ~ b O V ( 3 , 2) A V(9)

0 I (L2) 0 I (VI) 0 v (4) 0 v ( 8) v I (L3) v v (2)

6 Stability analysih

Stability analysis is vitlal importance for any converter circuit. According to [he circuit network and control systems theory [15, 161, the transfer functions for switching on and off slates are obtained as

IEE Proc -Electr Power A p p l , F'ol 145, No 4, July 1998

- sCR[(C1 + C,) + S2L3ClC21

{ sC[(C~+e2)+s~L3C~C2][~+sL2+szLzco RI

+se1 cz [R+sLz+s2LzCo RI}

-

+(l+sCo R)[(Ci +Cz)+sZL3Cicz]

(55) where s is the Laplace operator. From eqns. 54 and 55 one can see that the re-lift converter is a third-order control circuit for the switching-on state and a fifth- order control circuit for the switching-off state.

0 a

j0.880,

p,5 .R4 23 0

0 b

Fig. 20 x pole 0 zero a Switch-on b Switch-off

Pole-zero diagrams of voltage transfer functions SV,(s)/SVi(s)

For the switching-on state, the zeros are determined by the equation that the numerator of eqn. 54 is equal to zero, and the poles are determined by the denomina- tor of eqn. 54 being equal to zero. There is a zero at the original point (0, 0). Since the equation to deter- mine the poles is the equation with all positive real

323

coefficients, according to the Gauss theorem, the three poles are: one negative real pole ( p 3 ) and a pair of con- jugate complex poles with negative real part The three poles located in the left half plane (in Fig. 20), so that the re-lift converter is stable. When the load resist- ance R increases and intends towards infinitive, the three poles move. The real pole goes to the original point and eliminates with the zero. The pair of conju- gate complex poles becomes a pair of imaginary poles locating on the imaginary axis. Assuming that all capacitors have same capacitance C, and Ll = L, ( L = L , L21(L1 + L2) or L2 = 2L) and L3 = L, eqn. 54 becomes

and the pair of imaginary poles is

= f j w , . C + C o 1

Pl,2 = +3 L C 0 ~ - -+& poles for switch-on (57)

where con = (LC)-", is the re-lift converter normal angular frequency. For the switch-off state, the zeros are determined by the equation that the numerator of eqn. 55 is equal to zero, and the poles are determined by the equation that the denominator of eqn. 55 is equal to zero. There are three zeros: one (z3) at the ori- gin (0, 0) and two zeros ( z ~ , ~ ) on the imaginary axis, which are

zeros for switch-off (58)

Since the equation to determine the poles is the equa- tion with all positive real coefficients, according to the Gauss theorem, the five poles are one negative real pole (ps) and two pairs of conjugate complex poles with neg- ative real parts e,,, and P ~ , ~ ) . There are five poles located in the left half plane (in Fig. 20), so that the re- lift converter is stable. When the load resistance R increases and intends towards infinitive, the five poles move. The real pole goes to the original point and eliminates with the zero. The two pairs of conjugate complex poles become two pairs of imaginary poles locating on the imaginary axis. Assuming that all capacitors have the same capacitance C, and L, = L2 ( L = L1L2/(L1 + L2) or L2 = 2L) and L3 = L, eqn. 55 becomes

(59)

and the two pairs of imaginary poles are

-3.225 --2f-= -0.775

- -8 f Jm

4 2 S2LC =

poles for switch-off so that p1,2 = +j1.8un and ~ 3 , ~ = f j 0 . 8 8 ~ ~ (60)

For both states, when R tends to infinity all poles locate on the stability boundary. Therefore the circuit works in the critical state. From eqn. 53 the output voltage will be infinitive. This fact is verified by the experiment and computer simulation. When R = a, the output voltage v, tends to a very high value. In the par- ticular circuit, since there is some leakage current across the capacitor CO, the output voltage v, cannot be iizfinite.

7 Discussion

7. 'I Output voltage V, against conducfion duty k Output voltage V, is a positive value and is usually greater than twice the source voltage VI when the con- duction duty cycle k is in the range 0 < k < 1. Although the output voltage V, is greater than 2VI with small k , when k = 0 the switch never turns on and results in V, = 0, not 2VP

If k is close to the value of 1, the ideal output voltage V, should be a very big value. Unfortunately, because of the effect of parasitic elements, the output voltage V, falls rapidly. Finally, k = 1 results in V, = 0, not infinity. In this case the accident of iL1 towards infini- tive will happen. The recommended value range of the conduction duty k is 0 < k 5 0.95. Considering the effect of parasitic elements, the particular output volt- age Vo differs from its ideal value when the conduction duty k is close to 1.

7.2 Switching frequency f The chopping frequency 5OltHz is selected to display the advantages of the re-lift converter. In this case the output voltage ripple is very small, shown in Figs. 8- 15. The switching frequency f was selected from 10 to 200kHz for experimental test. The higher the fre- quency, the smaller the ripples of all voltages and cur- rents. Generally, a higher frequency can be used for any DC-DC converters but the PWM switching pulse should have fast riselfall time and fast responses are required for all semiconductor devices is i.e. fast- switching MOSFETs, transistors and diodes.

7.3 Discontinuous inductance currents iL7 and iL2 Generally, large variations of inductance currents E L I and iL2 are allowed. Referring to eqns. 14 and 16, if L1 = L2, current iL1 becomes discontinuous sooner than current iL2 when k < 0.5, and vice versa, current iL2 becomes discontinuous sooner than current iL1 when k > 0.5. Usually, condition L1 > L2 is considered to keep current iL1 continuous.

8 Conclusion

A re-lift converter, a new DC-DC step-up converter, was developed. This is another design that applies the voltage lift technique in DC-DC converters, and is derived from the self-lift converter. The re-lift converter is a circuit with high efficiency, high power density and

IEE Proc -Elect? Powr Appl, Vol 145 No 4, July 19% 324

cheap topology in a siihple structure. Problems such as design, test, simulatiob and stability analysis of this converter have been discussed in this paper. The exper- imental waveforms and PSpice simulation results veri- fied its characteristics. Since two capacitors are successfully applied to’ lift the output voltage by twice of the input voltage, it$ output voltage is double that of the self-lift converter. The re-lift converter has higher direct voltage output \kith very small ripple. Therefore it can be used in higher voltage conversion applica- tions.

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