R&D Proposal on CCPD with HV/HR-CMOS - CERN Documents...R&D Proposal on CCPD with HV/HR-CMOS INFN Group V ... Following an idea proposed by I. Peric in 2007 [01], we want to investigate

R&D Proposal on CCPD with HV/HR-CMOS INFN Group V Bologna, Genova, Milano

ABSTRACT

We propose to prototype an active CCPD (Capacitive Coupled Pixel Detector) by developing, testing and characterizing an HV/HR-CMOS design and its integration with a pixel detector chip for R/O. Initially the R/O chip will be the ATLAS FE-I4 and will be then moved to the RD53 design, when this will become available.

R&D Proposal on CCPD with HV/HR-‐CMOS Version 1.1 Page 2 of 32

Document Index

1 PROJECT ORGANIZATION & FUNDING REQUEST ............................................................ 3 1.1 Introduction ................................................................................................................................................... 3 1.2 Work Program and Work Packages ........................................................................................................ 4

1.2.1 WP1: HV/HR-CMOS Chip Design and Test .................................................................................................. 4 1.2.2 WP2: CCPD Hybridization .................................................................................................................................... 5 1.2.3 WP3: Module Assembly and Test ....................................................................................................................... 5 1.2.4 WP4: Irradiation & Test beam .............................................................................................................................. 6

1.3 Project Timelines, Milestones and Deliverables ..................................................................................... 7 1.4 Participating Units (Sezioni INFN) ........................................................................................................... 8 1.5 Participants to the Project .......................................................................................................................... 8 1.6 CV of the Scientific Project Coordinator ................................................................................................ 9 1.7 Funding Request ........................................................................................................................................... 9 1.8 Collaboration with Enterprises ............................................................................................................... 11 1.9 External project Funding .......................................................................................................................... 11

2 SCIENTIFIC PROPOSAL .............................................................................................................. 12 2.1 Technical Proposal ..................................................................................................................................... 12 2.1.1 State of the art and objectives of the project ........................................................................................... 13 2.1.2 HV/HR-CMOS Design, Technology and Foundry. ................................................................................... 16 2.1.3 HV/HR-CMOS test ............................................................................................................................................... 18 2.1.4 HV/HR-CMOS Hybridization ........................................................................................................................... 19 2.1.5 Irradiation & Test Beam ...................................................................................................................................... 22

2.2 Significance with respect to INFN core Research ................................................................................ 23 2.3 Participant Units: Expertise, Infrastructures, Roles and Contributions ....................................... 23

2.3.1 Bologna ..................................................................................................................................................................... 23 2.3.2 Genova ....................................................................................................................................................................... 24 2.3.3 Milano ........................................................................................................................................................................ 26

2.4 Involvement of External Organizations ................................................................................................. 28 2.5 Implementation of the Project within Resources ................................................................................. 28 2.6 Risk Assessment .......................................................................................................................................... 29 2.7 Impact of the Research in View of Horizon 2020 ................................................................................ 29

2.7.1 Excellent science .................................................................................................................................................... 30 2.7.2 Industrial leadership .............................................................................................................................................. 30 2.7.3 Better society ........................................................................................................................................................... 30

3 References ............................................................................................................................................ 31


1 PROJECT ORGANIZATION & FUNDING REQUEST Project name: HVR_CCPD

Research area: DETECTORS

Scientific Project Coordinator: Attilio Andreazza

1.1 Introduction

Hybrid semiconductor pixel detectors are a well established technology; large scale detectors have been built and operated in high energy experiments. Pixel detectors have characteristics that make them interesting as well for imaging in biomedical applications and are considered as an important solution for imaging detectors at X-FEL light source. Complex readout functions are possible since sensors and electronics chip are separated and connected through a bump bonding process; however, bump bonding is an expensive process.

In view of the High Luminosity LHC (HL-LHC) project, experiments are studying upgrades of their tracking systems that will require several square meters of pixel detectors. ATLAS for instance is planning 4 or 5 layers plus disks for 8÷12 m2. Large area detectors would also be necessary in imaging detectors at X-FEL where high angular resolution on the direction of the detected light could be achieved placing the detectors at large distance from the interaction point. New technologies that reduce the cost and production time of the sensors and of the hybridization will be critical to develop the new systems in time, with required performance and inside the budgeted costs.

While some experiments are looking at MAPs (Monolithic Active Pixels), the requirement of the hit/trigger rate and the complexity of the digital front-end of the LHC experiments or X-FEL imaging detectors are difficult for a monolithic solution. Following an idea proposed by I. Peric in 2007 [01], we want to investigate a compromise solution, where the front-end chip, where complex functions are implemented, is coupled to a pixel matrix realized in a HV/HR-CMOS (High Voltage / High Resistivity) process. On the HV/HR-CMOS we plan to integrate just a preamplifier, a discriminator and limited logic for each pixel cell. The coupling between the readout chip and the HV/HR-CMOS is done in AC: signal from the discriminator output of each pixel is transferred through capacitors made using facing pads separated by a thin dielectric material (glue). This solution (termed Capacitive Coupled Pixel Detector, CCPD) is expected to be less expensive than the hybrid pixel since the expensive bump bonding process can be avoided. Also, the HV/HR-CMOS is an industrial process and not a custom sensor design.

In this project we want to design an HV/HR-CMOS chip suitable for the ATLAS/CMS requirements at HL-LHC: radiation dose, collection time, dimensions. We also want to study the hybridization process suitable for the AC coupling of the signals, its qualification in term of radiation, temperature, and electrical and mechanical stability. We also want to extend the hybridization from single chip to wafer level processing.

Part 1 of this document describes the organization of the project, part 2 provides a detailed scientific proposal.


1.2 Work Program and Work Packages

The HVR_CCPD project is organized in 4 Work Packages (WP). The activities covered by each WP are summarized in the Table 1.

A detailed description of each Work Package activity is then detailed in the following subsections.

Name Sez. Coord.

WP1 HV/HR-CMOS Chip Design & Test MI

WP2 CCPD hybridization GE

WP3 Module assembly & Test GE

WP4 Irradiation & Test beam MI

Table 1: Work Packages of the HVR_CCPD project.

1.2.1 WP1: HV/HR-CMOS Chip Design and Test

WP1 Leading Institute: Milano

This package contains the development of the detector design, resulting in three successive devices and their testing.

The HV/HR-CMOS devices need a technology that is high voltage and with high/moderate resistivity to deplete the substrate. In collaboration with STMicroelectronics (STM) of Agrate Brianza we plan to use the BCD8s technology (160 nm, Bipolar/CMOS/D-MOS) [02][03] and modify the substrate to a higher value of resistivity. The TCAD simulation of the technology changes will be done by STM, while INFN Milano will take care of the design. INFN Genova will help with the chip simulation. The Bologna group will also participate.

All devices will have a pitch compatible with FE-I4 [04][05][06] (50µm × 250 µm), so that they can be coupled with it for more refined tests:

1. A first test pixel matrix (TPM1), whose pixel cells will contain a charge preamplifier with an output of ~1 V for the signal delivered by a minimum ionizing particle. The output of each amplifier will be multiplexed to a sense pad for study of the pulse shape and characterization of the sensor. This device will have a size of approximately 5×5 mm2 and the design will also include test structure for characterization of the technology.

2. A second test pixel matrix (TPM2), with the addition of digital functionalities, like timewalk compensation and a tuneable comparator after the amplifier.

3. A final matrix (FPM) of approximately 1 cm2 size, designed to be also compatible with the FE ASIC developed by the RD53/CHIPIX65 project that should become available during the 3rd year of the project.

The plan consists of a submission per year, with the first two matrices on multi-project wafers. The higher cost of the initial submission is due to the procurement of a minimum lot of high-resistivity wafers for the substrate. The wafers can then be split between the two submissions. The FPM may be too large to fit in a multi-project wafer and therefore a higher submission cost is expected.

The work package includes also the realization of two test setups. A probing setup will be used to test the functionality of sensors devoted to irradiation test or assembly with FE-I4 readout chips. A custom test board for detailed characterization of the sensor properties, aiming to:


• Study of the pulse shape, height and noise, with an external injection; • Calibrate the absolute charge collection using radioactive source; • Measure the volume of charge collection by laser injection; • Extract the production yield.

1.2.2 WP2: CCPD Hybridization

WP2 Leading Institute: Genova

This package develops the hybridization technology for CCPD (Capacitively Coupled Pixel Detector) and will produce the needed stacks of R/O chip and HV/HR-CMOS detectors, as required to qualify the devices developed in package 1.

The plan for the 3-year R&D is the following:

• 1st year. Test the process using as dielectric an SU8 epoxy material and single chip assembly. We consider to do initial tests on single chip size assemblies using glasses with deposited metal patterns to align and measure capacitances. At the same time we want to produce dummy wafers with several test structures. Dummy wafers will be initially limited at 6” or 8” sizes. Dimension will be decided accordingly to the available machines for the process: spinners, photolithography, dicing saws, etc. Such dummy wafers have just one metal layer. For the first year we will use just one or few wafers that we will dice and process as single chip. After test of single dummy chip we will test hybridization with FE-I4 and TPM1 chips.

• 2nd year. Test the process of deposition on whole dummy wafers. This will be done in collaboration with industry. We plan to use 8” wafers (size of the FE-I4 and other 130/250 nm technologies). We will also study the integration of the DC lines (at least power/ground) with available wafer processes. After successful test on dummy wafer we will try a few full wafers of FE-I4. More assemblies will be done when TPM2 chips will come.

• 3rd year. We will look for industrialization of the full process on 12” wafers (as expected from the new generation of front-end chips under development by the RD53 collaboration, with participation of the CHIPIX65 INFN project). We will provide recommendations for the whole technology process.

Part of the package is the mechanical and electrical characterization of the process. This will be done by thermal and radiation tests. We will also consider wafer thinning to reduce material budget.

1.2.3 WP3: Module Assembly and Test

WP3 Leading Institute: Genova

This package will assemble HV/HR-CMOS detectors and FE-I4 into CCPDs, using the hybridization process developed in WP2. Modules will be assembled on PCB and equipped with flex-hybrids circuits. For the assembly we will use modified tooling that were used for module assembly of ATLAS IBL [05]. The test of the assemblies will be done using USBPix pixel R/O system; which was designed for FE-I4 with standard sensors and will be adapted to the CCPD.

The test of the assemblies in the lab will be done with gamma and beta sources and with focused IR laser. Aims of such tests are collection efficiency before and after irradiation and time response. In particular the laser can provide special information of the collection efficiency inside the pixel cell and time response. With the laser we also plan to perform edge-TCT (Transient Current Technique) to measure the charge collection depth (depletion depth).


Irradiated CCPD devices will be tested at different temperatures: we can use environmental cambers or setup with cool plates. Part of the responsibility in this package is to prepare assemblies for irradiation and test beams.

For producing assemblies we will have to procure/design PCB and flex-hybrid circuits, this is also responsibility within the package.

1.2.4 WP4: Irradiation & Test beam

WP4 Leading Institute: Milano

This work package concerns the organization of irradiation and test beam of the devices developed in the project. It includes also the analysis of test beam data.

The devices need to be irradiated at least to a dose of 3 MGy and a NIEL of 1015 1 MeV n/cm2, corresponding to intermediate silicon layers at the HL-LHC and possibly to a factor 10 more, corresponding to the innermost layer positions.

The preferred irradiation source consists of high-energy protons, for which dose and NIEL are in a similar proportionality, but to achieve high doses also gamma, neutron and low-energy charged hadrons will be considered.

Devices to be irradiated include individual dies of TPM1/2 and FPM. For the initial year also glass assemblies will be irradiated to study the properties of the material used for the bonding. Since FE-I4 has been already characterized as rad-hard, there is in principle no reason to irradiate assemblies and flipping of irradiated sensors on non-irradiated FE-I4 is preferred for characterization of irradiated sensors. In the second year assemblies with FE-I4 will in any case be irradiated to check the quality of the bonding.

Test beams with high energetic particles and high resolution reference telescope may provide a very detailed map of the charge collection efficiency and time resolution and their dependence on the position of the sensor surface. Low energy beams are still useful to evaluate average efficiency of the devices under test.

The usage of FE-I4 as the readout chip allows for using the DAQ system and infrastructures of the ATLAS pixel collaboration and we plan to join test beams used also for other INFN CSN1 projects at SPS, PS and DESY. This will result in an effective cost and manpower saving. Therefore the only costs expected for this work package are the expenses for setting up the devices. Travel money is asked mainly for irradiation tests.

The Milano unit will take care of organizing irradiation tests, Genova of the characterization of the devices and all units will share the test beams organization and data taking.

Deliverables for this work package are studies of performance of irradiated and non-irradiated devices, to be presented at international conferences and eventually published.


1.3 Project Timelines, Milestones and Deliverables

The timeline for the Work Packages is illustrated in Figure 1. Some preparatory work in WP1 and WP2 will already starts in 2014. This motivates their immediate ramp up. Milestones and deliverables proposed for the Work Packages are summarized in Table 2 and Table 3, respectively.

Table 2: HVR_CCPD project milestones.

Table 3: HVR_CCPD project deliverables.

Figure 1: HVR_CCPD project timeline.

WP DATE MILESTONES1 Jun115 Submission8of8TPM11 Jun116 Submission8of8TPM21 Jun117 Submission8of8FPM2 Dec115 Characterization8of8radiation8hardness8of8dummies2 Dec116 Definition8of8CCPD8process8on8single8chips2 Dec117 Definition8of8CCPD8process8on8wafers3 Dec115 Characterization8of8FEI48and8TPM18assemblies3 Dec116 Characterization8of8FEI48and8TPM28assemblies3 Dec117 Characterization8of8FEI48and8FPM8assemblies4 Dec116 Conference8reports8of8irradiation8and8test1beam8results8on8TPM14 Dec117 Conference8reports8of8irradiation8and8test1beam8results8on8TPM2

WP DATE DELIVERABLES

1 Sep015 Availability9of9TPM11 Sep016 Availability9of9TPM21 Sep017 Availability9of9FPM2 Sep015 Production9of9dummy9wafers2 Jul016 CCPD9processed9single9chips2 Sep017 CCPD9processed9wafers3 Oct015 FEI49and9TPM19assemblies3 Oct016 FEI49and9TPM29assemblies3 Oct017 FEI49and9FPM9assemblies4 Dec015 Irradiated9TPM14 Dec016 Irradiated9TPM24 Dec017 Irradiated9FPM

WP Task J F M A M J J A S O N D J F M A M J J A S O N D J F M A M J J A S O N D1 Submission*of*1st*test*pixel*matrix*(TPM1)1 Characterization*of*TPM11 Submission*of*2nd*test*pixel*matrix*(TPM2)1 Characterization*of*TPM21 Submission*of*1*cm2*pixel*matrix*(FPM)1 Characterization*of*FPM

2 Development*of*CCPD*procedure*on*dummies

2 Development*of*CCPD*on*single*FECI4*chips

2 Development*of**CCPD*process*at*wafer*level*on*dummies

2 CCPD*process*on*full*wafer*with*FECI4*and*TP1/2

3 Production*of*TPM1*assemblies*boards3 Characterization*of*TPM1*assemblies3 Production*of*TPM2*assemblies*boards3 Characterization*of*TPM2*assemblies3 Production*of*FPM*assemblies*boards3 Characterization*of*FPM*assemblies4 Irradiation*and*testbeam*of*TPM14 Irradiation*and*testbeam*of*TPM24 Irradiaton*and*testbeam*of*FPM

2015 2016 2017


1.4 Participating Units (Sezioni INFN)

There are 3 INFN Groups (Sezioni) participating to the HVR_CCPD project with 18 Researchers and Engineers for a total of 4 FTE. The groups are listed in Table 4, where the number of researchers and engineers (“tecnologi”) and corresponding full time equivalent (FTE) is also reported.

Table 4: INFN Groups in the project, with local coordinators, number of researchers and engineers (“tecnologi”) and FTE’s.

1.5 Participants to the Project

There are 18 participants to the project from 3 INFN groups for a total of 4 FTE (see Table 5). A summary of the participation of the 3 groups is shown in Table 4, where the responsible (local coordinator) for each group is also displayed. Local coordinators will also act as responsible for the Work Packages lead by the respective units.

Table 5: List of participants with affiliated group and FTE fraction.

INFN$Group Sez. Coordinator Res/Tec FTE

Bologna BO Carla*Sbarra 3 0,40Genova GE Giovanni*Darbo 8 1,60Milano MI Attilio*Andreazza 7 2,05

Total 3 18 4,05

No. Sezione First-Name Family-Name Role FTE1 BO Alessandro Gabrielli RU 0,1444444444444442 BO Carla Sbarra RIC 0,2444444444444443 BO Mauro Villa PA 0,1444444444444444 GE Michele Biasotti Assegnista4 0,1444444444444445 GE Valentina Ceriale Dottorando 0,2444444444444446 GE Giovanni Darbo DR 0,3444444444444447 GE Andrea Gaudiello Dottorando 0,3444444444444448 GE Claudia Gemme RIC 0,1444444444444449 GE Paolo Morettini 1RIC 0,24444444444444410 GE Leonardo Rossi DR 0,24444444444444411 GE Mario Sannino PA 0,24444444444444412 MI Attilio Andreazza PA 0,34444444444444413 MI Mauro Citterio DT 0,24444444444444414 MI Valentino Liberali PA 0,24444444444444415 MI Chiara Meroni DR 0,34444444444444416 MI Francesco Ragusa PO 0,34444444444444417 MI Hithesh Shrimali Assegnista4 0,54444444444444418 MI Alberto Stabile Assegnista4 0,344444444444444


1.6 CV of the Scientific Project Coordinator

Attilio Andreazza Born in Milano 24/04/1967 Presently Associate Professor at Università degli Studi di Milano

Academic career 2011- Associate Professor at the Physics Department of Università degli Studi di Milano 2000-2011 Research officer in particle physics at the Physics Department of Università degli

Studi di Milano 1999-2000 Wissenschaftliche Mitarbeiter at Physikalisches Institut dek Universität Bonn (D) 1997-1998 Fellow of the European Laboratory for Particle Physics (CERN). Geneva (CH) 1995-1996 Post-Doc fellowship of Istituto Nazionale di Fisica Nucleare 1995 Ph.D. in Physics at Università degli Studi di Milano 1991 Degree in Physics at Università degli Studi di Milano Research activity and responsabilities 2012- Coordinator of Group 1 (physics at accelerators) of Milano INFN section. 2010-2012 Convener of the ATLAS Tracking group and member of the Physics Coordination 2006-2010 Coordination of the simulation and reconstruction software of the ATLAS pixel

detector 2004-2006 Coordination of the ATLAS pixel detector modules production and acceptance tests. 1999-2004 Design and test of rad-hard prototype modules for the ATLAS silicon pixel detector 1993-1998 Responsible of the alignment of the DELPHI tracking system 1990-1996 Construction alignment and operation of the silicon microstrip vertex detector and

upgrades with double sided microstrips and silicon pixels Scientific activity is documented by more than 480 papers published on peer-reviewed journals and by 18 presentations at international conferences. The most relevant publication for this proposal are listed in a separate document.

1.7 Funding Request

The financial resources to exploit the three year program of the call amount to 309 k€. The splitting of the cost per work package (WP), with some details for the different items, and for the financial year (FY) is in Table 6.

We consider that the large part of the cost in each WP will go into common orders.

The required funding profile is the one shown in Figure 2 and is consistent with the HL-LHC preparation plans.


Table 6: Money resources for funding the 3-year HVR_CCPD project

2015 60k€((((((((((((( MI Submission(of(1st(test(pixel(matrix((TPM1)2015 3k€((((((((((((((( MI Evaluation(board(for(TPM12015 2k€((((((((((((((( GE Cadence(IC(License2016 40k€((((((((((((( Mi Submission(of(2nd(test(pixel(matrix((TPM2)2016 3k€((((((((((((((( MI Evaluation(boards(for(TPM2

2017 80k€((((((((((((( MIContribution(to(submission(of(full(size(matrix((FPM)(or(to(final(architecture(demonstrator

2017 3k€((((((((((((((( MI Evaluation(boards(for(FPM191k€%%%%%%%%%%

2015 8k€((((((((((((((( Material(for(hybridization(test(on(single(chip((at(home:(ATLAS/LTD(labs)2015 20k€((((((((((((( Hybridization(at(wafer(level((wafer(procurement)(2015 3k€((((((((((((((( Tooling(for(hybridization:(µVpipette,(tooling(adaptation(for(Fineplacer(962016 8k€((((((((((((((( Material(for(hybridization(test(on(single(chip((at(home:(ATLAS/LTD(labs)2016 30k€((((((((((((( Hybridization(at(wafer(level((industry)(2017 5k€((((((((((((((( Material(for(hybridization(test(on(single(chip((at(home:(ATLAS/LTD(labs)2017 20k€((((((((((((( Hybridization(at(wafer(level((industry)(

94k€%%%%%%%%%%%%

2015 3k€((((((((((((((( Module(assembly,(flex(hybrids,(to(test(FEI4+TPM(assemblies2016 3k€((((((((((((((( Module(assembly,(flex(hybrids,(to(test(FEI4+TPM(assemblies2017 3k€((((((((((((((( Module(assembly,(flex(hybrids,(to(test(FEI4+TPM(assemblies

9k€%%%%%%%%%%%%%%

2015 2k€((((((((((((((( MI Sample(preparation(for(irradiation(and(testbeams2016 2k€((((((((((((((( MI Sample(preparation(for(irradiation(and(testbeams2017 2k€((((((((((((((( MI Sample(preparation(for(irradiation(and(testbeams

6k€%%%%%%%%%%%%%%

2015 3k€((((((((((((((( BO/MI/GE TestVbeam,(contact(with(industries(and(partners.2016 3k€((((((((((((((( BO/MI/GE TestVbeam,(contact(with(industries(and(partners.2017 3k€((((((((((((((( BO/MI/GE TestVbeam,(contact(with(industries(and(partners.

9k€%%%%%%%%%%%%%%

309k€%%%%%%%%%%Grand%total

FY #Cost# Description

Travel#Money#("Missioni")

Total

FY #Cost# Description

Total

Group

Group

WP1#=#HV/HR=CMOS#Chip#Design#&#Test

WP3#=#Module#assembly#&#Test

WP4#=#Irradiation#&#Test#beam

Total

Total

#Cost# Description

Description

Total

WP2#=#CCPD#hybridization

FY

FY #Cost# Group

FY #Cost# Group Description

Group


Figure 2: Funding profile to fully exploit the project in the three-year plan. On the right is shown how the totals are split per WP.

1.8 Collaboration with Enterprises

The HVR_CCPD project activities are carried on with strong collaboration and partnership with STMicroelectronics R&D group of Agrate Brianza. This group has the responsibility for the development of the proprietary BCD8 process. This is a HV epitaxial process combining Bipolar, CMOS and DMOS devices in a single technology.

The main customers of this process are power applications, requiring a low resistivity substrate. Anyhow, since the process is epitaxial, it is possible to replace the substrate with high-resistivity wafers, resulting in a depleted region suitable for HV/HR-CMOS detector.

The ST Microelectronics R&D group has offered the possibility to take part in development runs of multi-project wafers. Part of the wafers can be processed with the high-resistivity substrate. A non-disclosure agreement (NDA) is in preparation and will be signed by the participating groups.

1.9 External project Funding

Given the very early stage of the HVR_CCPD proposal no external funds are available yet, but an application to AIDA-2 is in preparation where one of the work-packages is dedicated to HV/HR-CMOS simulation, design and hybridization. Genova and Milano will be beneficiary in that WP. In case of approval of the AIDA2 project we will also have irradiation time paid on EU funds on proton and neutron facilities participating in the AIDA2 network.

We also plan to apply for EU funds as soon as possible. One possible option will be a FET (Future Enabling Technology) application with STM for the design of sensors and with other firms that could contribute to industrial hybridization.

Other EU funding could come through Initial Training Networks (ITN) - Marie Curie Actions.

FY Cost2015 104k€((((((((((((((((2016 89k€((((((((((((((((((2017 116k€((((((((((((((((

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!k€!140.0!

2015! 2016! 2017!

Travel!

WP4!

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2 SCIENTIFIC PROPOSAL

2.1 Technical Proposal

The project investigates the possibility to develop a hybrid pixel detector, where the detecting layer uses an integrated IC technology suited for high voltage application. Using a high/moderate resistivity substrate is possible to deplete the silicon underneath the pixel, such that the released charge in the silicon is collected drifting the charge under the action of an electric field. Figure 3 shows the basic principle of charge collection in a HV-CMOS input stage using a three well technology. A pixel matrix will be implemented by the implantation of deep n-wells (the gray region in Figure 3). The deep n-well is connected to ground through a resistor. In each pixel there will be a charge amplifier and a discriminator is capable of detecting the charge signal. The above basic pixel cell circuitry can be fully contained in a single deep n-well or in multiple n-wells.

Figure 3: Principle of charge collection by deep n-well electrode in a depleted CMOS substrate.

In MAPs (Monolithic Active Pixels) the signal is collected by diffusion, while in the proposed device (HVR_CCPD) is collected by drift. This allows high-rate and high-dose applications (for instance ATLAS and CMS pixel/strip detectors).

The need of high voltage technology, with a rather non standard substrate, heavily limits the density of the logic that can be implemented in each pixel (like, for example, time stamp, multi event buffer, trigger). The basic cell circuitry integrated in the pixel cell will not allow realizing the complex readout architecture needed for HL-LHC applications. Therefore sophisticated data handling is achieved by coupling this detector layer with minimal analog/digital front-end to a

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NMOS! PMOS!

Deep!n#well!

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complete readout chip designed to operate in the LHC environment, like the FE-I4 ATLAS chip or the future front-end developed by the RD53 collaboration.

In the traditional hybrid pixel detectors, the connection of the sensor to the front-end is done in DC (bump-bonds), in HVR_CCPD’s is done in AC. A thin dielectric layer, between the pads available in each pixel, creates a tiny capacitor coupling between the HV/HR-CMOS active sensor and the front-end chip.

Ivan Peric [01], in 2007, proposed this type of hybrid pixel, that were called Capacitively Coupled Pixel Detectors (CCPD). The basic concept of this detector is shown in Figure 4.

Figure 4: simplified structure of a CCPD with an HV/HR-CMOS active sensor.

2.1.1 State of the art and objectives of the project

After the original proposal of the HV-CMOS detector concept as an improved MAP [01], it was realized that, besides a building monolithic detector, the full CMOS signal from the comparator output could be capacitively coupled to a readout ASIC [07]. The first CCPD prototypes were built in the 0.35 µm AMS technology, with matrixes of few mm2, and showed good performance after irradiation up 1015 neq/cm2 and 3 MGy, with a noise below 100 e- [08].

The observed radiation tolerance is one order of magnitude higher than the one demonstrated by MAPs detectors and at the level required for pixel detectors at the LHC. That makes these detectors appealing for particle physics experiments. Hybrid designs have been proposed for high counting rate applications, namely pixel detector at LHC or CLIC [09]. Monolithic solutions, with a very low material budget, have been proposed for the Mu3e experiment [10] and as an alternative to strip detectors [11].

+

TOT$=$sub$pixel$address$

Readout$pixel$–$ATLAS$FE:I4$

Size:$50$µm$x$250$µm$

Size:$33$µm$x$125$µm$

Different$logic$1$levels$

CCPD$–$The$principle$R/O$Front*end$

HV/HR*CMOS$

Dielectric$


The application to the HL-LHC detector upgrade requires demonstrating radiation hardness to unprecedented levels of 1016 neq/cm2 and 5 MGy, for the sensor, the readout electronics and the interconnection technique.

The most mature device is this field is the HV2FE-I4 chip, a 10 mm2 ASIC in 180 nm AMS technology [12]. It is a CCPD designed to be coupled to the ATLAS FE-I4 readout ASIC [04]. After irradiation to 1 MGy, the observed performance is encouraging but still does not demonstrate the required radiation hardness [12]. In addition in these devices no control of the capacitive coupling process is implemented.

In addition, the 180 nm AMS process has significant limitation reaching at most a 15 µm thick depleted region at the 60 V high voltage guaranteed by the technology.

Different alternative technologies are under study by various groups, to explore if they can provide a thicker depleted layer and better performance after irradiation. One key aspect is the availability of a high resistivity substrate. This is usually not part of the standard processes since most HV-CMOS technologies target power application where low resistivity bulk material is preferable. Some candidate technologies for development of CCPD are listed in

Foundry Technology node [nm]

Substrate resistivity [kΩ]

ESPROS 150 2

XFAB 180 0.1-1 (on request)

TowerJazz 180 1-3 (epitaxial)

Toshiba 130 3

LFoundry 150 2

Global Foundries 130 3

AMS 180 0.01

ST Microelectronics 160 0.01-1 (epitaxial)

Table 7.

Foundry Technology node [nm]

Substrate resistivity [kΩ]

ESPROS 150 2

XFAB 180 0.1-1 (on request)

TowerJazz 180 1-3 (epitaxial)

Toshiba 130 3

LFoundry 150 2

Global Foundries 130 3


AMS 180 0.01

ST Microelectronics 160 0.01-1 (epitaxial)

Table 7: Available HV/HR-‐CMOS technologies

The other critical feature for building large area CCPD detectors is the hybridization. The uniformity of the capacitive coupling must be controlled over areas of few cm2 (FE-I4 has a 4 cm2 area, for example). The pads of the sensor ASIC are also opposite to the pad of the readout ASIC and cannot be accessed by wire bonding, requiring either by Thru Silicon Vias or interconnections through the readout ASIC. There is currently no proven solution for these hybridization aspects.

The aim of this project is to address these technological challenges and to demonstrate that using an HV/HR-CMOS technology is possible:

• To produce radiation hard sensors; • To reduce the cost of the sensors using high volume production processes; • To reduce the production time that would be needed for large area silicon sensors; • To improve the tracking performance realizing detectors with smaller pixel and thinner

sensitive layer; • To reduce the hybridization cost since the process for dielectric layer should be simpler and

with higher yield than bump-bonding. The requirements that we aim to reach with this detector, having in mind possible application in the HL-LHC upgrade of ATLAS and CMS, are:

• Time resolution better than 25ns; • In time efficiency better than 97-98 %; • Radiation tolerance: up to 10 MGy for the innermost layer, 3 MGy for other layers.

The innovative characteristics of the project are:

• Access to the ST Microelectronics BCD8 160 nm technology, never used before for this kind of detector. It is promising because it provides a complete set of devices (Bipolar, CMOS, D-MOS) and it is an epitaxial process (among other vendors, only TowerJazz has an epitaxial process), allowing the choice of different substrates. First TCAD simulations indicate the possibility to reach a 30 µm depleted region.

• Using a full analogic design for the first iteration. This is possible because the BCD8 technology should enable to have large enough signals that we can directly exploit the FE-I4 analog features to measure pulse height. This simplifies the design and provides access directly at pulse shapes. Compared to usual designs, that readout the comparator output logical signal, our approach enables more detailed studies of the collection process.

• Prepare for integration of the new devices with the next generation of readout ASICs in 65 nm, developed by the CERN RD53 and INFN CHIPIX65 projects.

• Develop a process able to guarantee a uniform capacitive coupling on the full area of a 4 cm2 readout chip.

The proponents are already active in the ATLAS upgrade projects, contributing to the development of 3D sensors, front-end electronics, bump bonding technology, and readout systems. Therefore will have access to irradiation and test beams within the wider scope of the ATLAS upgrade. We are already in close collaboration with the international groups involved in the design of HV/HR-CMOS detectors and in particular the HV2FE-I4.


2.1.2 HV/HR-CMOS Design, Technology and Foundry.

We intend to develop the HV/HR-CMOS detectors with the BCD8sP technology from

STMicroelectronics (STM). See

Figure 5 for the BCD8s platform.

Figure 5:BCD8s process platform.

This technology can be modified, using an high resistivity substrate, to allow a depletion layer of approximately 30µm, which is enough to efficiently detect the charge deposited by a minimum ionizing particle (MIP). The modification of the substrate will be done in close collaboration with the STM R&D group in Agrate Brianza (MI). It is important that the modification of the technology is done under the control of the TCAD simulation performed by STM. This will ensure that the technology files will be accurate, allowing designing and properly simulating the chip. Figure 6 shows depletion width as function of the substrate resistivity and applied bias voltage.


Figure 6: Depletion width versus reverse bias voltage for different resistivity values of the substrate.

The BCD8sP platform[02][03] uses a 160nm 3-well CMOS technology, where also bipolar and D-MOS transistors can be used. The technology allows 3.3 V designs withstanding 70 V isolation. The use of 3 wells gives an important benefit for the type of design we want to implement. Since we use the deep n-well as collecting electrode, the use of a second n-well, to contain the p-transistors, allows a full CMOS design, instead of a more tricky N-MOS only design. Having the pixel cell electronics inside the charge collection well (see Figure 4) allows a design with the collection node having a large fill factor. A large fill factor favours charge collection within a short drift distance (no lateral drift), and therefore reduces trap recombination in irradiated devices. A large fill factor also implies large sensor capacitance (deep n-well to p-well junction) and requires precautions in the design for noise, crosstalk and speed.

Figure 7: Simplified section of a pixel cell with 3-well technology (like BCD8s).

In the first part of the project we will realize prototypes and tests structures to characterize the technology and demonstrate that is adequate for our application. It will include fully functional CCPD prototypes. We plan to design a few chips in MPW (Multi-Project Wafers) provided by STM. MPW access is directly through the R&D group in Agrate. Since we will use special

0

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idth [µ

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substrates, we will buy few complete wafers (useful for wafer level hybridization studies). To reduce the cost of MPW masks, STM uses the Multi-Layer Reticle, which limits the MPC dimensions to ¼ of the maximum allowable: i.e. 1.6 x 1.3 cm2. We will use a part of such reticle for our submission, so the test design will be smaller than the FE-I4 ATLAS pixel front-end chip, but still large enough to study system aspects. The plan is to have 3 design submissions in the 3 years of the project.

2.1.3 HV/HR-CMOS test

The HV/HR-CMOS chips will be tested at first as stand-alone blocks: amplifier, discriminators for noise and timing behaviour before and after irradiation, memory elements for SEU resistance, etc. Already in the first silicon batch we will put a matrix of pixel elements to use with the FE-I4. Assemblies with the FE-I4 will be (initially) mounted on PCB and will be readout with a USBpix system adapted for the HV/HR-CMOS modules.

Test of the modules, and in a more limited way of the pixel cells adapted for direct readout, will be done with sources and focused laser, prior to complete test in a particle beam. We will use a pulsed laser beam (PicoQuant PLD800) to scan a pixel cell from the bottom of the sensor (the bottom side will not be metalized). The laser spot has 9 µm FWHM on the focal plane. With the laser we can have information on the timing response and on the uniformity of the collection charge at the edges of the pixel cell. We also consider performing measurement of edge-TCT (Transient Current Technique) to evaluate the depth of the depleted region (including indirect TCT measurements through the FE-I4 readout). The FE-I4 could be used as sampling waveform recorder by changing the delay of the laser pulse and the synchronous readout clock and varying the discriminator threshold. Figure 8 shows the laser setup. Almost all the components exist from previous setups.

Setup+SchemaTc+

19/06/14# 4#

USBPIX+Board+

Delay+

Logic+Analyzer+

PaNern+Generator+

DRIVER+LASER+

LASER+HEAD+ATTENUATOR+

SPLITTER+

FOCUSER+

SENSOR+ XYZϑ+MOVE++

MONITOR+USB+Meter+


Figure 8: Block diagram of the laser setup. (better figure to be done)

Since we are planning measurements on irradiated parts, we will have in the test setup the possibility to cool down the device under test (DUT), in order to control the leakage current noise. This will be done using a chiller with glycol bath connected to a plate with a cooling serpentine. Part of the system will be an automatic micrometric control of the XYZ and theta positions of the DUT. Figure 9 shows the CAD drawings of the laser setup on the optical bench.

Figure 9: Laser setup on optical bench.

2.1.4 HV/HR-CMOS Hybridization

Another critical aspect of the R&D is the development of technologies for cheap hybridization. Differently to passive silicon pixel sensors, active HV/HR-CMOS sensors do not need DC coupling to the input of the R/O front-end chip (FE). AC coupling can be done through metal pads, present on the facing HV/HR-CMOS and on the FE chip. Such tiny pads are 18 µm in diameter (standard value used in the FE-I3/FE-I4 chips). A rough estimation of the capacity (C) needed to transfer 1 V signal (discriminated output of a HV/HR-CMOS pixel cell) to produce a charge of 1.6 fC (10ke) is 1.6 fF. If we consider as dielectric an epoxy material (SU8), the relative permittivity is 3.2. From the above values and the formula in the figure below the thickness of the dielectric should be 5 µm.

Such thin layer dielectric can be obtained by epoxy glue: for instance with a rather low viscosity SU8, like SU8-2000.5 or SU8-2002. The problem of keeping uniform and defined distance over the whole surface can be solved by patterning some spacer on the surface of one of the two chips. SU8 is a negative photoresist where an image can be produced with a contact mask. The wanted thickness (height of the spacers) is obtained by spinning of SU8. Once the spacers are produced a

Future+Upgrade+

19/06/14# HV#CMOS#Mee6ng#1910612014## 6#


tiny amount of SU8 is deposited and the two chips are pushed together until the spacers are in contact, limiting the minimum distance. Figure 10 shows the gluing process.

Figure 10: gluing process of HV/HR-CMOS to FE chip.

The alignment of the top and bottom chip is another critical issue. We plan to use a flip-chip machine (in a similar way that is done for bump-bonding) to align front-to-front the facing chips and then apply pressure and temperature (to polymerize the epoxy SU8). We are equipped to develop the process in house (INFN Genova) using tooling and apparatus from the ATLAS and from the LTD (Low Temperature Detector) laboratories.

Preliminary test will be performed with microscope slide cover glasses where we plan to deposit metal (LTD lab) simulating bonding pads. These will be used to align with the flip-chip machine. Once glued together the top and bottom the alignment is easily cheeked by visual inspection with a microscope. To verify the uniformity of the glue thickness we will deposit some metal structures on the glasses such to create capacitors of a few pF (7÷4 pF for 3÷5 µm of dielectrics). Figure 11 and Figure 12 show the 3D and overlaid views of the stack.

R/O$CHIP$

R/O$CHIP$

Glue$deposi2on$

R/O$CHIP$DETECTOR$CHIP$Align$&$pressure$


Figure 11: Test structure to verify the gluing process with microscope slide cover glasses. In grey and purple are the top and bottom metal layer deposited on glass. The green in the middle are the SU8 spacers.

Figure 12: Full stack of bottom (white) and top (purple) metal and SU8 spacers (green).

The XY alignment can be done with a precision of 6-7 µm with the Fineplace 96 die bonder. We think that this is good enough to develop the process. Results of alignment with patterned glasses are shown in Figure 13.

3D#View#

Overlaid)bo,om/top)glasses)with)spacers)interposer))

7)capacitors)to)evaluate)thickness)of)the)glue)layer)

Rows)of)bump=pads)to)visually)align)top/bo,om)

Capacity=meter)probe)pads))

SU8)spacers)


Figure 13: test of alignment with old glasses having patterned bump (from early years 2000) used to develop indium bump-bonding with Alenia-Marconi (now Selex).

The process will be qualified for mechanical and thermal test. We are able to do thermal cycles with an environmental chamber (Binder MK-53). Changes in bow can be measured with the KLA-Tencor mechanical profilometer. We will also irradiate and verify the changes in the mechanical electrical properties (X-rays, neutrons). One of the critical parameter is the uniformity of the spacer thicknesses. This will be verified by mechanical profilometer.

Once the procedure is established on dummies, we will test with real chips. The process for single dies will be done and qualified with the instruments we have in Genova, Qualification will be done by measuring electrical behaviour and by thermal cycles and irradiation.

Since we want to develop the full process at wafer level, we will investigate the transfer of the process to industry. We think that the deposition of the SU8 spacers should be done on the R/O chip. We will look at industries that can process 8” and 12” wafers (RD53 chips will be on 12” wafers).

The whole process will also have to consider how to connect the HV/HR-CMOS I/O and Power pads in a module system. One possibility is to use TSV (Thru Silicon Vias) to bring these pads to the opposite side of the HV/HR-CMOS chips. Another possibility to investigate for the I/O pads is to connect them to the front-end R/O chip in AC. This is in principle possible if the input/output signals are DC balanced: BPM (BiPhase Mark Encoded) for Data/Clock and 8B/10B for the Data out. This is what is used by the FE-I4 and could be replicated in the HV/HR-CMOS chip. The problem is to design a circuit that uses very small decoupling capacitances (0.1 ÷ 0.01 pF).

To complete the hybridization of the CPPD we have to consider how to bring power and ground to the HV/HR-CMOS chip. The pads available for powering are on the side of the chip facing the R/O chip. This is rather inconvenient at system level for using wire bonding: should wire bond both sides of the CCPD. Different solution can be considered. One is to process TSV to bring the few lines to the opposite side. Other possibilities will be investigated to package the CCPD with the flex hybrid circuit into a module assembly.

2.1.5 Irradiation & Test Beam

We are considering irradiation with gamma, n and p of components and complete assemblies. We want to test the radiation tolerance of the HV/HR-CMOS both to ionizing radiation and to bulk

Alignment at X + 0 mm Alignment at X + 8 mm


damage. We expect that the ionizing radiation will affect the gate oxide, changing the transistor Vt, while the NIEL will affect the charge collection due to dislocation center generating charge trapping. The hybridization technology has also to be tested for radiation damage. We would like to push the qualification of the HV/HR-CMOS pixel modules to values that will be seen in HL-LHC at the innermost layer: 10 MGy and 2x1016 1MeV neq/cm2. We will perform irradiation in collaboration with ATLAS and CMS colleagues who will need similar requirements for testing samples. We also plan to get support for irradiation facilities from AIDA-2 partnership.

Final qualification of the devices will be done with test beam. We will have to map the charge collection inside a pixel cell. This is done with high-energy beams (like from SPS) and high resolution telescope like EUDET (<3µm of spatial resolution). Tests beam campaigns will be organized together with other pixel detectors that will be done in the next years.

2.2 Significance with respect to INFN core Research

The HV/R-CMOS technology is of great interest for application in the upgrades of the LHC experiments [09]. With respect to currently available technologies, it offers potential improvements:

1. Low-cost sensor fabrication, using existing commercial processes. 2. Increase in performance due to reduced radiation length of the sensor and of the cooling

system (operation below 0 °C is not mandatory). 3. Additional reduction of cost and complexity can be reached by using capacitive coupling to

fast readout electronics, instead of bump bonding. Items 1 and 2 are also relevant for future experiments, most notably at high luminosity lepton colliders, where speed, space resolution and minimal mass are very important.

In application with not extremely high count-rate, a solution with strip-like readout, but pixelated resolution, by encoding the position information in the pulse height is also of interest [11].

Such solution may also provide integrated detector and readout electronics setups that can operate at low voltage to be used in standard laboratory practice.

2.3 Participant Units: Expertise, Infrastructures, Roles and Contributions

In the following section a description of the expertise, an expression of interests for the proposal Work Packages and a list of available infrastructures is presented separately for each institute.

2.3.1 Bologna

Expertise

In the recent past the Bologna group contributed to the CNS5 experiments Slim5 and VIPIX and to two PRIN projects dedicated to the development of monolithic pixel sensors with expertise on the design of the chip peripheral readout and precise responsibilities in the Trigger/DAQ Work Package. In this respect the group also developed the chip readout electronics and the software framework used in several test beam performed both at the PS and SPS [13][14][15]. During these activities several devices have been tested among which analogic and digital CMOS sensors, silicon micro-strips, scintillators and photomultipliers. The detectors used in the test beam, often coming


from different projects, have been put in common operation via a fast online synchronization system using FPGA. The Bologna group is able to provide a general purpose DAQ system based on VME programmable boards, which can be configured for different uses respect to the ones initially foreseen.

The group has also expertise in chip design. Recently within the group was realized an asynchronous digital circuit, without external clock and with a full-custom design. The chip is used for the wireless transmission of signals coming from external sensors or from an integrated radiation sensor. The circuit includes a "ring" oscillator, a driver for an integrated antenna and a VCO [16][18]. The used technology is the TowerJazz 180nm. In the past the design activities on standard-cell concerned the development of an architecture of digital readout of a matrix with 4096 pixels for a total of ~ 100 kcells. The design was performed in VHDL-Verilog (Synopsis) and integrated using Encounter. The used technology was the ST 130nm .

Infrastructure and Equipment

Bologna is equipped with a full DAQ system ready for use in any beam-test or laboratory setup, including dedicated PCs, racks, crates, VME computer boards and VME programmable boards for trigger and synchronization purposes. Both a local installation of ATLAS TDAQ SW or any version available on AFS can be used as SW infrastructure.

As far as microelectronic instrumentation is concerned, a full CAD/CAE station with Cadence SW is installed and two licences are available via the Europractice licensing system. Major technology libraries are already installed and other libraries may be installed upon request. Software for digital and analog simulation is also available and the Calibre tool via Mentor Graphics can provide extraction of parasitics. Besides that, and besides the regular electronic instrumentation of a laboratory, the laboratory features a multi-channel digital pattern-generator to test ASIC prototypes.

Roles and Contribution to Work Packages

WP1

The group will take part in the design and test of the CMOS sensor prototypes.

WP4

The group will participate in test beam setting up, operation and analysis

2.3.2 Genova

Expertise

The group joins the expertise of researchers that developed hybrid pixel sensors since early 1990 and researchers who have expertise in micro-fabrication and thin film grow for low temperature detectors.

One component of the Genova group has a long experience in silicon tracking detectors, started with fixed target experiments at CERN West Area. In ATLAS the group plays a leading role in the Pixel Detector [19] since its very first days. Genova has contributed to the layout of the detector and many items of R&D for its construction. In Genova one third of the barrel modules − the building blocks of the detector − have been built, characterized and then assembled on the Carbon-


Carbon cooling structures. A major role has been played in the assembly, installation and commissioning at CERN. The readout software is also under the responsibility of the group.

The module control chip (MCC) of the ATLAS Pixel detector was completely designed in Genova. Several designs and technologies were used from prototype to final version (250 nm CMOS).

Since 2009, the research unit has worked on 3D silicon pixel detectors in collaboration with the University of Trento for the FBK sensors and with INFN-Milano for the bump-bonding at Selex [20][21]. The first sensors have been tested with the pixel detector readout chip. Once the Phase-0 upgrade for the ATLAS pixel detector has been approved, the group has worked to qualify the 3D silicon sensor as detector technology, assembling and testing irradiated and non-irradiated devices both in the laboratory and in test beam. In June 2011 the 3D technology has been chosen to cover 25% of the detector and since then we have collaborated closely with FBK and CNM to qualify the produced 3D sensors. In these days the unit is fully involved in the assembly and testing of the IBL planar and 3D modules, sharing the task with Bonn University. Very interesting measurements of 3D sensor properties are undergoing with the help of several students from Genova, Barcelona, Tokyo and Geneva.

Genova has also contributed in the FE-I4 chip by porting the MCC command decoder to the new architecture and technology.

Besides modules, the other main areas of expertise are in the readout software, the support and cooling structures, design and production of electrical circuits; in particular in the IBL project the inner services (module and stave flex) are under our responsibility.

The second component of the group are researchers of the Low Temperature Laboratory (LTD); a facility that has been set-up I the last 25 years by Flavio Gatti and his team. This group has access to a class 100 clean room at INFN Genova equipped with infrastructures for metal deposition, photolithography and MEMS realization with photoimageable resists, like SU8. Their contribution will be particularly qualified for the WP2.

Infrastructures and equipment

Genova has a large pixel laboratory for studying silicon detectors, with the necessary equipment. In particular:

• Wire bonding: Hesse & Knipps mod.715 • Pull test for wire-bonds: Dage 3000 • Fineplace 96 die bonder from Finetech • Alessi REL 4500 - 6” probe station • Climate chamber: Binder MK-53 (-40 ÷ +180°C) • Mini Flecto System for Ar / O plasma cleaning. • Thermostatic bath: Lauda RP-845 (-45 ÷ + 200°C), RP-855 (-45 ÷ + 200°C) • Infrared camera: FLIR SC620 (Temperature Range: –40°C to 500°C, Thermal Sensitivity

≤55mK) • Pulser Agilent 81110A, Logic State/Time Analyzer and pattern generator HP16700, CV-meter • Pulsed IR Laser: PixoQuant PLD-800 driver, Laser head LDH-P-160 (1067 nm, 44 ps), focuser

(9µm spot at 12 mm). • Microscope with 2.1M pixels camera: Keyence VX-8000, several microscopes.


• Mechanical profilometer KLA-Tencor P7: 8”, 1 mm step, Repeatability/reproducibility: 4/15 Å Vertical resolution: 0.01/0.60 Å

• Radioactive β and γ sources • USB-based FE-I4 readout system • 2 clean rooms class 10000 (140 m2) and a large Low Temperature Detector facility with instruments like:

• Thin Film Growth Systems o 2 E-guns 4 material each @ 10-9 mbar o 2 AC & 1 DC Magnetron Sputtering Systems o Pulsed Laser Deposition System @ 10-10 mbar

• Micro-fabrication o Reactive Ion Etching, Plasma & Wet etching o Mask Aligners, Oxygen Plasma & Ion Beam o PLD film deposition o TES on SiN membrane o Critical Point Dryer

Roles and Contributions to the Work Packages

WP1

The Genova unit will provide support in the designs of the CMOS sensor and of the adapter cards for test of dies

WP2

The unit is responsible for the full development of the connection process.

WP3

The group is responsible for the work package. It will develop the adapters needed to interface the assemblies with the USBPIX boards. It will characterize the detector with electrical measurements, source measurement and laser.

WP4

Preparation of the devices for test beam will be performed in Genova. The group will also participate to test beam data taking.

2.3.3 Milano

Expertise

The Milano research unit consists of a group of integrated circuit designers and of a group of researchers who gave a major contribution to the development, construction and operation of precision tracking detectors.

The integrated circuit designers have expertise in the design of radiation-hardened CMOS circuits, and dedicated CMOS circuits for high-energy physics experiments [13][14]. Milano has played a


key role in the design of the associative memory chips for the FTK project (trigger ATLAS update), and in chip-level integration of CHIPIX65 prototypes (new CMOS pixel circuits with unprecedented radiation tolerance level). The team has also experience in radiation tolerance measurement.

The Milano group has played a major role in the ALEPH and DELPHI experiments at LEP and participated since the early stage in the ATLAS pixel detector [19]. In particular the group took the responsibility of coordinating the indium bump-bonding activities with Selex [20][21]. This activity included the design and realization of the probing system and the stripping machine used during the detector production. They were used for the quality check of modules after the flip-chip process and the reworking of defective modules. Researchers from the Milano unit have also experience in the calibration and operation of modules equipped with FE-I3 and FE-I4 chips.

The Milano group had also a leading role in the characterization of the pixel detectors in test beams, having performed the measurement of the efficiency, resolution and Lorentz angle, and developed analysis techniques to assess timing performance and charge trapping which provided inputs for the improvement of both the electronics and detector design [22].

The group can count on a class 10000 clean room for testing of electronics and sensors, and on support of the electronics and mechanical engineering services, which have build the probing and testing setup used for the qualification of the ATLAS pixels and the power regulation system used for Pixels and IBL.

Infrastructures and equipment

The group has a CAD/CAE laboratory, with Cadence and Ansys suites for ASIC and printed circuite design, which has been used for Super-B ASIC and Flex-Hybrid design, for ATLAS FTK associative memory ASIC, developments within the CHIPIX65 and RD53 Collaboration.

The Milano unit is equipped with a clean room and laboratories for measurement and operation of silicon detectors and microelectronic circuites, with the related equipment. In particular:

• Wire bonder Kulicke and Soffa Model 4123 • Ball bonder Kulicke and Soffa Model 4524 • Alessi REL 4500 - 6” probe station • Karl Süss SOM4 probe station • Climate chamber Votsch VT 7010 • Thermal bath Julabo F30-C • Radioactive β and γ sources

• USB-based FE-I4 readout system • Clean room class 10000 Roles and Contributions to the Work Packages

WP1

The unit will take the main responsibility of the prototype design. It will develop the setups for probing the bare dies and for

WP3


The unit will take in part in the electronic characterization of the assembled devices and in measurements with radioactive sources. It will also explore the feasibility of cosmic ray measurements using an on-site strip telescope.

WP4

The unit has responsibility of the coordination of the work package. It will organize the irradiation of HV-CMOS devices and hybridized samples. It will perform the analysis of test beam data.

2.4 Involvement of External Organizations

This proposal involves STMicroelectronics, which allow access to the R&D runs for the BCD8 technology at the factory in Agrate Brianza.

The project benefits from the collaboration with the groups of the ATLAS experiment, both from INFN and foreign institutions, involved in the R&D for the upgrades at HL-LHC. The readout systems for FE-I4 chips that will be used in WP3 and WP4 are realized by this collaboration. In addition test beams and irradiation time can be shared.

In particular the proponents of the HVR_CCPD project are in close cooperation with the groups of Bonn, Karlsruhe and Marseille that are developing similar devices in different technologies. This provides a sharing of competences and design aspects, with the common aim to assess which is the best process for the production of this kind of devices. It is especially relevant for the mitigation of the risks assessed in section 2.6.

Some of the proponents are also involved in the INFN project CHIPIX65 and the CERN project RD53, developing a front-end chip in 65 nm technology for pixel detectors at the HL-LHC. That will help in harmonising the new detector design with that of the future readout chips.

2.5 Implementation of the Project within Resources

The funding profile described in section 1.7 is laid out giving emphasis to the two main development goals: the HV-CMOS sensor and the hybridization technique.

The sensor development costs are driven by the submissions to STMicroelectronics. To allow for hybridization of the devices, the minimal size cannot be much smaller than 5×5 mm2. Therefore we plan to exploit the Multi-Layer-Mask approach and the participation of multi-project runs to keep the costs on average at 50 k€ each for the early submissions, with higher costs for the later ones with a larger size detector. Most of the testing and assembly equipment is already available in the sites and only some adapter cards needs to be developed for characterization of single dies and assemblies.

For the development and qualification of the hybridization process, equipment for the deposition of SU8 spacer is already available within the Low Temperature Detector laboratory, and the only additional instrument needed is a new chip-flipping machine. Therefore most of the cost is due to the consumables. It has a peak in the first year due to the need to purchase the minimal amount of FE-I4 and mechanical wafers needed for the development of the hybridization technique. It cannot be deferred because the production process used for FE-I4 is being dismissed and wafers cannot be ordered at a later stage. In the final part of the project a cost is foreseen for the development of the deposition on full FE-I4 wafer that must be done at an external firm.


The group human resources match the goals and the timeline of the project.

The hybrid approach of the HVR_CCPD concept decouples the readout architecture from the analog signal generation, resulting in a strong simplification of the CMOS sensor design. This simplification is a key part of the success of this project, because the sensor, besides the amplification chain, needs only a limited amount of configuration logic and service circuitry. Therefore a small team can completely develop the sensor design.

The Milano and Genova groups will develop the initial sensor. An increased participation by the Bologna group is expected already in 2015, with additional human resources that cannot yet be accounted in this proposal, but will become available in the next months.

The hybridization development and module assembly tasks present no critical issues, given the resources both in term of researchers and technicians in the Genova unit.

Most of the researchers taking part in the project have experience in the characterization, irradiation and operation of silicon pixel detectors and electronics, including data analysis. In addition all the test setup for assemblies already exists, since it has been developed for the FE-I4 characterization within the ATLAS-IBL project. Therefore the evaluation components of WP1, WP3 and WP4 are well covered.

2.6 Risk Assessment

The main risks associated to the project are connected to the fact BCD8 STMicroelectronics technology reveals unsuitable for the realization of sensor, for either technical or commercial reasons, or that the hybridization technique, using AC coupling will not guarantee sufficient reliability and performance. The impact of both these events can me mitigated within the workflow of the project.

Should the BCD8 technology reveal unsuitable (for example a too shallow depletion layer, limited radiation resistance) or become unavailable, we plan to continue the research project with one of the alternative foundries, listed in Table 7, in cooperation with our ATLAS colleagues. In that case the funding allocated for submissions to STMicroelectronics will be used for submissions to these foundries. That may results in a delay of 3-4 months, due to the need of migrating the design to the new technologies. The delay can be reduced at a minimum since we are already in strict cooperative contacts with groups working with these foundries. Notice this risk is reciprocal, if other foundries become unavailable, we hope other collaborators will join our efforts with STMicroelectronics.

If the AC coupling hybridization results unsuitable, we will be able to carry on the rest of the project resorting to standard bump-bonding technologies that are developed by CSN1 and other funding agencies for the LHC upgrades. The design will therefore foresee a connectivity mechanism that can accommodate both solutions. The fall back of bump bonding will results in an extra-cost, due to the need to purchase the process.

2.7 Impact of the Research in View of Horizon 2020

The HVR_CCPD project aims to develop a technology for charged particle detectors that will significantly improve the status of the art.

It falls within the area of “Micro- and Nano-electronics” one of the six strategic Key Enabling Technologies (KETs) envisaged in Horizon 2020 as prioritized areas due to their huge potential for


creating jobs, attracting and promoting talents, developing top research infrastructures, tackling the social challenges of our time and making the EU more competitive on the global stage. The impact of the project concerns the three pillars of Horizon 2020: Excellent science, Industrial leadership and Better society.

2.7.1 Excellent science

The direct application of the project is building a technology suitable for the upgrade of the ATLAS and CMS experiments for the HL-LHC at CERN, the European Laboratory for Particle Physics, which the world leading institute for the research on fundamental particles and their interactions.

The LHC is now the accelerating machine on top of the high-energy frontier. Its operation in 2009-2013 resulted in breakthroughs in human knowledge. The discovery of the Higgs boson, which received the Nobel Prize in physics in 2013, has culminated an almost 50 year long quest for understanding the origin of the fundamental particle masses.

The continuation of fundamental research in this field requires innovative detectors, able to cope with unprecedented charged particle rates and radiation damage. By providing a detector suitable for operation in this environment, the HVR_CCPD project will sustain the excellent science in Europe.

2.7.2 Industrial leadership

The exchange of ideas and experiences between the academic and industrial environments can play a significant role in creating a fertile ground for innovation even in directions unforeseen by the original goals of the cooperation. This project promote this exchange in its two main topics:

• A key feature of the project is the application of the STMicroelectronics BCD8 technology to the construction a new kind of devices.

• The CCPD process for coupling of the active sensor and front-end electronics proposed in the HVR_CCPD program is also an innovative interconnection technology. It may provide an alternative solution for the integration of pairs of semiconductor devices, when DC coupling is not needed.

In both cases the active cooperation between the INFN researchers and their industrial partners will result in new products and an increased know-how.

In addition the possibility to attract students and young researchers on technological challenge will build the professionals that will be needed for maintaining the European industrial leadership.

2.7.3 Better society

Charged particle detectors are found in a large number of applications of social relevance.

The detector proposed in this project is characterized by:

• Low operating voltage;

• High speed;

• Radiation hardness. The first property makes the technology suitable for the construction of portable instruments for medical imaging application, dosimetry and measurement of radiation sources for Environmental


monitoring and Homeland security. Transportability and usability may also be improved by the possibility to integrate some of the readout feature on the same ASIC where the sensor is built.

High speed and radiation hardness allow the use of such detector also in applications like beam monitoring for medical therapy or sensors used in space and in nuclear installations.

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