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Development of HV CMOS sensors for 3D integration. Ivan Peri ć Bonn, CPPM, CERN, Heidelberg. Overview. Collaboration between Bonn, CPPM, CERN, Heidelberg Sensors for particle physics in standard CMOS Merging of two technologies: HV CMOS detectors 3D integrated CMOS - PowerPoint PPT Presentation
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Development of HV CMOS sensors for 3D integration
Ivan PerićBonn, CPPM, CERN, Heidelberg
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Overview
• Collaboration between Bonn, CPPM, CERN, Heidelberg• Sensors for particle physics in standard CMOS• Merging of two technologies:• HV CMOS detectors• 3D integrated CMOS• 3D integrated HV CMOS sensors
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HVCMOS pixel detectors
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors
Potential energy (electrons)/e
p-substrate
NMOS
p-welln-well
- 3.3 V
1.1 V
4
n-well
PMOS
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors
Potential energy (electrons)/ep-substrate
NMOS
n-well
PMOS
- 3.3 V
5
p-well
1.1 V
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors
Potential energy (electrons)/ep-substrate
NMOS
n-well
p-well
PMOS
- 3.3 V
6
1.1 V
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors
High-voltage pixel
Potential energy (electrons)/e
collectedcharge
p-substrate
NMOS
n-well
p-well
particlesPMOS
- 3.3 V
50 V
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors – the structure
• Charge collection occurs by drift. (main part of the signal)• Certain part of the signal collected by diffusion
PMOS NMOS
p-substrate
Depletion zone
Potential energy (e-)
deep n-well
Drift
8
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors – the structure
• Charge collection occurs by drift. (main part of the signal)• Additional charge collection by diffusion
PMOS NMOS
p-substrate
Depletion zone
Potential energy (e-)
deep n-well
Drift
Diffusion
9
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors – the structure
• HVCMOS sensors can be implemented in any CMOS technology that has a deep-n-well surrounding low voltage p-wells. (e.g. GF 130nm.)
• Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies (like AMS HV):
• These technologies (usually) use deeper n-wells and the substrates of higher resistances than the LV CMOS.
PMOS NMOS
p-substrate
Depletion zone
Potential energy (e-)
deep n-well
10
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors – the structure
• Example AMS 350nm AMS HV: Typical reverse bias voltage is 60-100 V and the depleted region depth ~15 m.
• 20 cm substrate resistance -> acceptor density ~ 1015 cm-3.
PMOS NMOS
Depletion zone
100V ~15µm
deep n-well
11
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV-CMOS sensors
• The advantages of the HV CMOS pixel sensors are: • Fast charge collection by diffusion that leads to a high radiation tolerance.• The use of CMOS electronics in pixels, both PMOS and NMOS can be used.• Possibility of thinning: only the surface region of the sensor is relevant for the signal generation.• Compatibility with the existing CMOS technologies.
12
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
• Particle hit
N-well
e-h
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
• Charge collection• Assume: Vsat = 8 x 104 m/s• Tcol = 188 ps
e-
188 ps
15
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
• Voltage drop in the n-well
Cdet
Q/Cdet
188 ps
Q
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
• Amplification
Cdet
Q/Cdet
188 ps 20ns
Q
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Signal-generation and amplification
• Feedback action through Cf• N-well potential restored• The diode amplifies its own signal• Active or “smart” diode
Cdet
Q/Cf
Q
188 ps 20ns
Q
Cf
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric 19
Measurements
0.00 0.02 0.04 0.06 0.08 0.100.0
0.2
0.4
0.6
0.8
1.0
~ nu
mbe
r of s
igna
ls
signal amplitude [V]
RMS Noise 0.5mv (12e) 55Fe 70mV (1660e)
Room temperature
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.160.0
0.2
0.4
0.6
0.8
1.0
~num
ber o
f sig
nals
signal amplitude [V]
RMS Noise, 2.4mv (40e) 55Fe, 100mV (1660e)
Temperature -10CIrradiated with protons to 1015n
eq
55Fe spectrum and RMS noiseNot irradiatedRoom temperature RMS Noise 12 e
55Fe spectrum, RMS noiseIrradiated-10C RMS Noise 40 e
Base line noise (RMS)
55Fe
Base line noise (RMS)
50 x 50 µm pixels, shaping time 300ns
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Technology drawbacks – crosstalk
• Capacitive feedback into the sensor (n-well)• Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune
DAC, SRAM but…• “Active” (clocked) CMOS logic gates and sometimes comparators cause large crosstalk.• Possibility 1: Place the active digital circuits on the chip periphery. OK for large pixels.
• Possibility 2: Using of RO chips, either bump-bonded or capacitive coupling. Used so far.• Possibility 3: 3D integration.
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RO cells
ROC
ROC
ROC
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV CMOS sensors based on 3D integration
Sm
art diode sensorR
eadout chip
Signal charge
21
Wafer bonding TSV
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Tezzaron-GF 3D Process
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• Tezzaron Global Foundries process, offered by Mosis and CMP.
• Two tier process based on Global Foundries 130nm technologies.
• Two wafers (tier 1 and tier 2) are connected face to face with Cu-Cu thermo-compression bonding.
• For this purpose Tezzaron uses the 1µm thick Cu TopMetal to create the “leopard skin” pattern.
• The Super contacts (TSVs) are realized after the transistor processing and before the metallization – via middle process (TSV diameter of 1,2 µm, TSV distance 25 µm).
• The top wafer is thinned to access the super contacts. Back side metal is added for bonding after thinning.
M5 M4 M3 M2 M1
M6
Super- Contact
Bond Interface
2.5µm min
12µm 1.2µm
One tier
5µm
10µm
Bond interface layoutWafer to wafer bonding
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
SDA
3D HVCMOS in Tezzaron-GF Process
23
TSV
Tier
2Ti
er 1
(thin
ned
waf
er)
Back Side Metal
M5M4M3M2M1
M1M2M3M4M5
M5M4M3M2M1
M1M2M3M4M5
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Technology options
24
• For the sensor part three options.• 1) Use the HV technology “BCD lite”.
This technology includes the low-power option and the high-voltage option.
• Substrate resistivity 20 Ω cm. • High voltage n-well available. • 35V reverse bias is achievable, leading
to a depleted layer of about 5 µm. • 5 metal layers• Reticle size : 26 x 30 mm.• The engineering run cost ~ 350k$• Upper tier thinned down.
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Technology options
25
• For the sensor part three options.• 2) Use 130nm LP process. • Lower substrate resistivity (?).• N-well diode breakdown voltage ~ 20V.• Avalanche multiplication process might
be possible.
PSUB
DN
LPWNW
NMOSPMOS
DN
LPWNW
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Avalanche Multiplication
5
6
7
8
9
10
11
0 20 40 60 80Reverse bias [V]
Time over threshold [μs]
• LED – light pulses have been detected.• Signal amplitude has been measured as the time over threshold.• From 60V reverse bias, the time over threshold increases exponentially. (about 2x increase)
Charge multiplication!
26
Measurement done by Ann-Kathrin Perrevoort
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Technology options
27
• For the sensor part three options.• 3) Use 130nm GF process with a high resistivity wafer.• Wafer resistances 500 to 1000 Ω cm might be possible.
PSUB
DN
LPWNW
NMOSPMOS
DN
LPWNW
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
3D HVCMOS – readout architecture
28
• 20um x 20um pixels, expected noise of 15 e• Time resolution of about 20 ns and a power consumption of 1-2 uW/pixel
Address ToT TSComparator
FIFO
Address ToT TS
Address ToT TS
Address ToT TS
RO cell
Pixels
TS
Trigger TSdel
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
3D HVCMOS – results and plans
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• Submission planned for spring 2013. • We have separately tested both components of the detector, the sensor part implemented in
the AMS HV technology and the Tezzaron / GF 3D technology.• Sensor readout chip in Tezzaron/GF 3D process designed by Bonn and CCPM – nice results
will be presented by Theresa Obermann.• HVCMOS in AMS H18 technology stand alone – tests and the readout with FEI4; will be
presented by Daniel Münstermann.• The 3D integration of HVCMOS sensors should be straightforward.
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Summary
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• The HV-CMOS technology allows production of a hybrid detectors in a commercial process without the need for dedicated sensors. In this way we are reducing of costs, time and complexity.
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Thank you
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Additional Slides
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
FETC4
FETC4 – prototype 3D IC• Part of a Multi Purpose Wafer produced at Tezzaron 3D and Chartered 130 nm CMOS (tested
w.r.t. irradition)• Pitches 50 x 166 • Optimized technologies• The 2D tiers are fabricated on the same wafer
Analog tier (14 columns x 61 rows)• Similar circuitry as FE-I4 Injection capacitances, CSA, Discriminator• For standalone testing the analog tier has a shift register implemented• For the vertical connection to the digital tier it has a TSV at the discriminator output
Digital tier (14 columns x 62 rows)• Four pixel region layout• For standalone testing it has a shift register implemented• For the vertical connection to the analog tier it has a TSV at its input
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
FETC4
FETC4 – prototype 3D ICCircuitry of analog tier
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
FETC4
• The depleted layer is relatively small => relatively small signals.
35
Threshold ~2400 e Noise ~94 e
The threshold can be measured by reading out both tiers with the same result The measured threshold and noise dispersions and mean values are within the expectations
THRESHOLD NOISERead analog tier Read digital tier Read analog tier Read digital tier
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Test Chip HV2FEI4
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
HV2FEI4
• Pixel matrix: 60x24 pixels• Pixel size 33 m x 125 m• 21 IO pads at the lower side for CCPD
operation• 40 strip-readout pads (100 m pitch) at
the lower side and 22 IO pads at the upper side for strip-operation
• Pixel contains charge sensitive amplifier, comparator and tune DAC.
Strip pads
IO pads for CCPD operation
IO pads for strip operation
Pixel matrix
4.4m
m
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
CCPD readout
2
3
1
2
3
1
Bias A
Bias B
Bias C
FEI4 Pixels
CCPD Pixels
Signal transmitted capacitively
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Sr-90 signals after 80 MRad
39
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric 40
AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.80.0
0.2
0.4
0.6
0.8
1.0
~n
umbe
r of s
igna
ls
signal amplitude [V]
22Na - 0V bias (0.075V or 1250e) 22Na - 30V bias (0.18V or 3125e) 22Na - 60V bias (0.22V or 3750e) 55Fe - 60V bias (100mV or 1660e) RMS Noise (2.4mV or 40e)
Temperature: - 10CIrradiated with protons to 1015n
eq
Irradiation with protons at KIT (1015 neq/cm2, 300 MRad)
55Fe
22Na
0V -30V-60V
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Publications
• I. Peric, A novel monolithic pixelated particle detector implemented in high-voltage CMOS technology, Nucl. Instrum. Meth. A582 (2007) 876–885.
• I. Peric, A novel monolithic pixel detector implemented in high-voltage CMOS technology, IEEE Nucl. Sci. Symposium Conference Record vol. 2 (2007) 1033–1039.
• I. Peric, Ch. Takacs, Large monolithic particle pixel-detector in high voltage CMOS technology, Nucl. Instrum. Meth. A624 (2010) 504–508.
• I. Peric, Ch. Takacs, J. Behr, P. Fischer, The first beam test of a monolithic particle pixel detector in high-voltage CMOSTechnology, Nucl. Instrum. Meth. A628 (2011) 287–291.
• I. Peric, Ch. Takacs, J. Behr, P. Fischer, Particle pixel detectors in high voltage CMOS technology - new achievements, Nucl. Instrum. Meth. A650 (2011) 158–162.
• I. Peric for HVCMOS Collaboration, Active Pixel Sensors in high voltage CMOS technologies for ATLAS, JINST 7 C08002 (2012).
• I. Peric, Hybrid Pixel Particle Detector Without Bump Interconnection, IEEE Trans. Nucl. Sci. 56 (2009) 519–528.
• I. Peric´, C. Kreidl, P. Fischer, Hybrid pixel detector based on capacitive chip to chip signal-transmission, Nucl. Instrum.Meth. A617 (2010) 576–581.
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AIDA: Advanced interconnections for chip packaging in future detectors, Frascati, 2013, Ivan Peric
Experimental results - overview
HVPixel1 – CMOS in-pixel electronics with hit detectionBinary RO
Pixel size 55x55μmNoise 60e
MIP seed pixel signal 1800 eTime resolution 200ns
CCPD2 -capacitive coupled pixel detectorPixel size 50x50μm
Noise 30-40eTime resolution 300ns
MIP SNR 45-60
PM2 chip - frame mode readoutPixel size 21x21μm
4 PMOS pixel electronics128 on-chip ADCs
Noise: 21e (lab) - 44e (test beam)MIP signal - cluster: 2000e/seed: 1200eTest beam: Detection efficiency >98%
Seed Pixel SNR ~ 27Cluster signal/seed pixel noise ~ 47
Spatial resolution ~ 3 mIrradiations of test pixels
60MRad – MIP SNR 22 at 10C (CCPD1)1015neq MIP SNR 50 at 10C (CCPD2)
Monolithic detector -frame readout
Capacitive coupled hybrid detector
MuPixel – Monolithic pixel sensor for
Mu3e experiment at PSICharge sensitive amplifier in
pixelsHit detection, zero suppression and time measurement at chip
peripheryPixel size: 39x30 μm (test chip)
(80 x 80 μm required later)MIP seed signal 1500e (expected)
Noise: ~40 e (measured)Time resolution < 40ns
Power consumption 7.5µW/pixel
HV2FEI4 chipCCPD for ATLAS pixel detector
Readout with FEI4 chipReduced pixel size: 33x125μmRO type: capacitive and strip like
Noise: ~80e (stand alone test, preliminary)
HPixel - frame mode readoutIn-pixel CMOS electronics with CDS
128 on-chip ADCsPixel size 25x25 μm
Noise:60-100e (preliminary)MIP signal - cluster: 2100e/seed: 1000e
(expected)
SDS - frame mode readoutPixel size 2.5x2.5 μm4 PMOS electronics
Noise: 20e (preliminary)MIP signal (~1000e - estimation)
Monolithic detector – continuous readout
with time measurement
1. Technology 350nm HV – substrate 20 cm uniform
2. Technology 180nm HV – substrate 10 cm uniform
3. Technology 65nm LV – substrate 10 cm/10 m epi43