Radiation Damages to Electronic Components … · Dr. Sven Löchner Radiation Damages to Electronic Components Experiment Electronics 3 Categories of Radiation Effects There are 3

Experiment Electronics

Radiation Damages to Electronic Components

Strahlungsschädigungen an elektronischen Bauteilen

Sven LöchnerGSI Darmstadt

SD Gruppenseminar5. Mai 2011

Dr. Sven Löchner Radiation Damages to Electronic Components 2Experiment Electronics

AgendaAgenda

• Categories of Radiation Effects• Total Ionising Dose

– MOSFET– BJTs

• Displacement Damage• Single Event Effects• Radiation Effects in FPGAs• Charge Coupled Devices – CCDs• CMOS Imaging Sensors - CIS


Categories of Radiation EffectsCategories of Radiation Effects

There are 3 broad classes of effects that may occur on electronic devices after/during exposure to radiation:

1. Total Ionizing Dose (TID) effects2. Displacement Damage (DD) effects3. Single Event Effects (SEE)


Categories of Radiation EffectsCategories of Radiation Effects

TID and DD• degradation is cumulative• long term effect (maybe only

visible after some time) • uniformly affect all devices

• characterized by the maximum parametric drift (end of lifetime)

SEE• occur stochastically at any time• short time response (<ns)

• tiny part of a device is affected(position of ion strike)

• characterized by the rate of occurrence

TID • operation depends

on surface propertiese.g. MOSFET, BJT

DD• rely on conduction in

bulk semiconductorse.g. BJT, solar cells, optocouplers

SEE• rely on conduction in

bulk semiconductorspossible in MOS

and bipolar world


AgendaAgenda


– MOSFET– BJTs



Radiation Damages Radiation Damages -- TIDTID

Total Ionising Dose (TID)Gradual effect during complete lifetime of the MOSFET and

BJT devicesReasons:

– Progressive build-up of trapped charge and defects in insulating layers (gate oxide, lateral isolation, passivation, etc.)

– is responsible for parametric degradation and functional failure• MOSFET (interface traps producing inter-bandgap states)

e.g. threshold voltage shift, increase of leakage current• BJT: e.g. current gain decrease


Radiation Damages Radiation Damages –– TID (MOSFET)TID (MOSFET)Threshold voltage shift

Energy band diagram of a Metal-Oxide-Semiconductor structure with a positive gate

voltage applied

Increase of the sub-threshold current in a NMOS transistor given by a

decrease in the threshold voltage and change of the sub-threshold slope


Radiation Damages Radiation Damages –– TID (MOSFET)TID (MOSFET)

Leakage current (parasitic channel):path between Source and Drain

prevent e.g. switch-off of the transistorchange of circuit behaviour

(operation point, ...)


Annealing mechanisms Annealing mechanisms –– TID (MOSFET)TID (MOSFET)

• Annealing of charge in oxide-traps may start immediately(tunneling or thermal process)

• Interface traps do not anneal at room temperature(require higher temperatures to reestablish broken bonds)


Radiation hardness by technology scalingRadiation hardness by technology scaling

Steps towards a radiation hard layout in CMOS:

• Tox > 10 nm:Delta Vth ~ 1/Tox²

• Tox < 10 nm:Trapped charges in the gateoxide are reduced due to tunneling

Threshold shift after irradiation of 1 Mrad as a function of the gate-oxide thickness

250nm

smaller technology process are more immune against TID

effects (self annealing)


Radiation hardness by design techniquesRadiation hardness by design techniques

Steps towards a radiation hard layout in CMOS:

• Prevent of nMOS leakage currents due to chip irradiation:

– Using enclosed transistors (right)instead of linear transistors (left)

• Disadvantage:– Complex model of transistor

behavior– Larger area consumption– Bigger parasitic capacitances– Small W/L ratios not possible


Radiation Damages Radiation Damages –– TID (BJT)TID (BJT)

Bipolar are not immune from TID (bulk semiconductor properties)• Current gain is one of the most radiation-sensitive parameter• Device-to-device / collector-to-emitter leakage can be the

dominant failure mechanism Sensitivity due to dielectric layers (passivation and isolation)• depends strongly on the device structure itself

(position of oxides with respect to the emitter/base/collector)• quality of thick oxides



e.g. NPN deviceWith irradiation:• Base current (at a given base-emitter voltage) increases• Collector current remains unchanged

Reducing the device gain


Most sensitive area


The base current is the sum of:1. Holes injected from the base into the emitter2. Recombination in the emitter-base depletion region3. Recombination with electrons traversing the neutral

active base

Affected by:non-radiatedionizing dosedisplacement

damage

Schematics of PNP and PNP bipolar transistors



Problems with higher and low dose rates for (many) BJTs:• Degradation is higher at low dose

rates than at high dose rates !!!Phenomenon is known as Enhanced Low Dose Rate Sensitifity (ELDRS)

Strongly complicates the extrapolation of test results to operating conditions

In contrast: for MOS devices effects from low/high dose rates are the same


Radiation Damages Radiation Damages –– ELDRSELDRS

Explanation of ELDRS via space charge modles:

At high dose ratelarge amount of positive charge generatedacts as barrier for holes and hydrogen transport to the interfacereducing the degradation rate


AgendaAgenda


– MOSFET– BJTs



Displacement DamageDisplacement Damage

Displacement damage (DD) is generated • directly by energetic particles (neutrons, protons, electrons, heavy

ions• indirectly by photons through energetic secondary electrons

DD is related to the displacemnet of atoms in the lattice of the irradiated material

Frenkel pairs


Displacement Damage ProcessesDisplacement Damage Processes

Low cross section of neutrons and protons with silicon atomsmajority of DD is generated by so-called Primary Knock-on Atom (PKA)

no permanent damageis created

PKA is energetic enoughto displace Secondary Knock-on Atoms (SKA)


Displacement Damage AnnealingDisplacement Damage Annealing

• Short term annealing processesusually less than an hour

• Long term annealing can go for years

Annealing can be enhanced by:• Temperature• Presence of free carriers•

Time scale of displacement damage formation

after neutron irradiation


Displacement DamageDisplacement Damage

Effects and related defects generated by displacement damage


Displacement Damage Displacement Damage -- SummarySummary

Effects on bipolar devices:

• CMOS technologies are largely immune to DDconduction occurs on a tiny region (close to the chip surface)

• BJTs rely on properties of bulk silicondeeply affected

gain decreases (introduction of recombination centers)


AgendaAgenda


– MOSFET– BJTs



Radiation Damages Radiation Damages -- SEESEE

Single Event Effect (SEE)Generic term for effects that can be triggered in semiconductor

devices by the crossing of ionizing particles.Alpha radiation,Proton / Neutron radiation,Cosmic radiation orHeavy ion radiation

Distinction between two type of effects:Cause of permanent damages (so-called hard errors) Cause temporary malfunctions (so-called soft errors)


Radiation Damage Radiation Damage -- OverviewOverviewRadiation Damage in Microelectronic

Devices

Cumulative Effectsgradual effect during complete

lifetime of device

Single Event Effects

Ionisingtotal ionising dose

primarily depend on absorbed energy

independent of type of radiation

Non-Ionisingdisplacement

depend on energy and momentum transfer of incident particle to lattice atoms

mainly an issue in bipolar transistors or optoelectronic devices

must specified for a certain radiation type

Destructive Effects

Single Event BurnoutSingle Event Dielectric FailureSingle Event Gate Rupture Single Event Latch-upSingle Event Snapback...

Non-Destructive Effects

Single Event UpsetSingle Event TransientSingle Event Disturb...


Radiation Damages Radiation Damages –– SEU / SETSEU / SET

Majority of SEE cases are dedicated to soft errors:

Single Event Upset (SEU)Flip of a “bit” (e.g. FlipFlop cell, Memory cell)

Change the state of a digital circuit

Single Event Transient (SET)Short-term change in signal level in an electronic circuit (glitch)


Charge collectionCharge collection

Cross section of an ASIC Charge collection at the gate


Linear Energy Transfer (LET)Linear Energy Transfer (LET)

Minimum amount of particle energy induced to a semi-conductor device at which a SEE appears is called LETcrit

The unit of LET is typical MeV·cm²/mg (related to Si for MOS)

deQLET

Si

critcrit ⋅⋅

⋅=

ρeV6.3 d - sensitive depth of penetration

ρ - material density (Si: 2.33g/cm3)

Typical values for 0.18µm process technology:d = 0.5 ... 2µmQcrit = 30 ... 60fC

=> LETcrit between 1.5 and 12 MeV·cm²/mg


Triple Redundant DTriple Redundant D--FlipFlopFlipFlopDecrease of the possibility for an SEU in a D-FlipFlop cell

Triple Redundant FlipFlop logic3 standard D-FlipFlop cells1 Majority logic(1 Error detection logic)

But: SEU “hardness” depends on refresh timegood for state machine registers

bad for setup/setting registers

Possible Solution for setup registers:automatic reprogramming

self-triggered triple redundant D-FlipFlop


Dual Interlock Cell (DICE)Dual Interlock Cell (DICE)

DICE (Dual Interlock Cell) memory technologies are (more or less) immune against SEU flips.

Reference: T. Calin, M. Nicolaidis, R. VelazcoUpset Hardened Memory Design for Submicron CMOS TechnologyIEEE Transactions on Nuclear Science, Vol. 43, No. 6, December 1996


AgendaAgenda


– MOSFET– BJTs



Radiation Effects in Radiation Effects in FPGAsFPGAs

Single Event EffectsSingle Event Transients (SETs)

short glitches (~100...200 ps)Single Event Upsets (SEUs)

flipped SRAM cells

>80% of all Upsets affect routing / PIP / MUX etc.LUT-Upsets <10%

Further:User-Flip-Flop UpsetsIO-Buffer UpsetsConfiguration-Interface-Upsets





Mitigating Radiation EffectsSpatial redundancy:

Triple Modular Redundancy (TMR) Double Modular Redundancy (DMR)

Temporal redundancy

Error DetectionParityError Correcting Codes (ECC)

Hamming distance

slides from Heiko Engel


Mitigating Radiation Effects (FPGA)Mitigating Radiation Effects (FPGA)

Correcting FPGA configurationAny redundancy approach will only be able to mitigate a limited number of

upsetsAim: keeping the number of upsets low

FPGA configuration scrubbingVirtex-4 FPGAs allow reconfiguration during runtime without resetting the device

Current implementation (V4-FX20)”Blind Scrubbing”, no ReadbackInitial Configuration: ~80msSingle Reconfiguration: ~60ms

Scrubbing-Frequency: ~16HzLimited by Flash memory: 8 bit data every 90 ns

Realistic future implementation16 bit every 30 ns (~12ms / ~80Hz)



Radiation Tolerance EstimationsRadiation Tolerance Estimations

Preliminaary test resultsOnly ~1/3 of all SEUs actually affect the running designRedundancy implementation can handle at least 1 functional error per

scrubbing cycle3 SEUs per scrubbing cycle (12ms)max. SEU-Rate: 3/12ms = 250/s

Cross section for proton SEUs <5*10-13 cm²/bitSEU-Rate ~6*106 bit

max. flux ~ O(107) protons/(cm²*s)Total Ionizing Dose estimationsOfficial Xilinx results:

Family: Virtex Virtex-II Virtex-II Pro Virtex-4Structure size: 220nm 150nm 130nm 90nmTID [krad]: 100 200 250 300



AgendaAgenda


– MOSFET– BJTs



Charge Coupled Devices Charge Coupled Devices -- CCDCCD

Charge Coupled Devices (CCDs) are:• A matrix of up to several million photosensitive elements (or pixels)• Operate by converting the photo-generated charge to a voltage• Voltage is multiplexed to a small number of output amplifiers

Present available CCDs• Pixel dark current in the range of pico ampere• Charge transfer efficiencies (CTE) in excess of 0.9999995 per

pixel


Charge Coupled Devices Charge Coupled Devices -- CCDCCD

Basic structure• Typically an array of Si-MOS capacitors

built on a p-type epitaxial layer• Potential wells are created by applying

a voltage to one of the gate electrodes• The n-type buried channel ensures that

the potential minimum is situated ~1 µm into the silicon so that charge is kept away from the silicon-silicon dioxide interface.

• Charge is moved from one pixel to another by switching the applied voltage from one electrode phase to the next

• A charge sensitive readout amplifier provides a voltage that can be further processed


Radiation Effects in Radiation Effects in CCDsCCDs

Radiation Effects in CCDs:The performance of CCDs is permanently degraded by • Total ionizing dose (TID) effects

– Threshold voltage shifts on the CCD gatesDegrade output amplifier performance

• Displacement damage effects– Reduces the CTE– Increases the dark current– Produces dark current non-uniformities– Creates random telegraph noise in individual pixels.

Single Event Effects also interfere with the device operation.


AgendaAgenda


– MOSFET– BJTs



CMOS Imaging Sensors CMOS Imaging Sensors -- CISCIS

Deep sub-micrometer (DSM, 250nm and beyond) CMOS processes dedicated to imaging (CIS processes) have brought important technological changes:

• Diodes dedicated to photo-detection with optimized doping profiles(enhance photo-collection)

• Introduction of shallow trench isolations (STI)• Optimized dielectric stack (improve light transmission to pixel)• Anti-reflecting coating• Micro-lenses• Color filters • ...


CIS Pixel Schematic CIS Pixel Schematic –– 3TPD3TPD

Typical three-transistor-active-pixel (3TPD pixel),based on a classical P-N junction


CIS Pixel Schematic CIS Pixel Schematic –– 4TPPD4TPPD

Four-transistor-active-pixel with in pixel charge transfer (4TPPD pixel), based on a fully depleted pinned photodiode


Radiation Effects in CISRadiation Effects in CIS

Radiation Effects in CIS:• Cumulative effects are the main contributor for performance

degradation.• The electrical parameters of a typical standard DSM CIS do not

change much with irradiation below ~100 krad (intrinsic radiation hardness of DSM)

• Total ionizing dose (TID) effects– Threshold voltage shifts– Increase of leakage current

more or less uniform over all pixels• Displacement damage effects

– May decrease the sensitivity for the longest wavelengths– Creating of hot pixels with very high dark values

Non-uniform increasing of dark current


Comparison 3TPD and 4TPPG CISComparison 3TPD and 4TPPG CIS

Comparison 3TPD and 4TPPG CIS:1. Dark current increase distribution following non-ionizing interactions will be

the same in both types of sensors2. Pre-radiation dark current is at least two orders of magnitude lower in

pinned photodiodes (4TPPG) than in 3T pixel photodiodes3. The relative dark current increase due to displacement damage will be 100

times larger in pinned photodiode based sensors (4TPPG)4. High electric field regions are more likely to exist in pinned photodiodes

(4TPPG) than in a well designed 3T pixel photodiode (especially near the transfer gate and the surface). If displacement damages occur in such regions, the resulting dark current can be significantly enhanced.

Displacement damage is expected to be a serious issue for the use of pinned photodiodes in a radiation hard environment.


Questions ?


Thank you for your attention


Additional Additional slidesslides......


GRISU projectGRISU project

Project objectives:Characterisation of UMC 0.18µm CMOS process concerning the

vulnerability against Single Event Effects (SEE), especially Single Event Upsets (SEU) and Single Event Transients (SET)SEU cross section for different Flip-Flop designs and layoutsCharacterisation of the critical charge Qcrit respectively the

Linear Energy Transfer (LETcrit )SET sensitivity of the UMC 0.18µm process

Single Transistor measurementsComparison of transistor models by simulationTotal Ionising Dose (TID)

Characterisation of the UMC 0.18µm process under irradiation, especially leakage currents, threshold shifts, annealing, ...


GRISU test ASICGRISU test ASIC

Test structures for TID

measurements

Test structures for SEU measurements

Test structures for SET measurements, Qcrit

Ring oscillator for TID / SEU measurements

GRISU chipUMC 0.18µm process1.5 x 1.5 mm²64 pads

28 core pads36 pads


SEE Building BlocksSEE Building Blocks

3 different building blocks for SEE characterisation: Test structures for SEU measurements

8 different types of flip-flops implemented, e.g. oversized flip-flops, flop-flops with Dual Interlock Cell (DICE) architecture, ...

Test structures for SET and Qcrit measurementsDifferent inverter chains

=> Qcrit,sim from 20 ... 1000fC2 ring oscillator test structure


•X6 cave at GSI

Low Energy testing siteLow Energy testing site

Installation of a test facility for ASIC irradiation with heavy ions at X6 cave at GSI (in cooperation with bio physics group)

Beam monitoring via ionisation chamber

Dosimeter setup availableIrradiation of DUT in airEasy access

Disadvantages of setupOnly one ion source

during beam time“Fixed” LET range for ion source


SEE Tests at GSISEE Tests at GSISEE test with heavy ions at GSI:X6 experimental site11.4 MeV/u7 irradiation tests so far

C-12 (3x)Ar-40Ni-58Ru-96Xe-132

LET in the range of 1...62 MeV·cm²/mg (SiO2)Q = 8..1300 fC


LET testing rangeLET testing range

Overview of the LET testing range for the applied heavy ions test


CrossCross--sectionsection ((WeibullWeibull--FitFit))

C-12 Ar-40 Ni-58 Ru-96 Xe-132

LETcrit = 1.93 MeV cm²/mgσsat = 1.48·10-8 cm²/bit


CrossCross--section (DF)section (DF)

LET = 4 MeVcm²/mg


TID tests TID tests –– single transistorssingle transistors

Measurements of the transistor characteristics and calculation ofthe threshold voltages for different dose levels (e.g. NMOS 0.24/1.80)

In total 6 chips are irradiatedTotal dose up to 2.5MradDecrease of threshold voltage

~ 20% after 1Mrdno further change

after 1Mrad



Measurements of the transistor characteristics and extraction ofthe leakage current for different dose levels (e.g. NMOS 0.24/1.80)

In total 6 chips are irradiatedTotal dose up to 2.5MradIncrease of leakage current

no significant increase up to200krad

by 3 orders of magnitude after 2.5Mrad



Measurements of the annealing and calculation of the thresholdvoltage for different dose levels (e.g. NMOS 0.24/1.80)

Detailed annealing scans only with one 1 chip

2.5Mrad total doseAnnealing at room temp.Increase of threshold voltage

after 6 weeksstill 10% under pre-radiation

valuebut no saturation reached

(maybe further increase possible)



Measurements of the annealing and extraction of the leakagecurrent for different dose levels (e.g. NMOS 0.24/1.80)

Detailed annealing scans only with one 1 chip

2.5 Mrad total doseAnnealing at room temp. Decrease of leakage current

after 6 weeksalmost back to pre-rad value


SummarySummary

In all cases, designing with radiation in mind is essential.The semiconductor industry's move to decrease device structure sizes,

reduce power requirements and increase speedless sensitive for TID but lead to increased SEE sensitivityradiation-induced device failure could become a majorproblem

At the board level, however, designers have only the following options: mitigation at chip level by using components, which do meet the radiation

requirementmitigation at board level by using design techniques to achieve a radiation-

tolerant board (or, most likely, a combination of both approaches)Designers can add radiation tolerance to their boards by choosing to

use rad-hard componentsRad-hard component qualification does not guarantee that the device is

insensible to radiation


Summary (2)Summary (2)

At least for the future experiments (like Panda, CBM, ...) different investigations in all kind of radiation hard techniques are ongoing to keep the specifications for the high radiation levels

Reduce the number of devices in an radiation hard environment to a necessary minimum

Think about redundancy, failures detection, power monitoring of your devices

By using the right technology, qualified parts and proper design, it should be possible to build the right solution for radiation-sensitive applications of your self-developed equipment

Follow the publications of the different conferences / communities that are working in that field (e.g. NSREC, RADECS, ...)


Total Dose ResultsTotal Dose Results

Beetle showed full functionality beyond 130 Mrad

• full trigger and readout functionality

• full slow control functionality

• performance degradations are small at 10 Mrad:

• peaktime: ≤ 1 nsgain: ≤ 4%

more significant at 130 Mrad:• peaktime: ~ 7 ns

~ 4 ns after annealinggain: ~ 10%

higher after annealing

no tuning of bias settings

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Radiation Damages to Electronic Components … · Dr. Sven Löchner Radiation Damages to Electronic Components Experiment Electronics 3 Categories of Radiation Effects There are 3