Racetrack Memory

CHAPTER 1

INTRODUCTION

Racetrack Memory is an experimental memory device under development at IBM’s

Almaden Research Center under a team lead by Dr. Stuart Parkin. It offers a higher storage

density as compared to the solid-state memory devices with a higher read/write performance.

There are two main means of storing digital information for computing applications: solid-

state random access memories (RAMs) and magnetic hard disk drives (HDDs). Even though

both classes of devices are evolving at a very rapid pace, the cost of storing a single data bit

in an HDD remains approximately 100 times cheaper than that in a solid state RAM.

Although the low cost of HDDs is very attractive, these devices are intrinsically slow, with

typical access time of several milliseconds because of the large mass of the rotating disk.

RAM, on the other hand can be very fast and highly reliable, as in static RAM and dynamic

RAM technologies.

Hard disk drives (HDDs) are data storage devices that allow the storage of "write data" on a

rotating magnetic disk (or similar magnetic recording medium) via operation of a read/write

head positioned over the magnetic recording medium. Upon subsequent demand, stored data

may be retrieved as "read data" from the magnetic recording medium using the read/write

head. Contemporary HDDs are high-density, non-volatile data storage devices, and are

generally implemented using a number of moving mechanical components and related

electromechanical circuits. The increasing demand for denser data storage together with the

relatively delicate nature of the moving mechanical components forming an HDD lead

inexorably to problems associated with deterioration of mobility, accuracy of positioning and

general reliability. Further, manufacturing complexity and corresponding costs, as well as

concerns over power consumption and noise generation have negative competitive

implications for conventional HDDs.

Accordingly, a number of recent development efforts have been directed to replacement data

storage devices capable of providing commensurate data storage capabilities, but without the

entire complex, moving mechanical systems. One possible replacement device commonly

referred to as the "magnetic racetrack memory device" uses a physics principle that

recognizes that magnetic domains and magnetic domain walls move within a magnetic

material (i.e., a magnetic body).

DIVISION OF ELECTRONICS, SOE, CUSAT 1

The architecture of computing systems would be greatly simplified if there were a single

memory storage device with the low cost of the HDD but the high performance and

reliability of solid-state memory. Because both silicon-based microelectronic devices and

HDDs are essentially two-dimensional (2D) arrays of transistors and magnetic bits

respectively, the conventional means of developing cheaper and faster devices relies on

reducing the size of individual memory elements or data storage bits. An alternative

approach is to consider constructing truly 3D devices.

One such approach is “racetrack” memory (RM) [1], in which magnetic domains are used to

store information in tall columns of magnetic material arranged perpendicularly on the

surface of a silicon wafer (Fig. 1). Magnetic domain walls (DWs) [2] are formed at the

boundaries between magnetic domains magnetized in opposite directions (up or down) along

a racetrack (Fig. 2). Each domain has a head (positive or north pole) and a tail (negative or

south pole). Domain walls along the racetrack alternate between head-to-head and tail-to-tail

configurations. DWs (that is, the bit length) are controlled by pinning sites fabricated along

the racetrack. There are several means of creating such pinning sites; for example, by

patterning notches along the edges of the racetrack or modulating the racetrack’s size or

material properties. Besides defining the bit length, pinning sites also give the DWs the

stability to resist external perturbations, such as thermal fluctuations or stray magnetic fields

from nearby racetracks.


CHAPTER 2

CONCEPT OF RACETRACK MEMORY

The fundamental concept of Racetrack Memory (RM) [1] is to store multiple data bits per

access point, rather than the typical single bit per transistor. This is accomplished by storing

data bits in the form of domain walls (DW) in magnetic nanowires where each wall

represents a single bit; which are oriented either parallel to the surface or perpendicular to

the surface of the silicon wafer (Fig. 1).

Fig.1 Concept of Racetrack Memory

By fabricating the nanowires perpendicular (A) on the chip surface the chip area occupied by

each wire area is kept to a minimum and very high data density can potentially be obtained.

However, fabricating such wires is a substantial challenge and a much simpler 2-dimensional

geometry (B) would already be competitive to most solid state memory types.

The racetrack is a ferromagnetic permalloy (Fe20Ni80) nanowire [2] fabricated by electron

beam lithography and a lift-off process on top of Si/SiO2 substrates. Racetrack Memory is

fundamentally a shift register in which the data bits (the DWs) are moved to and fro along

any given racetrack to intersect with individual reading and writing elements integrated with


each racetrack (Fig. 2). These domain walls separate magnetic regions which are magnetized

in opposite directions (which can be parallel or perpendicular to the nanowire’s direction).

Fig. 2 Racetrack memory as a shift register

The DWs are shifted along the nanowires using nanosecond long current pulses via the

transfer of spin angular momentum of the spin polarized current through the wire using the

phenomenon Spin Transfer Torque (STT) [3]. By writing successive bits and pushing them

up in the nanowire and reading domains by pushing back towards a read-head such as a

Tunnelling MagnetoResistance (TMR) sensor [4] we can access data bits.


HOW DOMAIN WALLS CAN BE CREATED?

In a ferromagnetic material, the energy of magnetic structure is the sum of exchange energy,

the anisotropy energy, the Zeeman energy and the demagnetization energy [5]. The magnetic

system seeks to minimize its overall free energy. Since the magnitude of the magnetization

cannot change, the way to minimize the energy is to vary the direction of the magnetization.

The exchange energy seeks to align the spins with each other, the anisotropy energy seeks to

align the spins with an axis determined by the crystal structure, and the Zeeman energy

aligns the spins with an external field. Minimization of these energies will lead to some

compromise that leads to the lowest overall energy direction for the magnetization. When

also the magneto static dipole-dipole interaction is taken into account, known as the

demagnetization energy, a nonuniform magnetization will generally be found as the lowest

compromise of the overall energy.

Short range exchange energy will prevail a configuration with the spins aligned, large range

dipole-dipole interaction will however prevail a magnetic state with minimal net

magnetization. Typically this competition leads to large domains with uniform

magnetization separated by narrow intermediate regions, called the domain walls.

Fig. 3 Kerr image of typical domain formation

Figure 3 shows an optical Kerr image of a typical domain formation in a permalloy thin film

structure [2]. In magnetic nanowires where the thickness and width is so small that the

magnetization can be assumed uniform over the thickness and width, relative simple

calculation of the DW structure is possible. Due to the large demagnetization field induced

by the thin film, rotation of the magnetization in a static domain wall within the plane of the

thin film is favoured, as depicted in Figure.


The structure of domain walls in sufficiently narrow permalloy nanowires are either of

transverse type or vortex type. These walls display two chiralities, clockwise and

anticlockwise; which have equal energies in smooth nanowires.

DOMAIN WALL DYNAMICS

Spin is a fundamental quantum property of electrons. Imagine each electron as a tiny

spinning ball of electric charge, with a magnetic field pointing along the axis of the spin. The

spin axis of an electron in an ambient magnetic field lines up either parallel or antiparallel to

the field. It is said to have either “spin up” or “spin down,” with respect to the local magnetic

field. When electrons travel through a magnetized metal, the spin-up electrons travel more

easily, resulting in a spin-polarized current or spin current—one in which most of the

moving electrons carry a specific spin. In contrast, an ordinary current, such as one travelling

along copper wire, involves electrons whose spins point randomly in all directions.

Permalloy, a strongly magnetic alloy of nickel and iron, can produce as much as 90 percent

spin polarization in a current

SPIN TRANSFER TORQUE

When a current is passed through a ferromagnetic material, electrons polarize; that is, the

spin of the conduction electron will align with the spin of the local electrons carrying the

magnetic moment of the material. When the conduction electrons subsequently enter a

region of opposite magnetization they will eventually become polarized again, thereby

transferring their spin momentum to the local magnetic moment, as required by the law of

conservation of momentum. Therefore, when many electrons are traversing a DW,

magnetization from one side of the DW will be transferred to the other side. Effectively the

electrons are able to push the DW in the direction of the electron flow. This effect is called

the Spin Transfer Torque effect (STT) and was first proposed by Berger [5].

DOMAIN WALL MOTION

The key concept and one of the most challenging aspects of Racetrack is the controlled

movement of DWs along the nanowires by means of current pulses. In permalloy (Fe20Ni80)

Racetrack nanowires with square cross section ranging in thickness from 10 to 20nm and

width from 100 to 500nm, most studies report of a critical current (from 109 to 1012 A/m2)

below which no DW motion is observed. This high current could readily cause structural


damages to the nanowires and DW instabilities. By using current pulses timed in accordance

with the resonance frequency of the DW, it is possible to de-lodge and propagate a DW in

the direction opposite to the electron flow [6].

Domain walls can be propagated with two methods, Field controlled motion and current

controlled motion.

I. FIELD CONTROLLED DW MOTION

In RM, domain wall exists anywhere that a 0 is next to a 1. The customary way to

move domain walls involves applying a magnetic field. The magnetization in each

domain actually comes about because the atoms in the domain have their individual

magnetism aligned. In a sufficiently strong external field aligned with one of the

domains, the antiparallel atoms at the domain wall tend to flip around to line up with

the applied field—and so the position of the wall shifts. This process does not move

the data bits along the nanowire. Consider a 0 sitting between a pair of 1s, with the

applied field pointing in the 1 direction. The two domain walls will move to increase

the size of the 1 domain, eventually wiping out the 0 altogether.

II. CURRENT CONTROLLED DOMAIN WALL MOTION

Spin Transfer Torque [3] method is as follows. Again consider the 1-0-1

arrangement of domains. The electrons flowing through the first 1 domain will be

spin-polarized with their own magnetism aligned in the 1 direction. As each electron

crosses the 1-0 domain wall, its magnetism will tend to flip to the 0 direction. But the

electron’s magnetism is tied to its spin, which is a quantity of angular momentum.

As with energy and ordinary momentum, angular momentum is a conserved

quantity. For the electron to flip from 1 to 0, something else must flip from 0 to 1,

and that something else is an atom just on the 0 side of the domain wall. As the spin-

polarized electrons flow through the domain wall, they move the domain wall along

the nanowire one atom at a time.

Now consider what happens when one of these same electrons arrives at the 0-1

domain and crosses it. The same reasoning shows that it flips from 0 back to 1,

which flips an atom from 1 to 0, again moving the domain wall a tiny amount along

the wire in the direction the electron is flowing. With both its domain walls moving

along the wire in lockstep, the 0 bit itself travels without expanding or shrinking.


NEED OF PINNING SITES

Nanosecond-long pulses of spin-polarized current cause a series of as many as six domain

walls to move in lockstep along magnetic nanowires. The domain walls can move 150

nanometers in a nanosecond, allowing access times of nanoseconds. They could easily drift

out of position if propelled by small stray currents or magnetic fields or because the con-

trolling pulses are not exactly the correct magnitude and duration. This hazard can be averted

by building small notches in the racetrack’s sides, spaced at the intended size of the bits. The

domain walls tend to become pinned at these notches because they will have the smallest

area and thus the least energy hence stable when sitting at a notch.

DATA REPRESENTATION

Fig. 4 Bit representation

The data bits can be represented in terms of the polarity of the domain wall as shown in

figure 4. It can also be assumed in the reverse order.

READING PROCESS

Fig. 5 Domain walls in racetrack


0 1 0 1

The DWs in the magnetic racetrack (Fig.5) can be read with magnetic tunnel junction

magneto resistive sensing devices [7] arranged so that they are in contact with the racetrack.

As the DW’s move near the sensing element, the field induces a change in the resistance of

the read-head according to the polarity of the field. Thus reading can be done (fig.6).

Fig. 6 Magnetoresistance sensor reading a domain wall

The magnetoresistive sensors are based on the magnetoresistive effect. The magnetoresistive

effect is the change of the resistivity of a current carrying ferromagnetic material due to a

magnetic field. GMR [7,8] sensor can be called as magnetically controllable resistors.

The spin-valve magnetoresistive sensor consists of a layer of nonmagnetic metal between

two magnetic layers. The first magnetic layer spin-polarizes the current in a specific

direction. The second magnetic layer changes its magnetism back and forth to match the

field coming from each passing magnetic domain representing a 0 or a 1 on a disk. When the

two magnetic layers of the sensor are parallel, the spin-polarized current flows through

relatively easily. When the layers are antiparallel, the polarized electrons are impeded.

Fig. 7 Magnetization vector in ferromagnetic material


When the current is passed through the ferromagnetic material (Fig.7) the internal

magnetisation vector (M) of the ferromagnetic material is parallel to the current flow. When

an external magnetic field is applied opposite to the direction of the current flow (as shown

in the figure) the internal magnetisation vector changes its position (M1) by an angle. The

change in position is depending on the strength of the magnetic field. The resistance depends

on the angle formed by the internal magnetisation vector (M) of the ferromagnetic material

and the direction of the current (I) flow.

Fig.8 GMR sensor working

Resistance is largest if the current flow and the internal magnetisation vector are parallel.

The resistance in ferromagnetic material is smallest if the angle is 90° between the current

flow and the internal magnetisation vector.

Here in Fig.8, the free layer magnetization changes depending on the state of target bit. This

change is detected as a change in read current since it causes the resistance to vary

accordingly. Normally 4 sensors are connected in a Wheatstone bridge configuration to form

a complete GMR sensor with each resistor arranged to maximize sensitivity and minimize

temperature influences.

In the presence of a magnetic field, the values of the resistors change, causing a bridge

imbalance and generating an output voltage proportional to the magnetic field strength. The

Wheatstone bridge configuration provides reduction of temperature drift and doubles the

signal output.


free layer magnetization changes depending on the state of target bit (this change is detected as a change in read current).

FREE LAYER

ANTI-FERROMAGNETIC LAYER

READ CURRENTTUNNEL OXIDE LAYERFIXED LAYER

WRITING PROCESS

Fig. 9 Writing process

Write process (Fig.9) is done by switching the direction of magnetization by either a

localized external field or by means of STT by passing a current into the wire from a

magnetic nano-element (Fig.10) or by using the fields of domain walls in a proximal

nanowire writing element [9,10].

Fig. 10 Writing field coupling

Nanosecond long current pulses and subsequently the mechanism of STT make the shift of

Domain Walls (DWs) possible (Fig. 2). If a uniform field is applied, the DWs would move

in opposite direction and eventually the data would be lost. This method can be used to wipe

out all the data.


RACETRACK MEMORY CONCEPT USING A FEW FIGURES [9]:

1. In a Racetrack Memory element, the data is stored as a magnetic pattern in a nanowire.

Domain walls are the boundaries in the pattern where the magnetic field reverses polarity.

This is similar to the way data is stored on a magnetic hard disk, except in racetrack there

are no moving parts; instead, we will move just the magnetic pattern of data.

Fig.11a

2. Pulses of spin-polarized electrical current exert force on the domain walls, making them

move along the wire. Because all the electrons in the current have the same spin, all the

walls move the same direction and the entire pattern moves together.

Fig.11b


3. As the domain walls move past the read head, a magnetic tunnel junction sensor is affected

by the magnetic field and detects the bits going by. This is indicated by the needle on the

meter swinging back and forth (see the meter in Figure). The sign of the signal depends on

the polarity of the domain wall.

Fig.11c

4. By applying current in the other direction, the data pattern can be made to move in reverse.

Thus, the data can be read out in either direction.

Fig.11d


5. A Racetrack memory device would consist of many of these nanowires on a chip, each

wire encoding a large number of bits via a single cell on the chip. This corresponds to the

high data density of these wires.

6. Writing is done by sending spin-polarized current through a second nanowire near the first.

The current moves a domain wall past the data pattern wire.

Fig.11e

7. The field from the domain wall in the second wire will re-magnetize the area of the data

wire it passes closest to, writing new data in place of the old.

Fig.11f

8. By controlling the direction of the current pulse and resultant motion of the writing domain

wall, data of either polarity can be written.

Fig.11g


Overall operation:

Fig.11h


FABRICATION OF RACETRACK MEMORY

Fig.12 Horizontal racetrack

Fig. 13 Vertical racetrack

The racetrack memory can be of two types, with horizontal racetrack (Fig.12) and vertical

racetrack (Fig.13). The vertical racetrack offers more storage density than that of the

horizontal racetrack. The horizontal Racetrack Memory likely will require the development

of a process to manufacture nanowires with very smooth edges and surfaces as well as

processes to integrate writing and reading elements in close proximity to the racetracks

themselves. Development of the vertical Racetrack [10] is likely to benefit from techniques

that have been and are continuing to be developed for building three-dimensional

microelectronic devices.


One approach to build the vertical Racetrack Memory is to take advantage of the knowledge

of fabricating vias in silicon (if necessary with a dielectric insulating layer covering the inner

surface of the via), and silicon oxide, and to fill such vias with magnetic metals. Filling of

the vias is readily achieved using electroplating techniques. For example, in arrays of vias,

this can be formed by anodization of aluminium metal. It has been demonstrated that very

long, high aspect ratio vias can readily be filled by electrodeposition. Both magnetic and

non-magnetic metals have been used as well as multilayer of different metals. Clearly the

same techniques are applicable to the deposition of metals in a wide variety of insulating or

poorly conducting template materials.

An advantage of electro-deposition of the magnetic metals to form the vertical Racetrack

Memory is that the same technique lends itself to the formation of trapping or pinning sites

for the domain walls in the Racetrack. This can be carried out by simply changing the

magnetic composition of the magnetic metals as they are deposited into the via.

Other perhaps more radical techniques to fabricate the Racetrack include the preparation of

the nanowires independent of the silicon substrate, such as has been demonstrated, for

example, for the case of electrodeposited very long (~1- 500 microns) and narrow (~15nm)

Mo nanowires, and by vapour-liquid-solid epitaxial growth of semiconducting nanowires.

These nanowires could then be placed on the substrates at appropriate tethering points.


Fig.14 Method of racetrack fabrication

A method for building the vertical Racetrack shown in figure14 is as described. A via is

constructed in a substrate which is formed from a multi-layer laminate composed of two

different alternating dielectric materials. By choosing these dielectric materials to have

different etch rates with the same etchant and then, by using a combination of selective and

non-selective etchants, a via can be constructed which has corrugated sides in the nanometer

scale. When the via is filled by a magnetic material, for example, by electrodeposition, then

the corrugated sides provide the pinning sites for the domain wall memory elements. Other

possible methods to fill the via include the use of a highly directional deposition technique,

or atomic layer deposition.

The integration of magnetoresistive sensing devices for reading data in the racetrack can

readily be accomplished using the techniques developed in recent years to form high quality

deep sub-micron sized magnetic tunnel junction elements.


CHALLENGES AND ISSUES

The proposed design requires a great effort in the research field so as to understand the

complete property variations of the permalloy nanowire in different conditions such as

temperature, current density etc. The basic limitation is in the commercial fabrication itself.

The field of the proximal racetrack may affect the nearby ones. Hence, proper shielding

methods have to be incorporated in the modular design so that it can be launched as a storage

device.

The domain wall dynamics in permalloy nanowire is under study. The prototype is with the

horizontal racetracks. The storage capacity of this mode of RM would be merely comparable

to flash memory, though with significant advantages: the memory would be much faster than

flash, would use less energy and would not wear out. The research group built vertical

racetracks, but they have not yet integrated devices on the same chip for writing and reading

of DW’s.


ADVANTAGES OF RACETRACK MEMORY

Racetrack memory is much faster; the DWs can be moved at a velocity of ~150m/s so that

any DW can be accessed in no more than a few nanoseconds. Average access time of RM

will be 10 to 50ns.

Racetrack memory being a solid-state memory has the potential to be a fast random

access memory that can compete with most of the solid-state memories.

It is non-volatile since the racetrack stores data bits as magnetic domains, hence no ‘boot-

up’ is required compared to the traditional RAM.

The 3D Racetrack Memory will offer the least cost per bit of storage and a high density.

It can replace both HDD and RAM from computer systems and thereby significantly

simplify the overall system architecture.


CONCLUSION

The novel 3 dimensional storage class RACETRACK MEMORY envisioned by Dr. Stuart

Parkin developing at IBM’s research center promises non-volatile high density data storage

medium with a very small access time. The reliability and performance of solid-state RM

will be high above than that of the conventional HDDs. It is highly energy efficient as the

data is stored in magnetic domains as domain walls.


REFERENCES

[1] M. Hayashi, L. Thomas, Y. Bazaliy, C. Rettner, R. Moriya, X. Jiang and S. S. P.

Parkin, “Current-Controlled Magnetic Domain-Wall Nanowire Shift Register”,

Science, vol. 320, pp.209-211, 2008.

[2] M. Hayashi, L. Thomas, Y. Bazaliy, C. Rettner, R. Moriya, X. Jiang and S. S. P.

Parkin, “Influence of current on field-driven domain wall motion in perm alloy

nanowires from time resolved measurements of anisotropic magneto resistance”, Phys.

Rev. Lett., vol. 96, p.197207, 2006.

[3] Wolf, S. A., et al., “Spintronics: A spin-based electronics vision for the future”,

Science, vol. 294, p.1488-1495, 2001.

[4] S. S. P. Parkin, et, al., “Giant tunnelling magnetoresistance at room temperature with

MgO (100) tunnel barriers”, Nature Matter, 3,12, p. 862-867, 2004.

[5] Berger, L., “Low field Magnetoresistance and domain drag in ferromagnets”, J. Appl.

Phys., vol. 49, p. 2156-2161, 1978.

[6] Thomas, L., et al., “Resonant amplification of magnetic domain-wall motion by a train

of current pulses”, Science, vol.315, p.1553-1556, 2007.

[7] Baibich, M. N., et al., “Giant magnetoresistance of (001)Fe/(001)Cr magnetic

superlattices”, Phys., Rev. Lett., 61(21), p.2472-2475, 1988.

[8] Binasch, G., et al., “Enhanced magnetoresistance in layered magnetic structures with

anti-ferromagnetic inter layer exchange”, Phys., Ver., 39(7), p.4828, 1989.

[9] S. S. P. Parkin et al., Proc. IEEE 91, 661, 2003.

[10] S. S. P. Parkin, US Patents 6,834,005, 6,898,132, 6,920,062, 7,031,178B2,

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Racetrack Memory