last updated: 9/10/96
QuickNote #45
VHDL Type ConversionSupport in Quick Works
A major addition to QuickWorks is support for VHDL synthesis. VHDL is apowerful hardware description language that can be used to model a digitalsystem. Standarized by IEEE, VHDL offers designers full design portability acrossdifferent vendor tools and platforms. VHDL, however, is not an easy language tolearn. It is often jokingly referred to as Very Hard Description Language. Themain reason for this is that VHDL is a very strongly typed language. In VHDL,operations can only be performed on objects of the same type, and it is oftenneccessary to convert from one type to another in order to perform anoperation. This QuickNote lists the IEEE standard type conversion functions thatare supported by QuickWorks. Type conversion functions are described on alibrary-by-library bases. These IEEE libraries are included with QuickWorks, andcan be called by using the USE keyword at the beginning of your VHDL design.
1. Std_Logic_1164The following functions are contained in the library std1164.vhd . To use them,place the line USE ieee.std_logic_1164.ALL at the beginning of yourVHDL design. Function Pass Return TO_BIT STD_ULOGIC BIT TO_BITVECTOR STD_LOGIC_VECTOR BIT_VECTOR TO_BITVECTOR STD_ULOGIC_VECTOR BIT_VECTOR TO_STDULOGIC BIT STD_ULOGIC TO_STDLOGICVECTOR BIT_VECTOR) STD_LOGIC_VECTOR TO_STDLOGICVECTOR STD_ULOGIC_VECTOR STD_LOGIC_VECTOR TO_STDULOGICVECTOR BIT_VECTOR STD_ULOGIC_VECTOR TO_STDULOGICVECTOR STD_LOGIC_VECTOR STD_ULOGIC_VECTOR TO_X01 STD_LOGIC_VECTOR STD_LOGIC_VECTOR TO_X01 STD_ULOGIC_VECTOR STD_ULOGIC_VECTOR TO_X01 STD_ULOGIC X01 TO_X01 BIT_VECTOR STD_LOGIC_VECTOR TO_X01 BIT_VECTOR STD_ULOGIC_VECTOR TO_X01 BIT X01 TO_X01Z STD_LOGIC_VECTOR STD_LOGIC_VECTOR TO_X01Z STD_ULOGIC_VECTOR STD_ULOGIC_VECTOR
TO_X01Z STD_ULOGIC X01Z TO_X01Z BIT_VECTOR STD_LOGIC_VECTOR TO_X01Z BIT_VECTOR STD_ULOGIC_VECTOR TO_X01Z BIT X01Z TO_UX01 STD_LOGIC_VECTOR STD_LOGIC_VECTOR TO_UX01 STD_ULOGIC_VECTOR STD_ULOGIC_VECTOR TO_UX01 STD_ULOGIC UX01 TO_UX01 BIT_VECTOR STD_LOGIC_VECTOR TO_UX01 BIT_VECTOR STD_ULOGIC_VECTOR TO_UX01 BIT UX01
2. Std_Logic_ArithThe following functions are contained in the library arith.vhd . To use them,place the line USE ieee.std_logic_arith.ALL at the beginning of yourVHDL design. FUNCTION Pass(arg, size) Return
CONV_INTEGER INTEGER INTEGER CONV_INTEGER UNSIGNED INTEGER CONV_INTEGER SIGNED INTEGER CONV_INTEGER STD_ULOGIC SMALL_INT; CONV_UNSIGNED INTEGER, INTEGER UNSIGNED; CONV_UNSIGNED UNSIGNED, INTEGER UNSIGNED; CONV_UNSIGNED SIGNED, INTEGER UNSIGNED; CONV_UNSIGNED STD_ULOGIC, INTEGER UNSIGNED; CONV_SIGNED INTEGER, INTEGER SIGNED; CONV_SIGNED UNSIGNED, INTEGER SIGNED; CONV_SIGNED SIGNED, INTEGER SIGNED; CONV_SIGNED STD_ULOGIC, INTEGER SIGNED;
CONV_STD_LOGIC_VECTOR INTEGER, INTEGER STD_LOGIC_VECTOR CONV_STD_LOGIC_VECTOR UNSIGNED, INTEGER STD_LOGIC_VECTOR
CONV_STD_LOGIC_VECTOR SIGNED, INTEGER STD_LOGIC_VECTOR CONV_STD_LOGIC_VECTOR STD_ULOGIC, INTEGER STD_LOGIC_VECTOR
EXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;
SXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;
3. Std_Logic_UnsignedThe following function is contained in the library unsigned.vhd . To use it, placethe line USE ieee.std_logic_unsigned.ALL at the beginning of your VHDLdesign.
CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
4. Std_Logic_SignedThe following function is contained in the library signed.vhd . To use it, placethe line USE ieee.std_logic_signed.ALL at the beginning of your VHDLdesign.
CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
5. Example UsageFollowing examples illustrate how to use the above functinos calls:
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;USE ieee.std_logic_unsigned.ALL;
ENTITY example ISPORT ( a : IN std_logic_vector(3 downto 0);
b : OUT integer range 0 to 15 );END example;ARCHITECTURE behav OF example ISSIGNAL ai : std_logic_vector(3 downto 0);SIGNAL bi : integer range 0 to 15;BEGINai
