Quick Start Tutorial for VHDL Homework/Projects One can check the full Xilinx ISE 9 Tutorial at the following link: http://www.xilinx.com/support/techsup/tutorials/tutorials9.htm Reading the documentation may save your time.

Before starting the homework/Project, you will need to create a folder first. Let’s assume that you are taking CMPEN297 class this semester. From the Start menu, click 'My Computer' and create C:\cmpen297 folder and collect all your homework projects in this folder. (I created C:\cur\class\cmpen297 folder.)

Start the ISE Project Navigator.

Under the File pull down menu, select the New Project…

Before typing the Project Name, you MUST specify Project Location. Specify C:\cmpen297 folder that was just created.

Now type the project name. In this case, you will be creating the Homework 5 project and you will be turning in your project as your homework, so you must name the project with your last name. Make the project name as your last name after "hw5_". For example, my project name will be 'hw5_choi'. Keeping this project/folder name convention is important, for you to get full credit of your work. When I name my project hw5_choi, the ISE program will create a sub-folder C:\cmpen297\ hw5_choi and collects all the project files in it. If your last name is longer than 8 characters, use only the first 8 character of your last name.

Select the following properties in the homework 5 project wizard window. These same properties will be used for all of the homework. Family => Spartan3E Top-Level Source Type => HDL Device => XC3S500E Synthesis Tool => XST (VHDL/Verilog) Package => FG320 Simulator => ISE Simulator (VHDL/Verilog) Speed => -4 Preferred Language => VHDL

Click Next on the subsequent window.

Again click Next on the subsequent window.

Check the properties and click Finish on the subsequent window.

You will see the similar ISE project navigator window shown below. Right click the device xc3s500e-4fg320 and select the New Source… option.

Now select the 'VHDL Module' on the left and type the file name. In this case, you will be creating a file with an AND gate. Also, ALL file names must contain your initials in the beginning. For example, my file name with 2-input AND gate circuit will be 'kcAND2' for my first name initial "k" and my last name initial "c" is added to the beginning of the file name. Keeping this file name convention is important, for you to get full credit of your work.

Creating a 2 input AND gate, the inputs are labeled 'a' and 'b'. The output of the AND gate is labeled 'z'. Follow the entries for the New Source Wizard shown below.

Once you see the ISE project navigator window similar to the one below, click on the kcAND2.vhd tab on lower middle left (below the FPGA Design Summary tab).

Scroll down the VHDL editor window using the right side scroll bar.

Type in the VHDL statement for the 2 input AND gate function.

Now scroll back to the top of the VHDL editor window, add necessary comments for the kcAND2.vhd file.

After all the comments are entered, be sure to save the VHDL file. One can save the file by clicking the file save button on the top line of the ISE project navigator window, shown above.

Now click the Sources tab and process Processes tab on the left side of the ISE window. Also click the kcAND2 - Behavioral module in the Sources tab.

Now synthesize the kcAND2.vhd file by double clicking the 'Synthesize - XST' in the Process tab.

Wait for the synthesis to complete. If no error, it will complete and show green check mark, as shown below.

If WARNING occurred, it can be ignored. If any Error occurred, it must be fixed and re-synthesized.

Now the kcAND2 gate can be simulated. Right click the 'kcAND2 - Behavioral' in the Sources tab. And select New Source… option. Select the Test Bench WaveForm and type the file name to test your design with the simulation.

Edit the input signal 'a' and 'b' by clicking on the light blue area.

The AND input signal 'a' and 'b' are shown below.

Now click the 'Sources for:' tab shown below. Select the 'Behavioral Simulation' option.

Select the test bench waveform file 'kcAND2tbw' in the Sources tab with single left click.

Expand the 'Xilinx ISE Simulator' in the Processes tab.

Double click the 'Simulate Behavioral Model'

Now you will see the simulation window pop up, showing only the first 1000ns simulation.

Add more simulation time and simulate more. First, type 10000 for the simulation time. Then click the 'Run for Specified Time' button next to the simulation time.

Then click the 'Zoom to Full View' button.

Check the output signal wave for Z, be sure that the output is correct - proper AND gate function.

Make an observation and check to see if the output signal ‘z’ is correct. Try left click, right click, and other button click to explore the simulation window features and be familiar with the tool. You may print the ISE Simulator output wave. Or capture the Simulator window with Alt-Print Screen key and paste it on a MS Word file.

One can zoom-in to the signal wave to see the AND2 gate delay time. You may use the vertical cursors (blue) and the horizontal scroll bar in the ISE simulation window to navigate to the signal transition points. Be brave and explore many features of the ISE tool.

Zoom - in for view.

The AND2 gate delay is in Pico Second [ps] range, much zooming steps are necessary to see from the Nano Second [ns] simulation time.

One can also measure the AND2 gate input to output delay time.

Using the vertical line cursors, one can measure precise delay time.

One can quit the active simulation as shown below, click X.

Then confirm 'Yes' to quit.

Back to the ISE window, you can now prepare for the homework file for the submission. You need to clean up the files and ZIP them. Click the Project menu.

Select the Cleanup Project File option.

Hw5 is now finished and you may quick ISE.

Now the cmpen297 folder contains cleaned-up hw5_choi sub-folder. One may inspect the content.

All of the files are created through the ISE Project Navigator.

For the homework turn-in, please zip-up the folder.

Turn-in your project, the hw5_choi.zip file through ANGEL.