Quick Start Guide for ADS in Power Electronics - Demo Guide · In power electronics, ADS can solve problems that SPICE alone cannot 2. Layout parasitics cause voltage spikes in high

Keysight TechnologiesQuick Start Guide forADS in Power Electronics

Demo Guide

02 | Keysight | Quick Start Guide for ADS in Power Electronics - Demo Guide

Why Evaluate ADS?

Trends in Switched Mode Power Supplies

The trend in switched-mode power supplies is to use wide band gap devices because these enable a higher switching frequency and higher edge speeds (the “di/dt” of the switched loop). These two in turn enable a smaller, lighter, cheaper power supply because the energy storage capacitors and magnetics can be smaller if you top them off more frequently. The higher edge speeds enable higher efficiency because there’s less heat dissipated when you have lower switching losses because the transistors spend less time in the dissipative cross over region.

Schematic View is No Longer Enough

These high slew rates come with a dark side, in particular the large spike voltage and noise generated by the layout parasitics, particularly inductance, of the PCB layout traces. This phenomenon is often called conductive electromagnetic interference (conductive EMI).

Current loops: Schematic view


When to Worry About Layout Parasitics Inductance?

Rule of Thumb: “If the rise/fall time of the switch loop edges in nanoseconds approaches the quantity on the left (vacuum permeability 1.26 nH/mm times effective switched loop length in mm divided by load resistance in ohms), then layout parasitic will be a concern. We recommend you use ADS to add EM-based model of your PCB traces into your circuit simulation.”

For such a planar loop and with typical circuit values (lloop = 1-10 mm, Rload = 0.1-1.0 ohm), problems begin as the rise time, τ, approaches tens of nanoseconds. The key point here is that ADS has a built in electromagnetic (EM) field solver allows you to extract an EM-based model of the layout parasitics. You can co-simulate regular SPICE-like lumped elements along with the effects of the layout. You can plot the voltage spikes and do "what if..." design space exploration, such as using a ground plane for the return current, to minimize their effects.

(See http://www.keysight.com/find/eesof-how-to-estimate-voltage-spikes)

ADS Offers an EM-Based Model of Layout Parasitics

For example, in the below circuit, the spike voltage in the switch loop gets larger and larger as di/dt gets larger.

Current loops: Layout view

http://www.keysight.com/find/eesof-how-to-estimate-voltage-spikes


How to Evaluate ADS: Three StepsStep 1: Download and install the binaries.Go to http://www.keysight.com/find/eesof-ads-latest-downloads

Step 2: Request a no-charge 45-day evaluation license.Go to http://www.keysight.com/find/eesof-ads-evaluation

http://www.keysight.com/find/eesof-ads-latest-downloads

http://www.keysight.com/find/eesof-ads-evaluation


Step 3: Follow this hands-on demonstrationGo to: http://edadocs.software.keysight.com/display/eesofkcads/Workshop+on+Including+Parasitic+Inductance+Effects+on+DC-DC+Converters and download the archives ADS workspace (as shown below) to the “home folder” that you picked during ADS installation.

Note: If you didn’t receive a knowledge Center login with the demo license, please register now.

http://edadocs.software.keysight.com/display/eesofkcads/Workshop+on+Including+Parasitic+Inductance+Effects+on+DC-DC+Converters

http://edadocs.software.keysight.com/display/eesofkcads/Workshop+on+Including+Parasitic+Inductance+Effects+on+DC-DC+Converters


Starting Advanced Design System

1. Go to Start -> ADS to open Advanced Design System2. Examine, but then close the “Getting Started with ADS” pop-up window.

The ADS “Main” window remains.

3. From the Main window menu bar, select the File -> Unarchive dialog box.


4. Select and open the *.7zads archive you downloaded.

5. Accept and download the settings of the Unarchive Wizard.6. Ignore the “Next” button and just click the “Finish” button to accept all the default

settings.


7. Close the Readme window, leaving the “Main” window open.


We are Going to Model a Switch-Mode DC-DC Converter. Here is a Simplified Version:

We are going to model the IC behaviorally as a simple single-pole, double-throw, break-before-make switch.

Note: The actual IC is LTC3609 from Linear Technology, but we don’t need the full vendor model for the purposes of this guide.


Let’s See the Real Thing

1. Open the “Exercise 3” folder.

2. Open the cell folder “Noise_wLayout.”3. Double click on “schematic” view of the “Noise_wLayout.”


Maximize the Window, and Let’s Take a Quick Tour:

The top-level schematic has a simulation controller.

In this particular case, we are using the time-domain SPICE-like simulator in ADS called “Transient.” It includes a Convolution engine so it is sometimes called “Transient Convolution” or just “TC.”

Note: Transient is just one of many circuit simulators available for ADS.


Components can be modeled behaviorally or using physics-based, vendor-specific “model cards.”


VAR blocks contain expressions evaluated before the simulation runs.

Can be convenient for parameterization, especially for parameter sweeps

ADS also has EQN or Measurement Equation blocks, which are similar to VAR blocks, but contain expressions that are evaluated after the simulation has run. Useful for analysis of simulation results, waveforms etc.

Most Important: The “Look-Alike” Component

The EM field solver in ADS can extract a model of the layout parasitics! Right click on it and select “Push into Hierarchy” from its popup context menu.


Under the hood are details of the EM model.

Click on the layout icon to open the artwork.

The EM model is based on:

1. The actual PCB artwork.


2. The material properties of the stack-up of the tech library that the layout is built from.

Optional: Click the EM cog icon, and click “Yes” to re-build the EM model dataset.

Caution: If you perform this optional step, the EM simulation takes about 20 minutes on a typical PC. This step is optional because we already ran the EM simulation for you and saved the resulting dataset in your workspace.

From the Windows task bar, bring the original schematic back on top.


From the schematic menu bar, select Simulate -> Simulate.

Note: You could also use the F7 hotkey or the cog wheel icon in the tool bar.

After a few seconds, the simulation finishes, and the data display window opens automatically.

Rescale the Y-axis in the baseline ripple plot (in preparation for comparing this “good” design with the “bad” one that we’ll do next).


Next Let’s See the Effect of Layout Parasitics On Ripple…

Parasitic impedance causes more ripple noise.

Let’s show what happens to ripple if we add a parasitic impedance by artificially increasing the trace length between Cout and the output ports to Rload.

Bring the schematic window back on top.

We are going to change the connection points of C_200u (Cout).

How to change the connection points

1. Left click to select the wire. Next, hit the delete key. Remove the other wire connecting C_200u.


2. After clicking the wire icon, left click on the nodes as shown to re-connect the capacitor.

Now re-run the simulation with “bad” connection points. The display dataset window comes into focus again.

Note: Do Y-axis scaling on the new plot as before.


Conclusion and Next Steps

1. In power electronics, ADS can solve problems that SPICE alone cannot2. Layout parasitics cause voltage spikes in high di/dt loops3. ADS incorporates an EM-based model of your PCB traces into the circuits simulation4. “What if…?” design space exploration

This guide has just a small taste! Contact your Keysight EEsof EDA expert for further e-learning material to meet your needs!

http://www.keysight.com/find/eesof-support

http://www.keysight.com/find/eesof-support


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This information is subject to change without notice.© Keysight Technologies, 2017Published in USA, August 15, 20175992-2514ENwww.keysight.com

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Quick Start Guide for ADS in Power Electronics - Demo Guide · In power electronics, ADS can solve problems that SPICE alone cannot 2. Layout parasitics cause voltage spikes in high