UNIT-INUMBER SYSTEMS AND DIGITAL LOGIC FAMILIESPART-A QUESTIONS1. List some advantages of CMOs families (Apr/May-2013,Nov/Dec-2007) 2. Add the hexa decimal numbers: 93 and DE (Apr/May-2013)3. Define fan in and fan out characteristics of digital logic families (AUC MAY 2011) Fan out specifies the number of standard loads that the output of the gate can drive without impairment of its normal operation.

Fan in is the number of inputs connected to the gate without any degradation in the voltage level.4. Why should we take care while using CMOS devices? (AUC DEC 2011)5. When can RTL be used to represent digital system? (Apr/May-2011)6. Which IC family offers (a) low propagation delay, and (b)low power dissipation? (AUC MAY 2010) 7. State the important characteristic of TTL family (AUC DEC 2010) 8. In which type of TTL gate wired ANS logic is possible? (AUC DEC 2010)9. Sketch the circuit diagram of a two input DTL NAND gate?(AUC MAY 2010)10. What is the effect of increasing the supply voltage on the propagation delay of the CMOS gates? (AUC MAY2009)11. Give the Gray code for the binary number (111)2 (AUC MAY2009)12. Subtract the following 01011011-00000101(AUC MAY2009)13. Define noise margin. (AUC MAY 2008)It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output. It is expressed in volts.14. Using 2s complement perform the given subtraction 10011012 1101002 (Nov/Dec-2007) 15. Draw the 2 input CMOS NOR gate(Nov/Dec-2007)16. Convert (100)10 to Gray Code. (Nov/Dec-2007)17. What is the drawback of parity method? (Nov/Dec-2007)18. Which is faster TTL or ECL? Which require more power to operate? (AUC DEC 2007)19. Give any two application of open collector Logic. (AUC MAY2007)20. Why does the propagation delay occur in logic circuits? (AUC DEC 2006)A propagation delay is the time required to change the output after application of the input

PART-B QUESTIONS1. (i) Explain the detail about TTL with open collector output configuration (8) (Nov/Dec-2013)(ii) Demonstrate the CMOS logic circuit configuration and characteristics in details (8) 2. Explain the basic working principle of TTL and ECL logic families (8) (Apr/May-2013)3. (i)Draw and explain the NOR gate using TTL logic (8) (Nov/Dec-2011)(ii)Explain the characteristics of CMOS(8)4. Write a note on digital logic families(9) (AUC MAY 2011) 5. Design Rom for the following function F1 = (1,2,3); F2 = (0,2 ) . (AUC MAY 2011) 6. Explain the characteristics of CMOS.(6) (AUC DEC 2011) 7. Discuss about the programmable logic devices.(10) (AUC DEC 2011) 8. Write briefly about the programmable logic array and EPROM. (8) (AUC DEC 2011) 9. Draw and explain the NOR gate using TTL logic. (AUC DEC 2011)10. Discuss on the concept, operation and characteristics of CMOS technology. (8) (AUC DEC 2010)11. Explain the concept, working and characteristics of TTL logic families. (8) (AUC DEC 2010)12. Compare all the IC logic families based on (Apr/May-2010)(i) Power consumption(ii) Fan out(iii) Power dissipation(iv) Propagation delay(v) Switching speed(vi) Noise margin 13. (i)Draw the circuit diagram and explain the working of TTL inverter with tristate output.(8) 14. (ii) Explain the concept and implementation of ECL logic family. (8) (AUC MAY2009)15. i)Explain the working of two input TTL totem pole NAND gate circuit (8) ii) Explain the working of two input CMOS NAND gate circuit. (8) (AUC MAY 2008)16. Write notes on : TTL,ECL and CMOS digital logic families. (AUC DEC 2007, Nov/Dec-2007))17. Explain the characteristics and implementation of the following digital logic families.i) TTL (8) ii) CMOS (8) (AUC MAY2007)18. Draw the 2 input NAND gate using shottky TTL logic and explain its operation. (16) (Nov/Dec-2007)19. Write a short note on the following(Nov/Dec-2007)(i) Self complementing codes(ii) Error detecting codes(iii) Hamming codes20. Draw the circuit of a two input TTL NOR gate and explain its action, clearly indicating logic and voltage level.(Nov/Dec-2007)21. Perform the following code conversion

UNIT-IICOMBINATIONAL CIRCUITSPART-A QUESTIONS1. List the names of universal gates. (AUC DEC 2013)1. NAND gate 2. NOR gate 2. Define multiplexer(AUC MAY 2013)Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line. 3. Construct OR gate using only NAND gate?(AUC MAY 2013)4. What is priority encoder?(AUC MAY 2012)A priority encoder is an encoder circuit that includes the priority function. The operation of priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. 5. Express the following switching circuit in binal7 logic notation. (AUC MAY 2012)

6. Why is MUX called as data selector (AUC MAY 2011) 7. How does dont care condition in k -map help for circuit simplification? (AUC DEC 2011)In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X ord in the truth tables and are called dont care conditions or incompletely specified functions. 8. What is the difference between decoder and demultiplexer? (AUC DEC 2011)Decoderdemultiplexer

A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n bit coded information has unused combinations, he decoder may have fewer than 2n outputsA multiplexer is combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected.

9. State DeMorgan's theorem (AUC MAY 2011)De Morgan suggested two theorems that form important part of Boolean algebra. They are,1) The complement of a product is equal to the sum of the complements.(AB)' = A' + B'2) The complement of a sum term is equal to the product of the complements.(A + B)' = A'B'

10. Show that (AUC MAY 2010)(i) (ii) 11. Draw the Truth table and logic circuit of half adder. (AUC MAY 2010) 12. Show that Excess-3 code is self complementing. (AUC DEC 2010) 13. Simplify (AUC DEC 2009)14. Implement half adder using Gates. (AUC DEC 2009) 15. What is the difference between half adder and full adder? (AUC DEC 2009)16. What will be the maximum number of outputs for a decoder with a 6 bit data word? (AUC MAY2009)17. Why digital circuits are mostly constructed with NAND and NOR gates than with AND and OR gates? (AUC MAY2009)18. State the associate law of Boolean algebra. (AUC MAY 2008) The associative property of Boolean algebra states that the ORing of several variables results in the same regardless of the grouping of the variables. The associative property is stated as follows:A+ (B+C) = (A+B) +C

19. Draw a 2 to 1 MUX using basic gates. (AUC MAY 2008)20. What is variable mapping? (AUC MAY 2007) 21. Using k-map find minimum SOP for the function (AUC MAY 2007) 22. Name the two canonical forms for Boolean algebra. (AUC MAY 2007) a) Sum of productsb) Product of sum23. Mention the difference between DMUX and MUX. (AUC MAY 2007)24. Draw a 4X16 decoder using two 3X8 decoders. (AUC MAY 2007) 25. Implement the given function in 4:1 MUX (AUC MAY 2007)26. Expand the function to standard SOP form. (AUC MAY 2007)27. What is meant by non weighted code?28. Using Boolean Algebra prove

29. Implement the function using 8:1 multiplexer 30. Design a half subtractor using 2 to 4 decoder31. Why NAND and NOR gate are called as universal gates?32. Minimize by K-map method?33. Draw the block diagram of 41 multiplexer and give its truth table.

PART-B QUESTIONS1. Express the function in (Nov/Dec-2013)(i) Canonical SOP form and (ii) Canonical POS form2. Design BCD to Excess 3 code conversion (Apr/May 2010)3. Simplify using K-map 4. Design a full subtractor using half subtractor (Apr/May-2013)5. Prove that is exclusive OR operation and its equals = 6. Prove that for constructing XOR from NAND gates where need four NAND gates7. Simplify the Boolean function using K-maps Which has the dont care conditions 8. Implement the given function using multiplexer 9. Implement the full subtractor using demultiplexer (Apr/May-2012)10. Implement the following Boolean function with NAND-NAND gate logic

11. Simplify and implement the following SOP function using NOR gates

12. Write brief notes on the following (Nov/Dec-2011)(i) DeMorgans theorem(ii) Comparator(iii) Binary to Gray code converter(iv) Multiplexer13. Given the simplified expression for the following logic equation where d represented dont care condition

Represent the simplified expression using logic gates14. Reduce the given expression using Boolean algebra(Apr/May-2011)(i) (ii) (iii) 15. For the given circuit derive the algebraic expression in SOP form

16. Reduce the following expression using K-maps 17. Implement a full adder circuit with (i) decoder (ii) multiplexer18. Solve (Apr/May-2010)19. design a decimal adder to add two decimal digits20. Simplify using K-maps 21. Design a 4 bit binary to excess 3 converter using the unused combinations of the code as dont care conditions, represent the converter using logic diagram.22. Simplify the following Boolean expression using three variable maps (Apr/May-2009)(i) (ii) (iii) 23. For the given function (Nov/Dec-2007)

List all prime implicants and find the minimum product of sum expression24. Design a 4:1 multiplexer using transmission gates and explain its operation25. Using K-map method simplify to the following Boolean expression and implement the same using only NAND gates represented the same expression using product of sum.

26. Explain how full adder can be designed using 2 half adder and a OR gate.27. With the help of a block diagram explain the operation of 38 decoder. Explain how it can be converted into demultiplexer. 28. For the given function

Find the minimum sum of products expression using Quine-McCluskey method.29. Using Quine-McCluskey method find all the prime implecants for the given function and find the minimum sum of product function

30. Obtain the minimum SOP using Quine McCluskys method and verify using K-maps

31. Reduce the following by using tabulation method and verify by using K-maps

32. Obtain the minimum SOP using Quine McCluskys method and verify using K-maps for the following

UNIT-IIISYNCHRONOUS SEQUENTIAL CIRCUITSPART-A QUESTIONS1. What is meant by transition table? (AUC DEC 2013)2. Differentiate sequential circuits and combinational circuits (AUC DEC 2013)3. Draw the truth table for JK flip flop. (AUC MAY 2013)4. How many flip flop are required to design Mod25 counter. (AUC MAY 2013)5. Give the characteristic equation and state diagram of JK flip-flop. (AUC MAY 2012) 6. What is lockout? How it is avoided? (AUC MAY 2012)7. Write the excitation table for JK flip-flop. (AUC MAY 2011) 8. Write the characteristics table for SR flip-flop. (AUC MAY 2011) 9. What is race around condition in Flip-flops? (AUC DEC 2011) 10. How does the state transition diagram of a Moore model differ from Mealy model? (AUC DEC 2011)11. How flip flop differ from latch? (AUC MAY 2010)12. Give the characteristics equation and state diagram of JK flip flop. (AUC MAY 2010)13. What is self starting counter? (AUC DEC 2010)14. Draw the circuit of SR Flip flop. (AUC MAY 2010)15. What are synchronous sequential circuits? (AUC MAY 2010) 16. Convert JK flip-flop to T-flip-flop. (AUC DEC 2010) 17. Mention the major application of Master Slave FF (AUC DEC 2010)18. Give the excitation table of JK flip flop and D flip flop. (AUC MAY 2009, Nov/Dec 2007) 19. How can the race condition be avoided in flip flop (AUC MAY2009) 20. What is a state? (AUC MAY2009) 21. Why is state reduction necessary? (AUC MAY2009)22. How many flip flops are required to design a mod-15 counter. (AUC MAY 2008) 23. Define a sequential logic circuit. Give an example. (AUC MAY 2008)24. Give the state diagram of JK flip flop. (AUC MAY2007) 25. Convert JK flip flop to D flip flop. (AUC MAY2007) 26. What is edge triggering? (AUC MAY2007) 27. Draw the logic diagram of Master Slave JK flip/Flop. (AUC MAY2007) 28. Obtain the excitation table of D and JK flip/flop. (AUC MAY2007)29. What are the advantages of JK flip flop over SR flip flop.30. How many flip flop are required to design Mod50 counter 31. Differentiate between flip flop and latch. (AUC MAY 2005) 32. Why a serial counter is referred to as asynchronous? (AUC MAY 2005)PART-B QUESTIONS1. A sequential circuit has two JK flip flop A and B the flip flop input functions are

i) Draw the logic diagram of the circuitii) Tabulate the state tableiii) Draw the state diagram2. Using JK flip flop design a synchronous counter which counts in the sequence 000, 001, 011, 100, 101, 110, 111, 0003. Design a 3 bit binary counter using T flip flop4. Construct the reduced the state diagram for the following state diagram.

5. A sequential circuit with 2D FFs A and B and input X and output Y is specified by the following next state and output equations

i) Draw the logical diagram of the circuitii) Derive the state tableiii) Derive the state diagram6. I) Realize SR flip-flop using NOR gates and explain its operation. (8)II) Convert a SR flip-flop into JK flip-flop 7. Draw the state transition diagram of a sequence detector circuit that detects 1010 from input data stream using Moore model Mealy model.8. Design a counter using JK flip-flop for realizing the following sequence.

9. Design BCD counter using T flip flop, where flip flop input are 10. Draw the state diagram. Derive the state equation and draw the clocked sequential circuit for the following state table

11. Design a synchronous sequential circuit using JK for the given state diagram

12. Design a BCD counter using t flip flop13. Design a counter with the sequence 0, 1, 3, 7, 6, 4, 0.14. The following sequence is to be realized by a counter consisting of 3 JKFFs. A1 0 0 0 0 1 1 0, A2 0 1 1 0 0 1 0, A3 0 1 0 1 1 0 0, Design the counter.15. Design a synchronous counter using JK flip flop to count the following Sequence 0,1,3,2,6,7,5,4,12,13,15,14,10,11,9,8,0,1,3.16. Design a sequential circuit with the four flip flops A,B,C,D. the next states of B,C and D are equal to the present state of A,B and C respectively. The next state of A is equal to the EX-OR of the present states of C and D.17. Design and implement a synchronous decade counter. Explain its working.18. a) Realize D and T flip flop using JK flip flops (8) b) Write the excitation table for SR, JK, D and T flip flops. (8)19. Design a mod-6 counter using FFS. Draw the state transition diagram of the same20. i) Differentiate between synchronous and asynchronous circuits. ii) Design a mod 5 synchronous counter using JK flip flop.21. For the state diagram shown, design a sequential circuit using JK flip flop

UNIT-IVASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC DEVICES PART-A QUESTIONS1. Define flow table in asynchronous sequential circuit2. How does the operation of an asynchronous input differ from that of a synchronous input?3. What is fundamental mode of operation in asynchronous sequential circuits?4. What are hazards in asynchronous sequential circuits?5. What is the difference between synchronous and asynchronous sequential circuits6. State the hazard in synchronous sequential circuits7. Define asynchronous sequential machine8. Draw the state diagram of SR FF9. What is a self starting counter?10. Give the characteristic equation and state diagram of JK flip flop.11. What are the assumptions that must be made for fundamental mode circuit?12. What is a hazard in combinational circuits?13. What are the assumptions that must be made for pulse mode circuit?14. What are the two types of asynchronous circuits?15. What is meant by non-critical race?16. Describe how to detect and eliminate hazards from an asynchronous network.17. Mention any one advantage and disadvantage of asynchronous sequential circuits?18. Define static 0 hazard and static 1 hazard and dynamic hazard19. What is meant by critical race?20. Distinguish between fundamental mode and pulse mode operation of asynchronous sequential circuits21. How will you minimize the number of rows in the primitive state table of an incompletely specified sequential machine22. What is meant by Race23. What makes PAL is differ from PLA?24. Define a memory location and a cell.25. What is FPLA?26. What is volatile memory? Give an Example27. Design a 2 bit up counter using PROM28. What is a PLA?29. How does the architecture of a PLA different from a PROM30. What is the advantage of PLA over ROM31. Name the types of ROM.32. What is FPGA33. List the configurable elements in the FPGA architecture

PART-B QUESTIONS1. Illustrate the analysis procedure of asynchronous sequential circuit with an example2. List and explain the steps used for analyzing an asynchronous sequential circuit3. Design a asynchronous BCD counter4. Derive the transition table and primitive flow table for the functional mode asynchronous sequential circuit shown in figure

5. Discuss the different types of HAZARDS that occurs in asynchronous sequential circuits6. Write a short notes on (i) Race for assignment(ii) pulse mode circuit7. List and explain the steps used for analyzing an asynchronous sequential circuit8. How do you get output specifications from a flow table in asynchronous sequential circuit operating in fundamental mode?9. Describe procedure to get state table from excitation table in an asynchronous sequential circuit. How does it differ from synchronous sequential circuit10. Reduce the number of states in the following state table

11. Design an asynchronous sequential logic circuit for the state transition diagram shown in Fig.

12. Derive the flow table for the circuit given in the figure

13. Design a pulse mode circuit with inputs x1, x2, x3 and output Z as shown in figure

14. i)Draw and explain the state transition diagram of modulo-6 counter in asynchronous sequential logic.(12) ii) When does oscillation occur in an asynchronous sequential logic circuit?(4)15. (i) A combinational logic circuit is defined by the following function. f1(a,b,c) = (O, 1, 6, 7), f2(a, b, e) = (2, 3, 5,7)Implement the circuit with a PAL having three inputs, product terms and two outputs. (ii) Describe the concept and working of FPGA.16. Write notes on ROM and its types17. Write briefly about the programmable logic array and EPROM.18. Discuss about the programmable logic devices19. Design Rom for the following function F1 = (1,2,3); F2 = (0,2 )20. Implement the following two Boolean function with a PLA F1(A,B,C) =(0,1,2,4), F2(A,B,C) = (0,5,6,7).21. Describe the characteristic of all type of memories22. Implement the following two Boolean function with a PLA F1(A,B,C) =(0,1,2,4), F2(A,B,C) = (0,5,6,7)23. Describe the working of EPROM. List the applications of EPROM24. Design a combinatorial circuit using ROM. The circuit accepts 3-bit number and generates an output binary number equal to square of input number25. Write notes on: 1.EPROM 2. PLD3. PGA26. Implement the given function using PAL and PLA F1=m(0,1,2,4,6,7),F2=m(1,3,5,7), F3=m(0,2,3,6)27. Describe the concept, working and application of the following memories. i) PLD (6) ii) FPGA (5) iii) EPROM (5)

UNIT-IIIVHDL- VHSIC Hardware Description LanguagePART-A QUESTIONS1. What is the function of wait statement in VHDL package?2. Write the explanation of T Base and T Low predefined attributes?3. Write HDL behavior model of D flip-flop4. What is need for VHDL5. What are the various modeling techniques in VHDL6. Write HDL for half adder7. What is the meaning of the following RTL statement?

8. What are the operators presents in VHDL9. When can RTL be used to represent digital systems?10. What are ASM?11. List the operator available in VHDL12. Write the VHDL code for AND gate13. Write HDL for half adder

PART-B QUESTIONS1. Write a VHDL program and explain the design procedure of 8 bit comparator2. Explain the standard VHDL description for 2 to 4 decoder in details3. i) write HDL for two to one line multiplexer with data flow description and behavioral descriptionii) write the VHDL for four bit adder4. Write VHDL for four bit binary counter with parallel load and explain5. i) write the VHDL code for a full adder using equationii) Write the VHDL code for a 4 bit full adder using the module defined in (a) as a component6. Write VHDL code to model JK flip-flop i) Use conditional assignment statementii) Use the characteristics equation7. i) Write an HDL behavioral description of JK flip-flop using if-else statement based on the value of present state.ii) Draw the logical diagram for the following module8. i) Explain the design procedure of RTL using VHDL ii) Write a note on VHDL test benches9. Write a VHDL code for mod 6 counter10. Describe the RTL in VHDL11. Explain in detail the design procedure for register transfer language12. Explain RTL design using VHDL with the help of example13. Construct a VHDL model listing for a 16: 1 MUX that is based on the assignment use a 4 bit select word SS3 S2 S1 S0 to map the selected input to the output