PT module design and readout

Work in Progress

The concept does not have to be fully accurate but a concrete picture is needed to expose the major issues and allows to propose solutions which can

be evaluated quantitatively

Geoff Hall

Overall layout [Mark P]

• Assume stacked layer at R ≈ 25 cm– Tilted to minimise cluster size

• large clusters from grazing incidence– need to simulate low pT tracks

– efficiency bias for oppositely charged low pT tracks?

relevant if full readout for tracking is used?

Feb 2009 G Hall 2

R = 25cmthickness = 285µm

R [cm] pT_graze [MeV/c]

10 60

25 150

35 210

50 300

100 600

Occupancy estimates

• Scenarios for sLHC and vLHC W Scandale & F Zimmerman– Nuclear Physics B (Proc. Suppl.) 177–178 (2008) 207–211

• 40MHz, peak luminosity 1.55x1035 – <294 interactions/bx>– PYTHIA & total inelastic(pp) = 79mb -> <306 interactions/bx>

• Then geometry dependent– R = 25cm ||=2.5, untilted sensors, 100um x 2.5mm pixels – average occupancy over layer is 0.45% ± 17%[3 Poisson variation],

• cross section uncertainty = ±30%[Tomalin], low pt track uncertainty = ±12%[Tomalin], cluster width uncertainty = ±50%[simulation] => (0.45 ± 0.3)% occupancy.

– Other factors include fluctuations in jets – being studied

Feb 2009 G Hall 3

PT layer pixel size

• Should reduce need to compare many nearby columns– independent of , but offset in z between layers increases with

• R-compare to assembly precision ~ 100µm

Feb 2009 G Hall 4

d

R

Luminous region L

∆

R = 25cm, L =28cm d = 2mm ∆ ≈ 2 mm

d

R

L

∆

’

∆ = dL/R

LHC luminous region L ≈ 28cm (±3) – may be larger or smaller at SLHC

Schematic PT module

Feb 2009 G Hall 5

Inexpensive prototyping, using wire bonding, might be possible- experimental demonstration will be important

2 x 2.5mm

12.8mm104 x 2

Data out

128 x100µmx 2x2.5mm

Correlator

data

R = 25cm Occupancy ~ 0.5% at 40MHz & 1035

-This is believed to be worst case

PT layer readout

• Bring data for comparison with second layer, using minimum power– high speed shift register? 128/25ns = 5.12Gb/s

• try to exploit low occupancy?• address hit channels?

– 128 = 7 bits – and should handle some multiple hits

• high PT candidates should be narrow clusters– ignore clusters of 3 or more strips– likely to be only one candidate group per 128 channel

even in congested environment

Feb 2009 G Hall 6

column of 128 pixels

Possible schematic

• divide column into 32 x 4 channel groups– eg logic sets 9 address lines: – 5 bit group + 4 bit pattern +1 bit spare– provide more information than single channel address– ignore combinations consistent with wide clusters

• a moderate number of address lines could be sufficient– still plenty of space for power, clock, I2C, …

• probably share some in 256 channel chip

– Nearest neighbour logic to avoid group boundaries• including (upper) chip edge

Feb 2009 G Hall 7

column of 128 pixels

Some details

• Valid 4 bit patterns– 0001 0010 0100 1000 … 0011 0110 1100 …– 1011 1101 = double cluster

• Invalid– 0000 1111 1110 0111

• Although infrequent, there will be adjacent groups – nearest neighbour logic to merge– eg is an invalid cluster

• Could also increase address lines to cope– eg 110 groups of 8 channel groups => 12 bits– cf 32 groups of 4 channels => 10 bits

• Optimise design using MC– eg 256 elements, longer groups, and to avoid bias

Feb 2009 G Hall 8

column of 128 pixels

0001 1100

More details

• At central boundary need data from ROC-L & ROC-R– extra level of bonding?

Feb 2009 G Hall 9

ROC-L ROC-R

ROC-L ROC-R

Simplest solution: If a valid pattern with hit in [pixel:127]pass all data from last pixel, even if match not founduse spare bit as indicator that no matching comparison

extra data volume, for rejection factor 20 (1 + 127*0.05)/(128*0.05) ≈ 1.15

[pixel:127] [pixel:0]

Data rate for PT module

Feb 2009 G Hall 10

2 x 2.5mm

12.8mm104 x 2

Data out

128 x100µmx 2x2.5mm

Correlator

data

Module 25.6mm x 80mm256 x 32 sub-units = 8192 channels

Occupancy ~ 0.5% => 40 hit channelsPT reduction ≈ 20 [Mark P] => 2 hit channels/BX ≈ 32 bits, with column address

ROC

Feb 2009 G Hall 11

RO

C-1

: 12

8 ch

an

RO

C-2

: 12

8 ch

an

Height: 128 x 100µm = 12.8mm +…Width: 2 x 1.5mm = 3mm + Space for bond pads, etc….

Dense bonds on module : 8192 channels Optimised pitch size?

Max chip size in 130nm: 19.5mm x 21mm

Functions: amplifier, threshold adjustment, comparator, latch, neighbour logic, connect to bus, internal test?

Questionscould assembly be done using inexpensive bump bonding?eg C4 layout with 200µm spacing should be possible

Power transmission over long, narrow chip?

Module - plan view of section

Feb 2009 G Hall 12

assembler 10 bits from column above transmits column to each neighbour receives 10 inputs from each neighbour and stores receives 10 inputs from module below

compares pattern from module below with three (10 bit) stored patterns

x10 x10

x10 x10

column128 channels

interconnectchip

lower layer

store +

(memory buffer for full readout)

10 bit bus

upper layer

10 bit bus

x10

x10

x10

x10

x10

x10

x10

x10 x10assembler

multi-via

column128 channels

x10

Module - section view in r- plane

Feb 2009 G Hall 13

Interconnect chipmass produced, cheapcoarse pitch ~250µm~2.5mm x 2.5mm

Maybe an easier method?

sensor

ROC assembler

store

PCB

PCB

ROC

2mm

Sensor & ROC ~ 200µm thick

Very small component, with regular spacing -…

Possible connectors

Feb 2009 G Hall 14

Fine Stack.40 mm Pitch Plug & Receptacle Number of Positions = 80 (also 20,24,46,50,60)Overall length = 18.4mmBoard-Board Stack Height = 1.0mm (X)In-Line Contact Layout

X

O Zorba

Fine Stack socket

Feb 2009 G Hall 15

More speculative

• Elastomeric connectors

Feb 2009 G Hall 16

Lifetime, aging, precision, reliability?

… become more cost-effective atboard separations of about 0.200” (5 mm) or less and pad pitches below 0.050” (1.27 mm).

Module - section view in r- plane

Feb 2009 G Hall 17

sensor

ROC assembler

store

PCB

PCB

ROC

2mm

Sensor & ROC ~ 200µm thick lateral connections via PCB layers and wire bonds

2.2mm

Questions:what is achievable precision? could all connections be made simultaneously?what accuracy vertical spacing is required? thermal stress

Adapt module for bump bonding - r- plane

Feb 2009 G Hall 18

sensor

An alternative variant with one layer inverted allows to avoid connectors but at the price of having doubled sided modules and possible assembly and handling questions.

How difficult will it be to align?For all designs, what is the best cooling method? Pipes at module edge may be sufficient NB expect to remove material from “picture frame” under sensor

ROC assembler PCB

2mm

ROC store PCB

wire bonding should be sufficient but could use silicon interconnect bridge to connect ROCs laterally

ROC (2)

Feb 2009G Hall 19

RO

C-1

: 12

8 ch

an

RO

C-2

: 12

8 ch

anHeight: 128 x 100µm = 12.8mm +…Width: 2 x 1.5mm = 3mm +

Space for bond pads, etc….Dense bonds on module : 8192 channels

Optimised pitch & pixel size?

Max chip size in 130nm: 19.5mm x 21mm

Would be natural to make assembler part of ROCand, if possible, aim for identical chip for top and bottom layer

Height = 5mm ? => 18 mm x 6mm

Assembler

Logic3 x 10 bit storage1 x 10 bit from paired layer

* Comparison logic – with compensation for r- offset (switch off for lower layer)

* Time stamp & pattern buffer for 256 latency (if needed) – > 50% empty for O ≈ 0.5%

* Output 10 bit column to/from paired layer (switch off for lower layer)* Output pattern & address if coincidence* Need to receive/transmit clock

Dimensions from pad layout

Assembler• Identical chip for top and bottom layer possible?

Feb 2009 G Hall 20

10 x 200µm

10 x 200µm

10 x 200µm

10 x 200µm

10 x 10(?) µm 10 x 10(?) µm

10 x 100µm 10 x 100µm

10 x 10µm

10 x 10µm

staggered

1.5mm

5mm

staggered

Module – sensor above

Feb 2009 G Hall 21

Is it feasible to assemble modules in this orientation?(Connectors are below board in top layer)

interconnect bridges( if bump bonds needed)

25.6mm

data outcontrol in

concentrator

80mm

Module – sensor below

Feb 2009 G Hall 22

Modularity: 10 bit bus = 320 lines, 4 x 80 way connectors 4 x 80 way =>4 x 18.4mm = 73.6mm

interconnect bridges80mm

25.6mm

data outcontrol in

concentrator

Module at large – schematic plan view

Feb 2009 G Hall 23

eg10mm

If accurate alignment possible, simply offset connectors, and add routing

Comparison logic

Feb 2009 G Hall 24

p = ∞

IP

• Modules are flat, not arcs• Compensate for Lorentz drift• Orientation of module => position dependent logic [Anders/Mark P]

R- view

Luminous region

z view

• z offset dependent• search window to allow for luminous region and quantization => 3 pixels (if not tiny)

~200µm ~12mm = 2.5

NB position dependent logic could contribute to alignment – at expense of complexity

Data transport

Feb 2009 G Hall 25

From 32 ROC + Assemblers & 0.5% occupancy 10 data bits + 5 address bits to transmit (differential?)~2 hits/module to transfer/BX after PT match ≈ 1 hit/32 ROC8 data bit bus + 1 busy bit @ 80Mb/s ?

Power - two arguments: CMOS logic [Mark] or energy per bit [Sandro](i) 2µW/MHz/cm x 80MHz x 8cm x 8 / 4096 = 2.5 µW/channel(ii) 10pJ/bit x 16bit /25ns /4096 ≈ 1.6 µW/channel

Clock distribution?

Store data on assembler while awaiting readout

Concentrator

29 30 31282726to GBT

Control, PLL, Trigger

Data volumes and link requirements

Feb 2009 G Hall 26

for 40M channels in stacked layer

Channels/chip 128

Occupancy 0.005

PT data reduction 0.050

Channels above PT cut/BX/layer 5,000

Bits/channel 16

No links @ 3.2Gbps [new] 1000

Power/link [W] 2.0

Link Power [kW] 2.0

Power/chan [µW] 50

Assume 16 bits/chip to transfer and trigger data from one layer Options – following trigger

(1)no further readout

(2) read out unmatched patterns saved in Assembler (choose top or bottom layer) more power: logic & to send data more links and traffic management extra data volume for rejection factor 20 ≈ (40MHz/20 + 100kHz)/(40MHz/20) = 1.05 (3) read out all datarequires 6.4µs storage on each FE pixelmemory in ROC FEsignificant extra power penalty & complexity

Power estimate• Budget for PT layer: <120µW/chan using 130nm CMOS

– Front end 30µW (amp, threshold, logic, data transfer)– GBT Links 50µW (not on module) – Control, PLL 10µW [*]– Digital logic 250µW x 64/8192 = 2µW (guess)

• little logic in pixel, comparison logic and data transfer on assembler

– Data transfer 2.5µW – Data transfer to remote GBT @ 160Mbps [ref: B Meier] 2hits x 16 bits x 10pJ/bit x 160Mbps x 2m = 102mW/8192 = 12.5µWTotal: 107µW/channel ≈ 0.6 W/module locally (exc

link)Option (2): increase by ~ 5% => 112µW/channel Option (3): for full readout => ??

Feb 2009 G Hall 27

* Ancillary chips in present tracker typically required 50mW => 20mW in 130nm Assume one PLL per side => 20mW/(32*128) = 5µW

Approximate dimensions

R [cm]

L [m]

A [m2]

Nface Nchan NROC Nmodule Nlinks P [kw]

25 3.0 9.6 64 38.5M 150k 4700 960 4.6

35 4.2 18.7 88 75M 293k 9200 1875 9.0

Feb 2009 G Hall 28

For stacked layer (doublet)

Pixel size 100µm x 2.5mm

ROC 2 x 128 channels

<Power>/pixel 120µW

|MAX| 2.5

NB no allowance for overlaps in R-or Simulations use 0.5-1mm overlap in -> +8% [Mark P]

≈ number of APV25sproduced and testedfor present Tracker

Conclusions

• The crucial issue is the assembly & interconnect problem– do layers need to be precisely aligned – ie sub-100µm?– is it feasible to use connectors?

• Density of lines on module and connections to sensors suggest bump bonding will be required– but “inexpensive” C4 looks feasible

• Power consumption for layer is still dominated by data transmission off the detector– this is very sensitive to occupancy and rejection factor– it probably will be remote from module

Feb 2009 G Hall 29